CN202957237U - Chip encapsulation structure - Google Patents
Chip encapsulation structure Download PDFInfo
- Publication number
- CN202957237U CN202957237U CN2012206804686U CN201220680468U CN202957237U CN 202957237 U CN202957237 U CN 202957237U CN 2012206804686 U CN2012206804686 U CN 2012206804686U CN 201220680468 U CN201220680468 U CN 201220680468U CN 202957237 U CN202957237 U CN 202957237U
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- CN
- China
- Prior art keywords
- chip
- coil
- pin
- substrate
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model provides a chip encapsulation structure. The chip encapsulation structure at comprises a substrate, wherein a chip and a pin frame are arranged on the substrate, and the chip is positioned in the pin frame; at least one conductive pad is arranged at the periphery of the chip; the pin frame is provided with at least one pin; each conductive pad is connected with a pin; and a coil surrounds the periphery of the pin frame and is insulated from the pin frame. By the chip encapsulation structure, certain special chip conductive pads can be electrically connected to the substrate and the coil, so that the manufacturing cost is reduced, and the encapsulation period is shortened.
Description
Technical field
The utility model relates to a kind of field of semiconductor manufacture, particularly relates to a kind of chip-packaging structure.
Background technology
In semiconductor industry, the semiconductor production flow process is tested after by wafer manufacture, wafer sort, chip package and encapsulation and is formed.The downstream of chip package process in whole semiconductor manufacturing process, encapsulation is necessary for chip, is also vital.Encapsulation is that the shell that semiconductor integrated circuit chip is used is installed, and it not only plays a part protection chip and increased thermal conductivity energy, but also is to link up chip internal circuit and the bridge of external circuit and the effect of specification general utility functions.Typical packaging technology flow process comprises: scribing, load, bonding, plastic packaging, pin plating, pin Trim Molding, outside polishing and packaging body lettering etc.Divide the semiconductor packages form according to material used, comprise metallic packaging, ceramic packaging, metal-ceramic package and Plastic Package.Semiconductor package types also can be divided into DIP, QFP, PGA, BGA etc.DIP(Double In-line Package wherein) refer to the integrated circuit (IC) chip that adopts the encapsulation of dual-in-line form, most middle small scale integrated circuits all adopt this packing forms, and its number of pins generally is no more than 100.The chip of DIP encapsulation has two row's pins, is distributed in both sides, and is in line and is arranged in parallel, and leg diameter and spacing are 2.54 mm(100 mil), need to be inserted on the chip carrier socket with DIP structure.On the circuit board that certainly, also can directly be inserted in identical welding hole number and arrange for how much, welded.The plug-in mounting mode of DIP has short and advantage cheaply of encapsulation time.
For EEPROM electric erasable program read-only memory, PDIP48 is that current product reliability is tested the most frequently used encapsulated type, has 48 packaging pins.In semiconductor packaging process, it is a kind of technology for conductive pad on semiconductor chip is connected with electrical property between packaging pin that routing engages (wire bonding).When no more than 48 of the conductive pad of chip, the PDIP48 encapsulated type can meet the encapsulation requirement of chip, completes the time of one week that approximately only needs from the wafer coupons to the encapsulation.And be greater than 48 chip for conductive pad quantity, because the packaging pin number is limited, so the chip conductive pad that can be connected on pin is just limited, can't carry out with the encapsulation of PDIP48 the various application of chip with regard to making like this, mode that can only be more complicated with other is carried out, and has greatly increased cost of manufacture and test period.
Therefore, how to enlarge the range of application of PDIP48 encapsulation, reducing cost of manufacture and shortening the encapsulation cycle is the problem that those skilled in the art need to solve.
The utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of chip-packaging structure, for solve prior art due to packaging pin quantity not and can't be by the problem that on chip, all conductive pads connect.
Reach for achieving the above object other relevant purposes, the utility model provides a kind of chip-packaging structure, and described encapsulating structure at least comprises: substrate, and this substrate is provided with chip and leadframe, and described chip is located at described leadframe inside; Described chip edge arranges at least one conductive pad; Described leadframe has at least one pin; Each conductive pad connects a pin; Coil, be centered around described leadframe around, between described coil and described leadframe, insulate.
Preferably, described encapsulating structure also comprises the ring body for mark, and described ring body is positioned on described coil, with described leadframe, with coil, insulate and contacts respectively.
Preferably, described conductive pad directly is electrically connected by the first bonding wire and a pin, and described the first bonding wire is gold thread.
Preferably, described conductive pad directly is electrically connected by the second bonding wire and substrate, and substrate and a pin are electrically connected, and described the second bonding wire is gold thread.
Preferably, described conductive pad directly is electrically connected by the 3rd bonding wire and coil, and coil and a pin are electrically connected, and described the 3rd bonding wire is gold thread.
Preferably, the material of described coil is gold copper-base alloy.
Preferably, described coil is located in substrate, and described coil contacts with the substrate insulation.
Preferably, described chip according to the routing angle adjustment of the first bonding wire from intrabasement position.
As mentioned above, chip-packaging structure of the present utility model, there is following beneficial effect: for the encapsulation that on chip, conductive pad quantity is greater than 48, some special conductive pads can be electrically connected on described substrate and coil, like this, in the situation that it is constant to remain potted number of pins, complete the connection of all conductive pads on chip, reduce cost of manufacture and shortened the encapsulation cycle.
The accompanying drawing explanation
Fig. 1 is shown as chip-packaging structure schematic diagram of the present utility model.
The element numbers explanation
Embodiment
Below by particular specific embodiment, execution mode of the present utility model is described, person skilled in the art scholar can understand other advantages of the present utility model and effect easily by the disclosed content of this specification.
Refer to Fig. 1.Notice, appended graphic the illustrated structure of this specification, ratio, size etc., equal contents in order to coordinate specification to disclose only, understand and read for person skilled in the art scholar, not in order to limit the enforceable qualifications of the utility model, therefore the technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under the effect that the utility model can produce and the purpose that can reach, all should still drop on the technology contents that the utility model discloses and obtain in the scope that can contain.Simultaneously, in this specification, quote as " on ", D score, " left side ", " right side ", " centre " reach the term of " " etc., also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the utility model, the change of its relativeness or adjustment, under without essence change technology contents, when also being considered as the enforceable category of the utility model.
As shown in Figure 1, the utility model provides a kind of chip-packaging structure, and described encapsulating structure at least comprises: substrate 1 ' and coil 2 '.
Described substrate 1 ' is provided with chip 11 ' and leadframe 12 ', and described chip 11 ' is located at the inside of described leadframe 12 '.
Described chip 11 ' edge arranges at least one conductive pad 111 '.In the present embodiment, conductive pad 111 ' quantity, for being greater than 48, guarantees insulation between conductive pad 111 '.The Facing material of described conductive pad 111 ' is aluminium, but is not limited to this.
Described leadframe 12 ' has at least one pin.In the present embodiment, the quantity of leadframe 12 ' upper pin is 48, and pin 1 ~ 48 as shown in Figure 1, and a described conductive pad 111 ' connects a pin, and the different conductive pads 111 ' that are connected on pin have different electrical property states.
Described conductive pad 111 ' directly is electrical connected by the first bonding wire 3 ' and a pin, and the first bonding wire 3 ' that connects different electrical property states can not interlock in space.Described the first bonding wire 3 ' is formed gold thread, copper cash, aluminum steel or silver-colored line etc. in line connection process.The present embodiment is preferably gold thread.
It is upper that described chip 11 ' adheres to described substrate 1 ', and the material that adheres to described chip 11 ' comprises allly can adhere to the binding agent in substrate 1 ' by chip 11 '.The position of described chip 11 ' in substrate 1 ' can be according to the angle adjustment of the routing of the first bonding wire 3 ' from the position of substrate 1 ', and in the present embodiment, described chip 11 ' sticks to the center of substrate 1 ', as shown in Figure 1.
Described conductive pad 111 ' directly is electrical connected by the second bonding wire 4 ' and substrate 1 ', and the electrical property state of all the second bonding wires 4 ' outputs that is connected to substrate 1 ' is identical.It should be noted that, substrate 1 ' is except with conductive pad 111 ' is connected, and substrate 1 ' also is electrically connected with a pin.As shown in Figure 1, pin 26 on leadframe 12 ' is electrically connected with substrate 1 ', like this, and all conductive pads that are connected with substrate 1 ' 111 ' and pin 26 conductings, again by pin 26 by the electrical property State-output to external pin, external pin is dual inline type (diagram).Described the second bonding wire 4 ' is gold thread, but is not limited to this.
Described coil 2 ' be centered around described leadframe 12 ' around, between this coil 2 ' and described leadframe 12 ' insulation.Described coil 2 ' has certain plane width, is convenient to bonding wire and connects.Described coil 2 ' is electrically connected by the 3rd bonding wire 5 ' and the conductive pad 111 ' on chip 11 ', and the electrical property state of all the 3rd bonding wires 5 ' outputs that is connected to described coil 2 ' is identical.It should be noted that, coil 2 ' is except with conductive pad 111 ' is connected, and coil 2 ' also is electrically connected with a pin.As shown in Figure 1, being electrically connected with coil 2 ' of the pin 27 on leadframe 12 ', like this, all conductive pads that are connected with coil 2 ' 111 ' and pin 27 conductings, then pass through pin 27 by the electrical property State-output to external pin.Described the 3rd bonding wire 5 ' is gold thread, but is not limited to this.The material of described coil 2 ' is gold, copper, aluminium or silver.The present embodiment is preferably gold copper-base alloy.
In addition, it is upper that described coil 2 ' is located at substrate 1 ', and described coil 2 ' contacts with substrate 1 ' insulation.Certainly, it is upper that coil 2 ' is not limited to be located at substrate 1 ', so long as can carry coil 2 ' and the carrier that contacts with coil 2 ' insulation gets final product.
The bonding wire connection of the conductive pad had in Fig. 1 is illustrated, but those skilled in the art should understand that.
Described encapsulating structure also comprises the ring body 6 ' for mark, is positioned at described coil 2 ' upper, with described leadframe 12 ' insulation, contacts.As shown in Figure 1, can know the position of all pins by described ring body 6 ', be convenient to the exact connect ion of chip and external circuit.
It should be noted that, described chip-packaging structure also comprises seal, top cover etc.Described chip-packaging structure is configurable on a circuit board, with other element on circuit board, is connected to form the electronic installation with specific function.
In sum, the chip-packaging structure that the utility model provides, be greater than the encapsulation of number of pins for conductive pad quantity on chip, some special conductive pads can be electrically connected on described substrate and coil, like this, in the situation that it is constant to remain potted number of pins, completed the connection of all conductive pads on the chip, reduce cost of manufacture and shortened the encapsulation cycle.So the utility model has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all can, under spirit of the present utility model and category, be modified or be changed above-described embodiment.Therefore, have in technical field under such as and usually know that the knowledgeable modifies or changes not breaking away from all equivalences that complete under spirit that the utility model discloses and technological thought, must be contained by claim of the present utility model.
Claims (8)
1. a chip-packaging structure, is characterized in that, described encapsulating structure at least comprises:
Substrate, this substrate is provided with chip and leadframe, and described chip is located at described leadframe inside;
Described chip edge arranges at least one conductive pad; Described leadframe has at least one pin; Each conductive pad connects a pin;
Coil, be centered around described leadframe around, between described coil and described leadframe, insulate.
2. chip-packaging structure according to claim 1, it is characterized in that: described encapsulating structure also comprises the ring body for mark, described ring body is positioned on described coil, with described leadframe, with coil, insulate and contacts respectively.
3. chip-packaging structure according to claim 1, it is characterized in that: described conductive pad directly is electrically connected by the first bonding wire and a pin, and described the first bonding wire is gold thread.
4. chip-packaging structure according to claim 1, it is characterized in that: described conductive pad directly is electrically connected by the second bonding wire and substrate, and substrate and a pin are electrically connected, and described the second bonding wire is gold thread.
5. chip-packaging structure according to claim 1, it is characterized in that: described conductive pad directly is electrically connected by the 3rd bonding wire and coil, and coil and a pin are electrically connected, and described the 3rd bonding wire is gold thread.
6. chip-packaging structure according to claim 1, it is characterized in that: the material of described coil is gold copper-base alloy.
7. chip-packaging structure according to claim 1, it is characterized in that: described coil is located in substrate, and described coil contacts with the substrate insulation.
8. chip-packaging structure according to claim 1 is characterized in that: described chip according to the routing angle adjustment of the first bonding wire from intrabasement position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012206804686U CN202957237U (en) | 2012-12-11 | 2012-12-11 | Chip encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012206804686U CN202957237U (en) | 2012-12-11 | 2012-12-11 | Chip encapsulation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202957237U true CN202957237U (en) | 2013-05-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012206804686U Expired - Fee Related CN202957237U (en) | 2012-12-11 | 2012-12-11 | Chip encapsulation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202957237U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117263A (en) * | 2013-01-31 | 2013-05-22 | 建荣集成电路科技(珠海)有限公司 | Integrated circuit package |
-
2012
- 2012-12-11 CN CN2012206804686U patent/CN202957237U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117263A (en) * | 2013-01-31 | 2013-05-22 | 建荣集成电路科技(珠海)有限公司 | Integrated circuit package |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130529 Termination date: 20181211 |