CN203367360U - Wafer-level-chip packaging structure of silicon-based BGA - Google Patents
Wafer-level-chip packaging structure of silicon-based BGA Download PDFInfo
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- CN203367360U CN203367360U CN 201320401404 CN201320401404U CN203367360U CN 203367360 U CN203367360 U CN 203367360U CN 201320401404 CN201320401404 CN 201320401404 CN 201320401404 U CN201320401404 U CN 201320401404U CN 203367360 U CN203367360 U CN 203367360U
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Abstract
The utility model relates to a wafer-level-chip packaging structure of a silicon-based BGA (ball grid array) and the structure belongs to the technical field of semiconductor chip packaging. The structure comprises a plurality of IC chips (100), a wafer (200) and a plurality of solder ball bumps (300). Chip bodies (110) of the IC chips (100) are provided with chip electrodes (111). The surface of a silicon-based body (210) of the wafer (200) is covered with an insulating layer (220). The surface of the insulating layer (220) is provided with a re-wiring metal wiring layer (230). The surface of the re-wiring metal wiring layer (230) is provided with a dielectric layer (240). The solder-ball bumps (300) are distributed in a BGA. Electrical-signal connection of the IC chips (100) with the solder ball bumps (300) are realized through a design of metal wirings in the re-wiring metal wiring layer (230). The utility model provides the wafer-level-chip packaging structure of the silicon-based BGA and the structure is small in pin distance and packaging size, large in pin number and low in packaging cost and realizes multi-chip packaging.
Description
Technical field
The utility model relates to the wafer level chip-packaging structure of a kind of silica-based BGA, belongs to the semiconductor die package technical field.
Background technology
Along with the develop rapidly of semicon industry, Electronic Packaging has become an importance of whole industry development.The development of the encapsulation technology of decades, make miniaturization and highdensity encapsulation requirement become the main flow direction of Electronic Packaging industry.
Adopt at present single chips encapsulation technology can't meet industry demand gradually, wafer level packaging is adopted by industry gradually as a kind of novel packaged type.But, from current known situation, be limited to the SMT(surface mount) and the PCB(printed circuit board (PCB)) technique, traditional wafer level packaging has following deficiency:
1, the pin-pitch great majority of current chip encapsulation can only be confined to 0.4mm and 0.5mm, make wafer factory must consider last part technology, thereby can't utilize the advanced technologies of wafer factory self to do little by the size of chip;
2, the chip number on individual disk can't increase, and manufacture and the packaging cost of chip are larger;
3,, for the chip of many pins, utilize wafer level packaging also can't realize.
The utility model content
The purpose of this utility model is to overcome above-mentioned deficiency, provides that a kind of pin-pitch is little, the pin number is many, package dimension is little, the wafer level chip-packaging structure of multi-chip package, silica-based BGA that packaging cost is low.
The purpose of this utility model is achieved in that
The wafer level chip-packaging structure of a kind of silica-based BGA, it comprises several IC chips, disk and several solder bumps, the chip body of described IC chip is provided with chip electrode, the surface coverage insulating barrier of the silica-based body of described disk, the surface of described insulating barrier arranges wiring metal routing layer again, the surface of the described routing layer of wiring metal again arranges dielectric layer
Form dielectric layer opening on described dielectric layer, described dielectric layer opening comprises the dielectric layer opening I and is distributed in dielectric layer opening I several dielectric layer opening II on every side, in described dielectric layer opening I described IC chip by the metal micro structure upside-down mounting in the surface of wiring metal routing layer again, described metal micro structure comprises metal column and is arranged on the metal dimpling point at metal column top, described IC chip and wiring metal routing layer again, spatial placement inserts between dielectric layer, described dielectric layer opening II is ball grid array and distributes, described solder bumps is distributed in the dielectric layer opening II, and be connected with the surface of wiring metal routing layer again, described solder bumps is ball grid array and distributes, described IC chip realizes that with solder bumps the signal of telecommunication is connected by the design of the metal routing in wiring metal routing layer again.
Further, also comprise and plant sphere, describedly plant the surface that spheric is formed in the routing layer of wiring metal again in the dielectric layer opening II, described solder bumps is connected with wiring metal routing layer again by planting sphere.
Further, described metal micro structure is arranged at the surface of chip electrode.
Further, the number of described chip electrode is more than two.
Further, the number of described metal micro structure is more than two.
Further, the spacing of described metal micro structure is less than 0.4mm.
Further, the spacing of described metal micro structure is 0.05 ~ 0.3 mm.
The effect that the utility model is useful is:
1, encapsulating structure of the present utility model is arranged in several IC chips on disk by upside-down mounting, the pin of IC chip is that metal micro structure can accomplish that by wafer level technique spacing is less than 0.4mm, preferably, the spacing of metal micro structure is 0.05 ~ 0.3 mm, many pins, multi-chip package have been realized, effectively overcome the SMT(surface mount) and the PCB(printed circuit board (PCB)) process limitations, met the requirement of high density and small-sized package.
2, solder bumps of the present utility model is ball grid array (BGA) distribution, the IC chip realizes that with solder bumps the signal of telecommunication is connected by the design of the metal routing in wiring metal routing layer again, this encapsulating structure provides the solution of face battle array wiring, contributes to be applied in the encapsulation field higher to semaphore request.
3, the chip body of this encapsulating structure and silica-based body are silicon substrate, are distributed in the upper and lower sides of this encapsulating structure, and thermal coefficient of expansion is basic identical, can improve the reliability of whole packaging body; Simultaneously, silicon substrate is cheap, has reduced whole packaging cost, meets the requirement of industry development.
4, this encapsulating structure on the routing layer of wiring metal again of disk, has reduced the route of signal transmission by the direct upside-down mounting of chip to greatest extent, has effectively promoted the stability of transfer of data, has reduced encapsulation volume simultaneously.
The accompanying drawing explanation
The front view of the wafer level packaging that Fig. 1 is a kind of silica-based BGA of the utility model.
Fig. 2 and Fig. 3 are respectively the A-A cutaway view of the amplification of Fig. 1.
In figure:
Metal micro structure 120
Metal dimpling point 122
Silica-based body 210
The wiring metal routing layer 230 again
Dielectric layer opening I 241
Dielectric layer opening II 242
Inserts 400.
Embodiment
Referring to Fig. 1 and Fig. 2, the wafer level chip-packaging structure of a kind of silica-based BGA of the utility model, it comprises several IC chips 100, disk 200 and several solder bumps 300.The chip body 110 of IC chip 100 is provided with two above chip electrodes 111.The surface coverage insulating barrier 220 of the silica-based body 210 of described disk 200, described insulating barrier 220 is silicon oxide layer or polymer material layer.The surface of described insulating barrier 220 arranges wiring metal routing layer 230 again, and the material of the described routing layer of wiring metal again 230 is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.The surface of the described routing layer of wiring metal again 230 arranges the dielectric layer 240 with photolithographic characteristics resin.Mode by exposure and development forms dielectric layer opening on dielectric layer 240, described dielectric layer opening comprises dielectric layer opening I 241 and is distributed in dielectric layer opening I 241 several dielectric layer opening II 242 on every side, the setting position of dielectric layer opening I 241 arranges according to actual needs, can be arranged on the central authorities of disk 200, also can secundly.In dielectric layer opening I 241, several IC chips 100 are arranged according to actual needs, and by metal micro structure 120 upside-down mountings in the surface of wiring metal routing layer 230 again.Described metal micro structure 120 is formed at the surface of chip electrode 111 by techniques such as sputter, photoetching and/or plating, its number is more than two.Described metal micro structure 120 comprises metal column 121 and the metal dimpling point 122 that is arranged on metal column 121 tops, and the material of described metal column 121 is copper or nickel, and the material of described metal dimpling point 122 is tin or ashbury metal.By wafer level technique, the spacing of metal micro structure 120 can accomplish to be less than 0.4mm, preferably, the spacing of metal micro structure 120 can reach 0.05 ~ 0.3 mm, thereby has realized that many pins are the chip package of a plurality of metal micro structures 120 or small size, superchip encapsulation.
Described IC chip 100 and inserts 400 such as spatial placement epoxy resin between wiring metal routing layer 230, dielectric layer 240 again, inserts 400 is solidified forming after heating.Described dielectric layer opening II 242 is ball grid array (BGA) and distributes, and described solder bumps 300 is distributed in dielectric layer opening II 242, and is welded in the surface of wiring metal routing layer 230 again.Described solder bumps 300 also is ball grid array (BGA) and distributes, as shown in Figure 1.During work, IC chip 100 realizes that by the design of the metal routing in wiring metal routing layer again 230 and solder bumps 300 signal of telecommunication is connected (the cabling situation of the metal routing that the not shown routing layer of wiring metal again 230 is interior).
Another embodiment of the wafer level chip-packaging structure of a kind of silica-based BGA, it also comprises plants sphere 310, as shown in Figure 3.The described sphere 310 of planting is formed at the surface of the routing layer of wiring metal again 230 in dielectric layer opening II 242 by exposure and the mode of developing, described solder bumps 300 is connected with wiring metal routing layer 230 again by planting the ball reflux type planting sphere 310.Plant sphere 310 and can strengthen solder bumps 300 and wiring metal routing layer 230 bonding strengths again, improve the reliability of whole encapsulating structure.Described solder bumps 300 also is ball grid array (BGA) and distributes.
Claims (7)
1. the wafer level chip-packaging structure of a silica-based BGA, it comprises several IC chips (100), disk (200) and several solder bumps (300), the chip body (110) of described IC chip (100) is provided with chip electrode (111), the surface coverage insulating barrier (220) of the silica-based body (210) of described disk (200), the surface of described insulating barrier (220) arranges wiring metal routing layer (230) again, the surface of the described routing layer of wiring metal again (230) arranges dielectric layer (240)
It is characterized in that: the upper dielectric layer opening that forms of described dielectric layer (240), described dielectric layer opening comprises dielectric layer opening I (241) and is distributed in dielectric layer opening I (241) several dielectric layer opening II (242) on every side, in described dielectric layer opening I (241) described IC chip (100) by metal micro structure (120) upside-down mounting in the surface of wiring metal routing layer (230) again, described metal micro structure (120) comprises metal column (121) and is arranged on the metal dimpling point (122) at metal column (121) top, described IC chip (100) and wiring metal routing layer (230) again, spatial placement inserts (400) between dielectric layer (240), described dielectric layer opening II (242) is ball grid array and distributes, described solder bumps (300) is distributed in dielectric layer opening II (242), and be connected with the surface of wiring metal routing layer (230) again, described solder bumps (300) is ball grid array and distributes, described IC chip (100) realizes that with solder bumps (300) signal of telecommunication is connected by the design of the metal routing in wiring metal routing layer (230) again.
2. the wafer level chip-packaging structure of a kind of silica-based BGA according to claim 1, it is characterized in that: also comprise and plant sphere (310), describedly plant the surface that sphere (310) is formed at the routing layer of wiring metal again (230) in dielectric layer opening II (242), described solder bumps (300) is connected with wiring metal routing layer (230) again by planting sphere (310).
3. the wafer level chip-packaging structure of a kind of silica-based BGA according to claim 1, it is characterized in that: described metal micro structure (120) is arranged at the surface of chip electrode (111).
4. according to the wafer level chip-packaging structure of claim 1 or 3 described a kind of silica-based BGA, it is characterized in that: the number of described chip electrode (111) is more than two.
5. according to the wafer level chip-packaging structure of claim 1 or 3 described a kind of silica-based BGA, it is characterized in that: the number of described metal micro structure (120) is more than two.
6. the wafer level chip-packaging structure of a kind of silica-based BGA according to claim 5, it is characterized in that: the spacing of described metal micro structure (120) is less than 0.4mm.
7. the wafer level chip-packaging structure of a kind of silica-based BGA according to claim 6, it is characterized in that: the spacing of described metal micro structure (120) is 0.05 ~ 0.3 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320401404 CN203367360U (en) | 2013-07-08 | 2013-07-08 | Wafer-level-chip packaging structure of silicon-based BGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320401404 CN203367360U (en) | 2013-07-08 | 2013-07-08 | Wafer-level-chip packaging structure of silicon-based BGA |
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| Publication Number | Publication Date |
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| CN203367360U true CN203367360U (en) | 2013-12-25 |
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| CN 201320401404 Expired - Lifetime CN203367360U (en) | 2013-07-08 | 2013-07-08 | Wafer-level-chip packaging structure of silicon-based BGA |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118817A (en) * | 2015-09-10 | 2015-12-02 | 江阴长电先进封装有限公司 | Encapsulation structure of low-cost silicon-based module and encapsulation method of encapsulation structure |
| CN105226040A (en) * | 2015-09-10 | 2016-01-06 | 江阴长电先进封装有限公司 | A kind of encapsulating structure of silica-based module and method for packing thereof |
| CN107403735A (en) * | 2016-05-20 | 2017-11-28 | 无锡天芯互联科技有限公司 | A kind of eMCP modular structures and preparation method |
| CN113140520A (en) * | 2020-01-19 | 2021-07-20 | 江苏长电科技股份有限公司 | Packaging structure and forming method thereof |
-
2013
- 2013-07-08 CN CN 201320401404 patent/CN203367360U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118817A (en) * | 2015-09-10 | 2015-12-02 | 江阴长电先进封装有限公司 | Encapsulation structure of low-cost silicon-based module and encapsulation method of encapsulation structure |
| CN105226040A (en) * | 2015-09-10 | 2016-01-06 | 江阴长电先进封装有限公司 | A kind of encapsulating structure of silica-based module and method for packing thereof |
| CN105118817B (en) * | 2015-09-10 | 2017-09-19 | 江阴长电先进封装有限公司 | A kind of encapsulating structure and its method for packing of inexpensive silicon substrate module |
| CN107403735A (en) * | 2016-05-20 | 2017-11-28 | 无锡天芯互联科技有限公司 | A kind of eMCP modular structures and preparation method |
| CN113140520A (en) * | 2020-01-19 | 2021-07-20 | 江苏长电科技股份有限公司 | Packaging structure and forming method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131225 |