CN204464262U - A kind of 3-D stacks encapsulating structure - Google Patents
A kind of 3-D stacks encapsulating structure Download PDFInfo
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- CN204464262U CN204464262U CN201520176383.8U CN201520176383U CN204464262U CN 204464262 U CN204464262 U CN 204464262U CN 201520176383 U CN201520176383 U CN 201520176383U CN 204464262 U CN204464262 U CN 204464262U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The utility model relates to a kind of 3-D stacks encapsulating structure, belongs to technical field of semiconductor encapsulation.Its chip I 1 is two or more, and transverse direction and/or genesis analysis, chip II is two or more, and transverse direction and/or genesis analysis, described chip I embeds in encapsulated member I by the back side, the upper surface of described chip I and the upper surface of encapsulated member I arrange passivation layer again, the surface of described passivation layer more optionally arranges interconnection metal layer I and encapsulated member II again, described chip II is connected with interconnection metal layer I upside-down mounting again, described encapsulated member II encapsulate chip II, interconnection metal layer I again, the upper surface of described encapsulated member II optionally arranges interconnection metal layer II and sealer again, and expose again the input/output terminal of interconnection metal layer II.The utility model provides and does not a kind ofly rely on base plate for packaging, realize multi-chip package and realize package dimension miniaturization and promote the 3-D stacks encapsulating structure of packaging density and encapsulation performance.
Description
Technical field
The utility model relates to a kind of 3-D stacks encapsulating structure, belongs to technical field of semiconductor encapsulation.
Background technology
In current semicon industry, Electronic Packaging has become an importance of industry development.The development of the encapsulation technology of decades, makes high density, main flow direction that undersized encapsulation requirement becomes encapsulation.
Along with electronic product is to thinner, lighter, higher pin density, more low cost aspect development, adopt single chips encapsulation technology cannot meet industry demand gradually, in tradition multi-chip package technology, dialogue between chip and chip is realized by substrate, namely chip signal transmission must transmit on substrate one enclose could arrive an other chip, even need transmission to printed circuit board (PCB) could realize the interchange of signal, this have lost the transmission speed of signal greatly, add the power consumption of package module, especially when various chips encapsulation forms module, the theory contradiction of the green energy resource advocated with modern society.On the other hand, multi-chip package adopts on the same substrate arrangement or existing three-dimensional stacked connection shoulder to shoulder all can cause larger package area because of substrate, cannot in response to the long-term trend of microelectronics Packaging development.
Utility model content
The purpose of this utility model is the deficiency overcoming above-mentioned process structure, provides a kind of and does not rely on base plate for packaging, realize multi-chip stacked package and realize package dimension miniaturization and promote the 3-D stacks encapsulating structure of packaging density and encapsulation performance.
the purpose of this utility model is achieved in that
A kind of 3-D stacks encapsulating structure of the utility model, it comprises the chip I and chip II that arrange face-to-face, and described chip I is two or more, and transverse direction and/or genesis analysis, described chip II is two or more, and transverse direction and/or genesis analysis,
Described chip I embeds in encapsulated member I by the back side, the front of the upper surface exposed chip I of described encapsulated member I, the front of described chip I and the upper surface of encapsulated member I arrange passivation layer again, described passivation layer again forms passivation layer opening again in the top of the chip electrode of chip I, the upper surface of the chip electrode of the described exposed chip of passivation layer opening again I
The surface of described passivation layer more optionally arranges interconnection metal layer I and encapsulated member II again, described interconnection metal layer again I passes through passivation layer opening again and is connected with the chip electrode of chip I, the upside-down mounting of described chip II to the upper surface of interconnection metal layer I again, described encapsulated member II encapsulate chip II and again interconnection metal layer I;
Upper surface in described encapsulated member II offers through hole, and described through hole is positioned at the surrounding of the chip II outside the vertical area in the front of described chip I, and the upper surface of the interconnection metal layer again I of the surrounding of through chip II,
Optionally arrange interconnection metal layer II and sealer in the upper surface of described encapsulated member II and through hole, described interconnection metal layer again II is connected with interconnection metal layer I again in the bottom of this through hole and optionally arranges the input/output terminal of interconnection metal layer II in the upper surface of this encapsulated member II again again;
The surface of the interconnection metal layer again II beyond the input/output terminal of interconnection metal layer II again described in described sealer covers and the exposed upper surface of encapsulated member II.
The utility model also comprises reinforced layer, and described reinforced layer is arranged at the lower surface of encapsulated member I, and and arranges adhesion layer between encapsulated member I.
By interconnection metal layer connection again between the adjacent described chip I of the utility model two.
By interconnection metal layer connection again between the adjacent described chip II of the utility model two.
Chip described in the utility model II is connected with interconnection metal layer I upside-down mounting again by connector I.
Connector I described in the utility model is soldered ball, welding block and/or micro-metal coupling.
The input/output terminal of interconnection metal layer again II described in the utility model arranges soldered ball, welding block and/or micro-metal coupling.
The upper surface of encapsulated member II described in the utility model is higher than the level height of chip II, and its difference in height h is 20 ~ 50 microns.
the beneficial effects of the utility model are:
The utility model discloses a kind of 3-D stacks encapsulating structure, its high density by the shaping of employing Wafer-Level Packaging Technology again interconnection metal layer connects multiple chip I and chip II, thus the base plate for packaging eliminated in conventional package, shorten the connection distance of chip chamber, again by metal column and/or another again interconnection metal layer by packaging body Signal transmissions to the input/output terminal of whole encapsulating structure, accelerate the speed of Signal transmissions;
Simultaneously, multiple chip I and chip II face-to-face cross direction profiles and/or genesis analysis are connected, instead of the packaged type of traditional larger package area, as the three-dimensional stacked connection encapsulation mode that multi-chip adopts on the same substrate array packages mode or employing substrate to be shoulder to shoulder communicated with, reduce the encapsulation volume of packaging body, achieve the miniaturization of chip package size, improve packaging density and encapsulation performance, be conducive to the propelling of Wafer-Level Packaging Technology in thin encapsulation structure, meet modern society's theory of green energy resource, thus in response to the long-term trend that microelectronics Packaging develops.
For above and other object of the present utility model, feature and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the generalized section of the embodiment of a kind of 3-D stacks encapsulating structure of the utility model;
Fig. 2 is the cross direction profiles view of Fig. 1 chips II and through hole;
Fig. 3 is Fig. 1 chips I and chip II genesis analysis view;
Wherein:
Chip I 1
Chip electrode 13
Chip electrode opening 131
Chip surface passivation layer 15
Encapsulated member I 2
Passivation layer 3 again
Passivation layer opening 31 again
Interconnection metal layer I 4 again
Chip II 5
Chip electrode 53
Chip electrode opening 531
Chip surface passivation layer 55
Interconnection metal layer II 6,61 again
Connector II 62
The input/output terminal 63 of interconnection metal layer II again
Soldered ball 67
Encapsulated member II 7
Through hole 71
Sealer 8
Reinforced layer 9
Adhesion layer 91.
Embodiment
Describe the utility model more fully hereinafter with reference to accompanying drawing now, exemplary embodiment of the present utility model shown in the drawings, thus scope of the present utility model is conveyed to those skilled in the art by the disclosure fully.But the utility model can realize in many different forms, and should not be interpreted as being limited to the embodiment set forth here.
Embodiment, see Fig. 1 to Fig. 3
As shown in Figure 1, for the generalized section of a kind of 3-D stacks encapsulating structure of the utility model, the front of the chip body of its chip I 1 is provided with chip electrode 13 and chip surface passivation layer 15, and chip surface passivation layer 15 covers the front of the chip I 1 beyond chip electrode opening 131.Encapsulating material encapsulate chip I 1 and the front of only exposed chip I 1.The material of encapsulating material is the most conventional with epoxy resin, phenolic resins, organic siliconresin and unsaturated polyester resin at present, and add the inserts such as silica, aluminium oxide wherein, to improve the performance such as intensity, electrical property, viscosity of encapsulating material, and promote the thermomechanical reliability of encapsulating structure.Encapsulating material encapsulating, solidified after, the encapsulated member I 2 in solid fraction, can play the effects such as waterproof, protection against the tide, shockproof, dust-proof, heat radiation, insulation.Usually, the upper surface of encapsulated member I 2 is not less than the front of chip I 1 in vertical direction, to be embedded in completely wherein by chip I 1.The passivation layer again 3 of silica, silicon nitride or resinae dielectric material is set at the upper surface of the front of chip I 1 and encapsulated member I 2, and form again passivation layer opening 31, with the upper surface of the chip electrode of exposed chip I 1 in the top of the chip electrode 13 of chip I 1.The surface of passivation layer 3 arranges the interconnection metal layer again I 4 adopting Wafer-Level Packaging Technology to be shaped again, the material of interconnection metal layer I 4 includes but not limited to copper again, and this is being connected with the chip electrode 13 of chip I 1 downwards by passivation layer opening 31 again of interconnection metal layer I 4 again.The upper surface of this interconnection metal layer I 4 again arranges the input/output terminal 41 of interconnection metal layer I and the input/output terminal 42 of interconnection metal layer I more again, wherein the input/output terminal 42 of interconnection metal layer I is for the chip II 5 of the face-to-face upside-down mounting of subsequent technique in chip I 1 is arranged again, the input/output terminal 41 of interconnection metal layer I is arranged at the surrounding of the input/output terminal 42 of interconnection metal layer I again again, and outside the vertical area being distributed in the front of chip I 1.Interconnection metal layer I 4 can be individual layer again, can be also multilayer, determine according to actual needs.
The front of the chip body of chip II 5 is provided with chip electrode 53 and chip surface passivation layer 55, and chip surface passivation layer 55 covers the upper surface of the chip II 5 beyond chip electrode opening 531.
The chip electrode 53 of chip II 5 realizes upside-down mounting by connector I 57 and the input/output terminal 42 of interconnection metal layer I again and is connected.Particularly, can for being grown on micro-metal coupling at chip electrode 53 place of chip II 5 perpendicular to the connector I 57 that interconnection metal layer I 4 distributes again, the lower end of micro-metal coupling is provided with solder (not shown), is connected with the input/output terminal 42 of interconnection metal layer I again to make connector I 57.The circular in cross-section of micro-metal coupling or the polygon such as quadrangle, hexagon, its material is the copper, silver, gold etc. that electric conductivity is good.Connector I 57 also can be soldered ball and/or welding block, is connected by chip II 5 with the input/output terminal 42 of interconnection metal layer I again, forms electrical communication.Encapsulated member II 7 encapsulate chip II 5, connector I 57 and interconnection metal layer I 4 again.The material of encapsulated member II 7 can be identical with the material of encapsulated member I 2, also can be different, selects according to actual needs, but can play the effects such as waterproof, protection against the tide, shockproof, dust-proof, heat radiation, insulation after its solidified forming equally.The upper surface of encapsulated member II 7 is higher than the level height of chip II 5, and its difference in height h is 20 ~ 50 microns, insulate with chip II 5 to make the interconnection metal layer again II 6 of follow-up setting.
Offer the through hole 71 of vertical interconnection metal layer I 4 again in the upper surface of encapsulated member II 7, go directly the upper surface of input/output terminal 41 of interconnection metal layer I again for the bottom of through hole 71.The cross section of through hole 71 is generally rounded.The interconnection metal layer again II 6 adopting Wafer-Level Packaging Technology to be shaped optionally is set in the upper surface of encapsulated member II 7 and the inwall of through hole 71, then the material of interconnection metal layer II 6 includes but not limited to copper.Interconnection metal layer II 6 is connected in the bottom of through hole 71 with the input/output terminal 41 of interconnection metal layer I more again.Interconnection metal layer II 6 can be individual layer again, can be also multilayer, determine according to actual needs.
The surface of interconnection metal layer II 6 optionally arranges the input/output terminal 63 of interconnection metal layer II again again.Sealer 8 covers the surface of the interconnection metal layer again II 6 beyond the input/output terminal 63 of interconnection metal layer II and the exposed upper surface of encapsulated member II 7 again.The input/output terminal 63 of interconnection metal layer II arranges soldered ball, welding block and/or micro-metal coupling again, so that be connected with pcb board or substrate.
For strengthening the intensity of whole encapsulating structure, reinforced layer 9 can also be set in the below of chip I 1, reinforced layer 9 is connected with the lower surface of encapsulated member I 2 by the adhesion layer 91 of the materials such as silica gel, the material of reinforced layer 9 is the silicon, metallic copper, iron-nickel alloy etc. with supporting role, its thickness, generally at 30 ~ 50 microns, also can thicken or its thickness thinning according to actual needs.Meanwhile, the reinforced layer 9 of the material that the thermal conductivity such as metallic copper, iron-nickel alloy is good can also be the heat radiation of whole encapsulating structure, to improve a kind of three-dimension packaging reliability of structure of the present invention.
Chip II 5 includes but not limited to IC chip, also can be any semiconductor chip.Chip II 5 can be two or more, can cross direction profiles, as shown in Figure 2, illustrates the cross direction profiles state of chip II and through hole, and figure chips II 51,52,53 tiles arrangement or arrayed, and through hole 71 is arranged in its surrounding.Can not electrical connection between two adjacent chips II 5, also can be connected by interconnection metal layer II 6 again.Equally, chip I 1 includes but not limited to IC chip, can be any semiconductor chip, and chip I 1 also can be two or more, and cross direction profiles.
Chip II 5 can be genesis analysis, and as shown in Figure 3, illustrate chip I and chip II genesis analysis state, figure chips II 51,52 is arranged above and below.Can be electrically connected between chip II 51 and chip II 52, also can by interconnection metal layer II 6 connection again.Chip I 1 also can be genesis analysis, by interconnection metal layer II 6 and/or interconnection metal layer I 4 connection more again.
During actual use, chip II 5 generally carries out longitudinal arrangement with chip I 1 while laterally arranging, by the interconnection metal layer again II 6 of laying and/or the organic connection of interconnection metal layer I 4 again between the chip be associated, three dimensions arrangement is realized in package interior to make multiple chip, improve packaging density, reduce multi-chip package size, and shorten the route of Signal transmissions to greatest extent.
A kind of 3-D stacks encapsulating structure of the utility model is not limited to above preferred embodiment, as chip I 1 can be identical with the model of chip II 5, also can be different, and determine according to actual needs.Therefore; any those skilled in the art are not departing from spirit and scope of the present utility model; the any amendment done above embodiment according to technical spirit of the present utility model, equivalent variations and modification, all fall in protection range that the utility model claim defines.
Claims (8)
1. a 3-D stacks encapsulating structure, it is characterized in that: it comprises the chip I (1) and chip II (5) that arrange face-to-face, described chip I (1) is two or more, and transverse direction and/or genesis analysis, described chip II (5) is two or more, and transverse direction and/or genesis analysis
Described chip I (1) embeds in encapsulated member I (2) by the back side, the front of the upper surface exposed chip I (1) of described encapsulated member I (2), the front of described chip I (1) and the upper surface of encapsulated member I (2) arrange passivation layer (3) again, described passivation layer again (3) forms passivation layer opening (31) in the top of the chip electrode of chip I (1) again, the upper surface of the chip electrode of described passivation layer opening again (31) exposed chip I (1)
The surface of described passivation layer again (3) optionally arranges interconnection metal layer I (4) and encapsulated member II (7) again, described interconnection metal layer again I (4) passes through passivation layer opening (31) again and is connected with the chip electrode of chip I (1), the upside-down mounting of described chip II (5) to the upper surface of interconnection metal layer I (4) again, described encapsulated member II (7) encapsulate chip II (5) and again interconnection metal layer I (4);
Upper surface in described encapsulated member II (7) offers through hole (71), described through hole (71) is positioned at the surrounding of the chip II (5) outside the vertical area in the front of described chip I (1), and the upper surface of the interconnection metal layer again I (4) of the surrounding of through chip II (5)
Optionally arrange interconnection metal layer II (6) and sealer (8) in the upper surface of described encapsulated member II (7) and through hole (71), described interconnection metal layer again II (6) is connected with interconnection metal layer I (4) again in the bottom of this through hole (71) and optionally arranges the input/output terminal (63) of interconnection metal layer II in the upper surface of this encapsulated member II (7) again again;
The surface of the interconnection metal layer again II (6) beyond the input/output terminal (63) of interconnection metal layer II again described in described sealer (8) covers and the exposed upper surface of encapsulated member II (7).
2. a kind of 3-D stacks encapsulating structure according to claim 1, it is characterized in that: also comprise reinforced layer (9), described reinforced layer (9) is arranged at the lower surface of encapsulated member I (2), and and arranges adhesion layer (91) between encapsulated member I (2).
3. a kind of 3-D stacks encapsulating structure according to claim 1 and 2, is characterized in that: by interconnection metal layer connection again between two adjacent described chips I (1).
4. a kind of 3-D stacks encapsulating structure according to claim 1 and 2, is characterized in that: by interconnection metal layer connection again between two adjacent described chips II (5).
5. a kind of 3-D stacks encapsulating structure according to claim 1 and 2, is characterized in that: described chip II (5) is connected with interconnection metal layer I (4) upside-down mounting again by connector I (57).
6. a kind of 3-D stacks encapsulating structure according to claim 5, is characterized in that: described connector I (57) is soldered ball, welding block and/or micro-metal coupling.
7. a kind of 3-D stacks encapsulating structure according to claim 1 and 2, is characterized in that: the input/output terminal (63) of described interconnection metal layer again II arranges soldered ball, welding block and/or micro-metal coupling.
8. a kind of 3-D stacks encapsulating structure according to claim 1 and 2, is characterized in that: the upper surface of described encapsulated member II (7) is higher than the level height of chip II (5), and its difference in height h is 20 ~ 50 microns.
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| CN201520176383.8U CN204464262U (en) | 2015-03-27 | 2015-03-27 | A kind of 3-D stacks encapsulating structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110739292A (en) * | 2019-09-02 | 2020-01-31 | 上海先方半导体有限公司 | 3D packaging structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110739292A (en) * | 2019-09-02 | 2020-01-31 | 上海先方半导体有限公司 | 3D packaging structure and manufacturing method thereof |
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