US20180342489A1 - Semiconductor structure and a method of making thereof - Google Patents
Semiconductor structure and a method of making thereof Download PDFInfo
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- US20180342489A1 US20180342489A1 US16/035,623 US201816035623A US2018342489A1 US 20180342489 A1 US20180342489 A1 US 20180342489A1 US 201816035623 A US201816035623 A US 201816035623A US 2018342489 A1 US2018342489 A1 US 2018342489A1
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- substrate
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- integrated circuit
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 179
- 238000000034 method Methods 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 239000012530 fluid Substances 0.000 claims description 3
- 230000005855 radiation Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims 1
- 230000001788 irregular Effects 0.000 claims 1
- 230000037361 pathway Effects 0.000 claims 1
- 230000008569 process Effects 0.000 description 26
- 230000000712 assembly Effects 0.000 description 19
- 238000000429 assembly Methods 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 238000012546 transfer Methods 0.000 description 11
- 230000008901 benefit Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 230000010354 integration Effects 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- 238000005192 partition Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
- Y10T29/53178—Chip component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
- Y10T29/53183—Multilead component
Definitions
- the subject matter herein relates to semiconductor devices and packaging of the semiconductor devices.
- a single chip is partitioned into a number of smaller chips. The smaller chips are then assembled on an interposer and wired together to form a functional chip.
- a single chip consists of a number of circuitry blocks such as memory, logic, DSP, and RF, each separated into a smaller chip. The smaller chips can be manufactured by different foundries and can be of different process nodes. The smaller chips are then assembled on an interposer and wired together to form a functional chip.
- the semiconductor industry has been transitioning from a 2D monolithic approach to a 2.5D/3D heterogeneous approach at a much slower rate than expected, mainly due to high costs.
- the high costs arise from manufacturing, poor reliability, and low yield.
- Establishing a supply chain for a 2.5D/3D device depends on the device market and volume. However, costs, reliability, and yield are the fronts that are hitting the industry the most.
- a silicon interposer is the building block and an enabler for 2.5D/3D integration, whether homogeneous or heterogeneous.
- blind vias with a diameter of 10 um are created within the wafer followed by back-grinding the wafer to 100 um nominal in order to reveal the vias from the backside, creating what is known as through-silicon vias (TSV).
- TSV through-silicon vias
- Such an interposer is known as an interposer with 10:100 aspect ratio, implying 10 um via diameter and 100 um interposer thickness. This process is called “wafer thinning and via reveal process.”
- not all of the blind vias are etched with equal depth, as there is always considerable variation in blind via depth due to process variation.
- a single chip is partitioned into multiple other chips or so-called partitions, whether homogeneous or heterogeneous. Partitions are then bumped using copper pillar bumping technology. Copper pillar is used for fine pitch bumping, normally when the bump pitch is less than 80 micron.
- a typical partition can have a bump pitch of 45 microns or smaller.
- Partitions are assembled on a thin silicon interposer with typical aspect ratio of 10:100.
- the back side of the interposer has a typical bump pitch of 150 micron or more in order to resemble the industry standard flip chip bump pitch in practice as of today and is bumped using solder bump material.
- the Silicon interposer is then assembled on a multi-layer organic build up substrate. A ball grid array (BGA) with a typical pitch of 1 mm is attached to the back side of the organic substrate.
- the organic substrate is then assembled on a printed circuit board (PCB).
- PCB printed circuit board
- the processes related to TSVs include the wafer thinning and TSV reveal process, the wafer bonding and debonding process, and the TSV copper via fill process. These three processes contribute to almost 60% of the overall cost of manufacturing.
- FIG. OA is a side view of an assembly employing through substrate vias according to prior art.
- TSVs 10 are used to transition signals 20 and supplies from the top 35 of the substrate 30 to the bottom 40 and vice versa through the substrate core thickness.
- TSVs are constrained by diameter, height, and pitch. Thus, a limited number of TSVs can be placed in a substrate, moreover, it has a negative impact on signal and power integrity.
- a method of creating a scalable 2.5D/3D structure without through substrate vias uses a via-less semiconductor interposer, a semiconductor substrate, and various combinations of wirebond, flip chip bumping, and redistribution layers (RDL) to transition signals or supplies to the bottom of the substrate.
- RDL redistribution layers
- FIGS. 1A, 1B, and 1C are side views of a stacked die structure, in accordance with one exemplary embodiment of the present invention.
- FIGS. 1E, 1F, and 1G are side views of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 1H is a top view of the assembly shown in FIG. 1G .
- FIG. 2A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 2B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 3A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 3B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 3C is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 4 illustrates arrangements of bump patterns used to create secured routing in accordance with an exemplary embodiment.
- FIG. 5A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 5B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIGS. 6A and 6B are side views of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 7 is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 8A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 8B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 9 is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 10A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 10B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention.
- FIG. 11 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment.
- FIG. 12 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment.
- FIG. 13A is a bump joint assembly between two substrates according to prior art.
- FIG. 13B is a bump joint assembly between a substrate and a die according to prior art.
- FIG. 13C is a bump joint assembly between two die according to prior art.
- FIG. 14 is a top view of a landing pad used to connect components, and side view of a plurality of holes shape and depth used to enforce a connection between components in accordance with an exemplary embodiment.
- FIG. 15A is a top view of a plurality of holes with uniform pitch, shape and depth in accordance with an exemplary embodiment.
- FIG. 15B is a top view of a plurality of holes with varying pitch, shape and depth in accordance with an exemplary embodiment.
- FIG. 16 illustrates an assembly process used to assemble mask defined components and substrates without using under bump metallization (UBM) in accordance with an exemplary embodiment.
- UBM under bump metallization
- FIG. 17 illustrates an assembly process used to assemble mask defined components and substrates in accordance with an exemplary embodiment.
- FIG. 18A illustrates a plurality of wirebonded dies placed inside a substrates cavity in accordance with an exemplary embodiment.
- FIG. 18B illustrates a plurality of wirebonded dies placed on a copper heat spreader in accordance with an exemplary embodiment.
- FIG. 19A illustrates a plurality of wirebonded dies placed side by side inside a substrate's cavity in accordance with an exemplary embodiment.
- FIG. 19B illustrates a plurality of wirebonded dies placed inside a substrate's cavity side by side and on top of each other in accordance with an exemplary embodiment.
- FIG. 19C illustrates a plurality of wirebonded dies placed side by side inside substrate cavities in accordance with an exemplary embodiment.
- FIG. 19D illustrates a plurality of wirebonded dies placed side by side and on top of each other inside substrate cavities in accordance with an exemplary embodiment.
- the semiconductor package may incorporate interposers having a multitude of redistribution layers. Relatively narrow and laterally elongated interposers to form the indentations used to house the electronic components.
- the height of the clearance may be equal to the height of the standoff interposers.
- the semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.
- the spaces and clearances may form a conduit configured to promote fluid flow and enhance cooling of the electronic components during operation in embodiments.
- the semiconductor packages described herein possess cavities and/or standoff interposers (generally referred to herein as interposer) to create spaces for a plurality of electronic components in a high density and high performance configuration.
- interposer may result in a smaller footprint, lower profile, miniaturized, higher performance thermally enhanced, and more secured packages.
- the packages may involve a combination of interposers, redistribution layers (RDL), zero-ohm links, copper pillars, solder bumps, compression bonding, and bumpless packaging.
- RDL redistribution layers
- cavities may be made into the interposer and/or substrate, and/or standoff interposers and secondary or side substrate may be used to provide spaces (clearance) for a plurality of electronic components (e.g., passives, antennas, integrated circuits or chips) in embodiments.
- the standoff interposers and secondary or side substrate may include RDL on the top and/or bottom.
- Standoff interposers may be formed, for example, by bonding multiple interposers together by thermocompression bonding or another low-profile connection technique. Oxide bonding techniques or laterally shifting any standoff interposer described herein enable wirebonds to be used to connect the standoff interposer to a printed circuit board, or substrate, or an underlying interposer in embodiments. Generally speaking, any interposer described herein may be shifted relative to the other interposers in the stack to allow the formation of wirebonds.
- the semiconductor interposer may be a silicon interposer according to embodiments.
- a method of creating a scalable 2.5D/3D structure which requires no TSVs is disclosed.
- This method uses various combinations of wirebond, flip chip bumping, redistribution layer (RDL) with or without RDL vias to transition signals or supplies
- RDL redistribution layer
- signals and supplies are routed through the RDL layers, thus eliminating TSV usage and reducing the cost of manufacturing and improving performance.
- an improved method of solder joint reliability is disclosed.
- Surfaces of assemblies disclosed herein maybe be covered with a high-Z material to create a radiation harden component.
- Electronic packages formed in the manner described herein possess improved reliability, lower cost, and higher performance due to a shortening of electrical distance and an increase in density of integrated circuit mounting locations.
- Reliability may be improved for embodiments which use the same semiconductor (e.g., silicon) for all interposer used to form the semiconductor package.
- the techniques presented also provide improved in solder joint reliability and a reduction in warpage. Warping may occur during the wafer processing and thinning of the semiconductor interposer. The second opportunity for warping occurs during the package and assembly. The chance of warping increases for larger interposer lengths and package dimensions which is currently necessary for a variety of 2.5D/3D integration applications (e.g., networking).
- the vertical density of integrated circuits may be increased which allows the horizontal area to be reduced to achieve the same performance.
- top and up will be used herein to describe portions/directions perpendicularly distal from the printed circuit board (PCB) plan and further away from the center of mass of the PCB in the perpendicular direction.
- Vertical will be used to describe items aligned in the “up” direction towards the “top.”
- Other similar terms may be used whose meanings will now be clear.
- Major planes of objects will be defined as the plane which intersects the largest area of an object such as an interposer.
- Some standoff interposers may be “aligned” in “lines” along the longest of the three dimensions and may therefore be referred to as “linear” standoff interposers.
- Electrical connections may be made between interposers (standoff or planar interposer) and the pitch of the electrical connections may be between 1 micron and 50 micron or between 10 micron and 100 micron in some embodiments. Electrical connections between neighboring semiconductor interposers herein may be direct ohmic contacts which may include direct bonding/oxide bonding or adding a small amount of metal such as a pad.
- a substrate includes metal layers, vias and other passive components used for transfer of signals.
- FIG. 1A is a side view of a TSV-less (i.e., without any through silicon vias) assembly 55 (alternatively referred to herein as structure) in accordance with an exemplary embodiment of the present invention.
- Assembly 55 is shown as including, in part, a semiconductor die 50 mounted on a interposer 90 via a multitude of electrical signal conductors (e.g., bumps).
- Interposer 90 is further shown, as including, in part, one or more redistribution layers 60 (RDL), and a substrate 70 .
- RDL redistribution layers
- FIG. 1A it is understood that layer 60 may include any number of redistribution later, collectively referred to herein as a redistribution layer.
- Redistribution layer(s) 60 is shown as including 5 metal layers 62 , 64 , 65 , 66 , 68 used to transfer signals to and from semiconductor die 50 , as described further below.
- FIG. 1B is a side view of another substrate 94 having a multitude of electrical signal conductors 99 and a cavity 96 adapted to receive assembly 55 therein.
- FIG. 1C shows assembly 55 after being disposed in cavity 94 .
- a multitude of wirebonds (two which, namely wirebonds 97 and 98 are shown in FIG. 1C ) may be used to transfer signals to and from silicon die 50 via the metal layers disposed in RDL 60 .
- a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals between silicon die 50 and substrate 94 over cavity 96 .
- a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals between silicon die 50 and substrate 94 over cavity 96 .
- layer 60 may include any number of metal layers.
- FIG. 1E is a side view of a TSV-less assembly 100 in accordance with another exemplary embodiment of the present invention.
- Assembly 100 is shown as including, in part, semiconductor dies (device) 50 and 52 mounted on interposer 90 .
- exemplary embodiment of assembly 100 is shown as including only two semiconductor devices, it is understood that an assembly, in accordance with embodiments of the present invention, may have any number of semiconductor devices.
- Semiconductor device 50 is shown as communicating with other devices, such as device 52 , or to receive voltage/current supplies via a multitude of electrical signal conductors 58 .
- semiconductor device 52 is shown as communicating with other devices, such as device 50 , or to receive voltage/current supplies via a multitude of electrical signal conductors 78 .
- Interposer 90 is further shown, as including, in part, one or more redistribution layers 60 (RDL), and a substrate 70 . Although for simplicity only one such redistribution layer is shown in FIG. 1E , it is understood that layer 60 may include any number of redistribution later. Redistribution layer(s) 60 is shown as including 5 metal layers 62 , 64 , 65 , 66 , 68 used to transfer signals to and from semiconductor devices 50 , 52 .
- FIG. 1F is a side view of a substrate 94 having a multitude of electrical signal conductors 99 and a cavity 96 adapted to receive assembly 100 therein.
- FIG. 1G shows assembly 100 after being disposed in cavity 94 .
- a multitude of wirebonds may be used to transfer signals to, from or between silicon devices 50 , 52 via the metal layers disposed in RDL 60 .
- a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals to, from or between silicon devices 50 , 52 and substrate 94 over cavity 96 .
- FIG. 1H is a top view of an exemplary embodiment of assembly 100 , showing devices 50 and 52 , top metal layers 62 , wirebonds 97 , 98 , and bonding pads 93 .
- FIG. 2A shows an assembly 210 in accordance with another embodiment of the present invention.
- Devices 227 , 229 together with interposer 225 form an assembly 235 that corresponds to and is formed in the same manner as assembly 100 shown in FIG. 1F .
- devices 230 , 240 together with interposer 220 form an assembly 245 that corresponds to and is formed in the same manner as assembly 100 shown in FIG. 1F .
- Assemblies 235 and 245 are mounted to substrate 214 to from an assembly 210 .
- Devices 229 , 227 , 240 and 230 of assembly 210 are adapted to communicate with one another via wirebonds 250 , 260 and the redistribution layers disposed in interposers 220 and 225 .
- Electrical signal conductors 233 (e.g., BGA) facilitate communication between the devices disposed in assembly 210 and devices not formed on assembly 210 .
- FIG. 2B shows an assembly 270 in accordance with another embodiment of the present invention.
- Assembly 270 is shown, as including, in part, two assemblies 235 A and 235 , each of which corresponds to assembly 235 shown in FIG. 2A .
- the devices disposed in assemblies 235 A and 235 B are adapted to communicate with one another via wirebonds 250 , 260 and the redistribution layers disposed in their respective interposers 220 and 225 .
- Electrical signal conductors 290 e.g., BGA
- substrates 275 disposed between assemblies 235 A and 235 surrounds interposers 220 and the devices mounted there to inhibit access to these devices.
- substrates 275 is disposed along one of the edges of assembly 235 to enable airflow between assemblies 235 A and 235 so as to allow for heat flow and dissipation.
- substrates 275 is disposed along one of the edges of assembly 235 to enable airflow between assemblies 235 A and 235 so as to allow for heat flow and dissipation.
- FIG. 3A is a cross-section view of stacking of interposers in accordance with an exemplary embodiment.
- An assembly 310 may include in part multiple assemblies, for example one according to assembly 105 and one according to assembly 210 , stacked and separated using a BGA 315 having a ball size and pitch appropriate for providing enough clearance so that devices of the assemblies fit and function properly.
- Assembly 210 has clearance from substrate 330 due to BGA 320 .
- FIG. 3B is a cross-section view of stacking or interposers, using larger BGA ball sizes, in accordance with an exemplary embodiment.
- An assembly 350 comprises stacked assemblies according to assembly 210 .
- BGAs 340 and 345 provide clearance for the stacked assemblies between one another and substrate 355 .
- BGAs 340 and 345 have a larger ball size and pitch, appropriate for providing enough clearance so that devices of the assemblies fit and function properly.
- FIG. 3C is a cross-section view of stacking of interposers, using smaller BGA ball sizes, in accordance with an exemplary embodiment.
- An assembly 360 comprises stacked assemblies according to assembly 210 . The two assemblies are shown as separated by a thin side-substrate 380 and BGAs having smaller ball size and pitch. Larger BGA 370 provides clearance from substrate 390 .
- FIG. 4 illustrates arrangements of bump patterns used to mask critical signals and/or supplies in accordance with an exemplary embodiment.
- Bump pattern 420 includes in part critical signals or supplies 460 and non-critical signals or supplies 470 .
- critical signal/supply bumps 460 or traces may be shielded against probing or tampering by placing the critical signal or supply bumps on an inner most line of bumps, namely bumps 441 - 446 while the non-critical signals or supplies 470 are placed on an outer most line of bumps.
- bump pattern 410 includes in part critical signals or supplies 440 , and non-critical signals or supplies 430 , 450 .
- signals 451 - 457 are shielded from probing or tampering by placing these signals on innermost line of the bumps.
- critical signals or supplies 440 may be positioned on a line of bumps between the non-critical signals or supplies 430 and 450 .
- FIG. 5A is an exemplary embodiment of an assembly in accordance with another exemplary embodiment of the present invention.
- Substrate 94 is adapted to have a cavity 95 adapted to receive assembly 100 (See FIG. 1E ) and cavities 520 disposed either along the periphery or opposite edges of substrate 94 to receive bumps 538 also formed on assembly 538 . Since bumps 58 , 78 , and 538 are fully embedded within the walls of substrate 94 , the signals used by devices 50 and 52 are shielded from tampering.
- FIG. 5B shows various components of FIG. 5A after they have been assembled together to form assembly 540 .
- FIGS. 6A and 6B are respectively similar to FIGS. 5A and 5B except that in FIGS. 6A and 6B , bumps 538 are not placed in a cavity.
- FIG. 7 shows two assemblies 640 (see FIG. 6B ) that are stacked together but separated via substrate 710 .
- the assembly shown in FIG. 8B is similar to that shown in FIG. 8A except that in the assembly of FIG. 8B , semiconductor devices 50 , 52 , interposer 90 , and a portion of each of substrates 45 , 48 is disposed on a copper layer 550 . The remaining portions of substrates 45 and 48 are disposed on substrates 552 and 554 . Substrate 94 is disposed above devices 50 , 52 and substrates 45 , 48 . Bumps 560 are used to transfer signals to or from devices 50 , 52 to bumps 99 for communication with devices external to the assembly. It is understood that transfer of signals between bumps 560 and 99 is facilitated through signal traces formed in PCB or substrate 94 using vias, and the like.
- the assembly of FIG. 9 is similar to that shown in FIG. 8B except that in FIG. 9 wirebonds 935 are used to transfer signals between various metal layers disposed in interposer 90 and bumps 560 .
- FIG. 10A is an exemplary embodiment of an assembly 1000 , in accordance with another embodiment of the present invention.
- Assembly 1000 includes, in part, a pair of substrates 94 A and 94 B (each corresponding to substrate 90 as described above). Each substrate has a cavity formed on its top and bottom surfaces.
- substrate 90 A is shown as including a cavity 96 A top formed on its top surface and a cavity 96 A bottom formed on its bottom surface.
- substrate 90 B is shown as including a cavity 96 B top formed on its top surface and a cavity 96 B bottom formed on its bottom surface.
- Interposer 90 A top has devices 50 A top , 52 A top as well as substrates 45 A top , 48 A top disposed thereon.
- Interposer 90 A bottom has devices 50 A bottom , 52 A bottom as well as substrates 45 A bottom , 48 A bottom disposed thereon.
- Interposers 90 B top and 90 B bottom have similar devices and substrates thereon as shown.
- Bumps 610 , 620 , 630 and 640 together with substrates 45 A top , 48 A top 45 A bottom , 48 A bottom are used to facilitate signal transfer between the devices shown as well as devices external to assembly 1000 .
- a copper heat spreader is disposed below substrates 45 A bottom , 48 A bottom and devices 50 A bottom and 52 A bottom . It is understood however, that a copper hear spreader may be disposed in other layers.
- FIG. 10B illustrates stacking and scaling up low profile thermally enhanced and secured interconnects in accordance with an exemplary embodiment.
- an interposer 1055 is attached to a copper heat spreader 1060 which is attached to side substrate 1065 .
- interposer 1055 does not have any TSVs.
- a secondary flip chip substrate 1070 is used to route the signals and supplies from the interposer 1055 the side-substrate 1065 .
- wirebonds are used to connect the interposer 1055 to the side-substrate 1065 instead of secondary flip chip substrates 1070 .
- FIG. 11 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment.
- Substrate connector 1140 includes an array of fine pitch bumps 1130 and an array of coarse pitch bumps 1120 .
- a gap 1110 between the fine pitch bumps 1130 and the coarse pitch bumps 1120 provides a bridge for connecting over a cavity.
- FIG. 12 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment.
- Substrate connector 1140 includes a first array of fine pitch bumps 1130 and a second array of fine pitch bumps 1150 .
- a gap 1110 between the first array of fine pitch bumps 1130 and the second array of fine pitch bumps 1150 provides a bridge for connecting over a cavity.
- FIG. 13A is a bump joint assembly between two substrates according to prior art. Substrate 1320 and substrate 1310 are connected using bump 1330 .
- FIG. 13B is a bump joint assembly between a substrate and a die according to prior art. Substrate 1320 and die 1340 are connected using bump 1330 .
- FIG. 13C is a bump joint assembly between two die according to prior art. Die 1340 and die 1350 are connected using bump 1330 .
- FIG. 14 is a top view of a landing pad used to connect components, and side view of a plurality of holes shape and depth used to enforce a connection between components in accordance with an exemplary embodiment.
- Landing pad 1410 includes a hole 1420 .
- Landing pad 1410 can also include a hole 1430 that has a different shape and depth than hole 1420 .
- landing pad 1410 can have a hole 1440 that has a different shape and depth than holes 1420 and 1430 .
- FIG. 15A is a top view of a plurality of holes with uniform pitch, shape and depth in accordance with an exemplary embodiment.
- Landing pad 1510 includes an array of holes 1515 , each having the same pitch, shape, and depth.
- FIG. 15B is a top view of a plurality of holes with varying pitch, shape and depth in accordance with an exemplary embodiment.
- Landing pad 1520 includes an array of holes, including holes 1530 , 1540 , 1550 and 1560 having varying pitch, shape, and depth.
- FIG. 16 illustrates an assembly process used to assemble mask defined components and substrates without under bump metallization (UBM) in accordance with an exemplary embodiment.
- Components 1610 and 1620 are assembled using bumps 1630 and 1640 and spaced apart by spacers 1660 .
- the bumps 1630 and 1640 are placed partially inside a through hole with proper depth. After process reflow, the bumps 1630 and 1640 are melted and joined together to form a connection 1670 between the components 1610 and 1620 .
- FIG. 17 illustrates an assembly process used to assemble mask defined components and substrates in accordance with an exemplary embodiment.
- Components 1710 and 1720 are assembled together using bumps 1730 and 1740 .
- Conductive material 1750 partially fills a mask defined hole. After a reflow the bumps 1730 and 1740 are melted and joined together to form a connection between components 1710 and 1720 .
- FIG. 18A illustrates a plurality of wirebonded dies placed inside a substrate cavity in accordance with an exemplary embodiment.
- Assembly 1810 includes a substrate 1820 with a cavity 1825 created therein.
- Devices 1830 and 1835 are wirebonded 1840 to substrate 1820 .
- FIG. 18B illustrates a plurality of wirebonded dies placed on a copper heat spreader in accordance with an exemplary embodiment.
- devices 1860 and 1865 are placed on a copper heat spreader 1855 (or substrate) and wirebonded 1885 to substrate 1870 .
- a substrate 1875 is assembled to substrate 1870 using bumps 1880 .
- FIG. 19A illustrates a plurality of wirebonded dies placed side by side inside a substrate cavity in accordance with an exemplary embodiment.
- Assembly 1910 includes a stack of assemblies having a substrate 1915 with a cavity 1920 created therein. Multiple devices 1925 can be placed in the cavity 1920 and wirebonded 1930 to the substrate 1915 . Assemblies are stacked and separated using bumps 1935 .
- FIG. 19B illustrates a plurality of wirebonded dies placed inside a substrate cavity side by side and on top of each other in accordance with an exemplary embodiment.
- Assembly 1940 is similar to assembly 1910 , except multiple devices 1945 are placed on top of one another within the substrate cavity.
- FIG. 19C illustrates a plurality of wirebonded dies placed side by side inside substrate cavities in accordance with an exemplary embodiment.
- Assembly 1950 comprises multiple stacked assemblies, each including a substrate having multiple cavities created therein. Devices are placed side by side within the cavities and are wirebonded to the substrate.
- FIG. 19D illustrates a plurality of wirebonded dies placed side by side and on top of each other inside substrate cavities in accordance with an exemplary embodiment.
- Assembly 1960 comprises multiple stacked assemblies and is similar to assembly 1950 except multiple devices are placed on top of one another within the substrate cavities.
Abstract
Description
- This application claims the benefit of priority to and is a continuation of U.S. patent application Ser. No. 15/164,866 filed May 25, 2016 (pending), the content of which is incorporated herein by reference in its entirety.
- This application claims the benefit of priority under 35 U.S.C. § 119(e) to U.S. provisional application Ser. No. 62/166,123 filed May 25, 2015 (now expired), the content of which is incorporated herein by reference in its entirety.
- The present application claims the benefit of priority to and is a continuation in part of U.S. patent application Ser. No. 14/717,798 filed May 20, 2015 now U.S. Pat. No. 9,893,004 (issued on Feb. 13, 2018), the content of which is incorporated herein by reference in its entirety.
- This application claims the benefit of priority to and is a continuation in part of U.S. patent application Ser. No. 14/746,045 filed Jun. 22, 2015 now U.S. Pat. No. 9,818,680 (issued on Nov. 14, 2017), the content of which is incorporated herein by reference in its entirety.
- Application Ser. No. 14/746,045 claims the benefit of priority under 35 U.S.C. § 119(e) to U.S. provisional application Ser. No. 62/015,459 filed Jun. 22, 2014 (now expired), the content of which is incorporated herein by reference in its entirety.
- Application Ser. No. 14/717,798 claims the benefit of priority under 35 U.S.C. § 119(e) to U.S. provisional application Ser. No. 62/002,794 filed May 24, 2014 (now expired), the content of which is incorporated herein by reference in its entirety.
- Application Ser. No. 14/717,798 claims the benefit of priority to and is a continuation in part of U.S. patent application Ser. No. 13/192,217 filed Jul. 27, 2011, the content of which is incorporated herein by reference in its entirety.
- Application Ser. No. 13/192,217 claims the benefit of priority to and is a continuation of U.S. patent application Ser. No. 12/205,875 filed Sep. 6, 2008 now U.S. Pat. No. 8,014,166 (issued on Sep. 6, 2011), the content of which is incorporated herein by reference in its entirety.
- The subject matter herein relates to semiconductor devices and packaging of the semiconductor devices.
- As Moore's law approaches its demise and the cost per transistor increases below the 22 nm node, device makers are pushed to seek alternative solutions to achieve higher yield, shorter interconnect length, lower delays, lower power, smaller footprint, reduced weight and higher performance. In a homogeneous 2.5D/3D integration approach, a single chip is partitioned into a number of smaller chips. The smaller chips are then assembled on an interposer and wired together to form a functional chip. In a heterogeneous 2.5D/3D integration approach, a single chip consists of a number of circuitry blocks such as memory, logic, DSP, and RF, each separated into a smaller chip. The smaller chips can be manufactured by different foundries and can be of different process nodes. The smaller chips are then assembled on an interposer and wired together to form a functional chip.
- The semiconductor industry has been transitioning from a 2D monolithic approach to a 2.5D/3D heterogeneous approach at a much slower rate than expected, mainly due to high costs. The high costs arise from manufacturing, poor reliability, and low yield. Establishing a supply chain for a 2.5D/3D device depends on the device market and volume. However, costs, reliability, and yield are the fronts that are hitting the industry the most.
- A silicon interposer is the building block and an enabler for 2.5D/3D integration, whether homogeneous or heterogeneous. In a conventional silicon interposer manufacturing flow, blind vias with a diameter of 10 um are created within the wafer followed by back-grinding the wafer to 100 um nominal in order to reveal the vias from the backside, creating what is known as through-silicon vias (TSV). Such an interposer is known as an interposer with 10:100 aspect ratio, implying 10 um via diameter and 100 um interposer thickness. This process is called “wafer thinning and via reveal process.” In reality, not all of the blind vias are etched with equal depth, as there is always considerable variation in blind via depth due to process variation. With more than 2 um variation in blind via depth, considerable contamination occurs during the back-grind process in order to reveal all of the blind vias. In general, thinning and the via reveal process has proven to have a tremendously negative impact on the yield and has given the 2.5D/3D integration a reputation as a costly process that is justified only if the market demands the technology and can absorb the associated cost.
- As mentioned above, in a conventional 2.5D/3D integration and assembly, a single chip is partitioned into multiple other chips or so-called partitions, whether homogeneous or heterogeneous. Partitions are then bumped using copper pillar bumping technology. Copper pillar is used for fine pitch bumping, normally when the bump pitch is less than 80 micron. A typical partition can have a bump pitch of 45 microns or smaller. Partitions are assembled on a thin silicon interposer with typical aspect ratio of 10:100. The back side of the interposer has a typical bump pitch of 150 micron or more in order to resemble the industry standard flip chip bump pitch in practice as of today and is bumped using solder bump material. The Silicon interposer is then assembled on a multi-layer organic build up substrate. A ball grid array (BGA) with a typical pitch of 1 mm is attached to the back side of the organic substrate. The organic substrate is then assembled on a printed circuit board (PCB).
- The conventional silicon interposer TSV manufacturing process with sequential bumping and assemblies has resulted in a costly platform which has inhibited the launch of 2.5D/3D products in many market sectors.
- According to industry sources, 40% of the cost associated with manufacturing a silicon interposer is attributed to wafer thinning and the back-grinding via reveal process. A recent independent study sheds light on the cost break down of processing steps required for manufacturing a conventional 31×31 mm2, 100 um thin silicon interposer with 12 um TSV diameter, 3 copper damascene RDL layers with 65 nm design rule for routing on the top layer. According to the study, 19% of the cost contribution is attributed to the wafer thinning and TSV reveal process, 20% to wafer bonding/debonding process, 19% to TSV filling process, 18% to RDL process, 13% to via etching process and only 5% to the bumping process.
- The processes related to TSVs include the wafer thinning and TSV reveal process, the wafer bonding and debonding process, and the TSV copper via fill process. These three processes contribute to almost 60% of the overall cost of manufacturing.
- Interposers in practice today consist of redistribution layers (RDL), RDL vias, and through substrate/silicon vias (TSVs). Figure OA is a side view of an assembly employing through substrate vias according to prior art. TSVs 10 are used to transition signals 20 and supplies from the top 35 of the substrate 30 to the bottom 40 and vice versa through the substrate core thickness. TSVs are constrained by diameter, height, and pitch. Thus, a limited number of TSVs can be placed in a substrate, moreover, it has a negative impact on signal and power integrity.
- A method of creating a scalable 2.5D/3D structure without through substrate vias is disclosed. The method uses a via-less semiconductor interposer, a semiconductor substrate, and various combinations of wirebond, flip chip bumping, and redistribution layers (RDL) to transition signals or supplies to the bottom of the substrate.
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FIGS. 1A, 1B, and 1C are side views of a stacked die structure, in accordance with one exemplary embodiment of the present invention. -
FIGS. 1E, 1F, and 1G are side views of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 1H is a top view of the assembly shown inFIG. 1G . -
FIG. 2A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 2B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 3A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 3B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 3C is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 4 illustrates arrangements of bump patterns used to create secured routing in accordance with an exemplary embodiment. -
FIG. 5A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 5B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIGS. 6A and 6B are side views of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 7 is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 8A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 8B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 9 is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 10A is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 10B is a side view of an assembly, in accordance with one exemplary embodiment of the present invention. -
FIG. 11 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment. -
FIG. 12 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment. -
FIG. 13A is a bump joint assembly between two substrates according to prior art. -
FIG. 13B is a bump joint assembly between a substrate and a die according to prior art. -
FIG. 13C is a bump joint assembly between two die according to prior art. -
FIG. 14 is a top view of a landing pad used to connect components, and side view of a plurality of holes shape and depth used to enforce a connection between components in accordance with an exemplary embodiment. -
FIG. 15A is a top view of a plurality of holes with uniform pitch, shape and depth in accordance with an exemplary embodiment. -
FIG. 15B is a top view of a plurality of holes with varying pitch, shape and depth in accordance with an exemplary embodiment. -
FIG. 16 illustrates an assembly process used to assemble mask defined components and substrates without using under bump metallization (UBM) in accordance with an exemplary embodiment. -
FIG. 17 illustrates an assembly process used to assemble mask defined components and substrates in accordance with an exemplary embodiment. -
FIG. 18A illustrates a plurality of wirebonded dies placed inside a substrates cavity in accordance with an exemplary embodiment. -
FIG. 18B illustrates a plurality of wirebonded dies placed on a copper heat spreader in accordance with an exemplary embodiment. -
FIG. 19A illustrates a plurality of wirebonded dies placed side by side inside a substrate's cavity in accordance with an exemplary embodiment. -
FIG. 19B illustrates a plurality of wirebonded dies placed inside a substrate's cavity side by side and on top of each other in accordance with an exemplary embodiment. -
FIG. 19C illustrates a plurality of wirebonded dies placed side by side inside substrate cavities in accordance with an exemplary embodiment. -
FIG. 19D illustrates a plurality of wirebonded dies placed side by side and on top of each other inside substrate cavities in accordance with an exemplary embodiment. - The various embodiments are described more fully with reference to the accompanying drawings. These example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to readers of this specification having knowledge in the technical field. Like numbers refer to like elements throughout.
- Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers having a multitude of redistribution layers. Relatively narrow and laterally elongated interposers to form the indentations used to house the electronic components. The height of the clearance may be equal to the height of the standoff interposers. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products. The spaces and clearances may form a conduit configured to promote fluid flow and enhance cooling of the electronic components during operation in embodiments.
- In some embodiments, the semiconductor packages described herein possess cavities and/or standoff interposers (generally referred to herein as interposer) to create spaces for a plurality of electronic components in a high density and high performance configuration. In some embodiments, the semiconductor packages described may result in a smaller footprint, lower profile, miniaturized, higher performance thermally enhanced, and more secured packages. The packages may involve a combination of interposers, redistribution layers (RDL), zero-ohm links, copper pillars, solder bumps, compression bonding, and bumpless packaging. In addition to these techniques, cavities may be made into the interposer and/or substrate, and/or standoff interposers and secondary or side substrate may be used to provide spaces (clearance) for a plurality of electronic components (e.g., passives, antennas, integrated circuits or chips) in embodiments. The standoff interposers and secondary or side substrate may include RDL on the top and/or bottom. Standoff interposers may be formed, for example, by bonding multiple interposers together by thermocompression bonding or another low-profile connection technique. Oxide bonding techniques or laterally shifting any standoff interposer described herein enable wirebonds to be used to connect the standoff interposer to a printed circuit board, or substrate, or an underlying interposer in embodiments. Generally speaking, any interposer described herein may be shifted relative to the other interposers in the stack to allow the formation of wirebonds. The semiconductor interposer may be a silicon interposer according to embodiments.
- A method of creating a scalable 2.5D/3D structure which requires no TSVs is disclosed. This method uses various combinations of wirebond, flip chip bumping, redistribution layer (RDL) with or without RDL vias to transition signals or supplies In other words, signals and supplies are routed through the RDL layers, thus eliminating TSV usage and reducing the cost of manufacturing and improving performance. In addition, an improved method of solder joint reliability is disclosed. Surfaces of assemblies disclosed herein maybe be covered with a high-Z material to create a radiation harden component.
- Electronic packages formed in the manner described herein possess improved reliability, lower cost, and higher performance due to a shortening of electrical distance and an increase in density of integrated circuit mounting locations. Reliability may be improved for embodiments which use the same semiconductor (e.g., silicon) for all interposer used to form the semiconductor package. The techniques presented also provide improved in solder joint reliability and a reduction in warpage. Warping may occur during the wafer processing and thinning of the semiconductor interposer. The second opportunity for warping occurs during the package and assembly. The chance of warping increases for larger interposer lengths and package dimensions which is currently necessary for a variety of 2.5D/3D integration applications (e.g., networking). The vertical density of integrated circuits may be increased which allows the horizontal area to be reduced to achieve the same performance.
- When describing all embodiments herein, “top” and “up” will be used herein to describe portions/directions perpendicularly distal from the printed circuit board (PCB) plan and further away from the center of mass of the PCB in the perpendicular direction. “Vertical” will be used to describe items aligned in the “up” direction towards the “top.” Other similar terms may be used whose meanings will now be clear. “Major planes” of objects will be defined as the plane which intersects the largest area of an object such as an interposer. Some standoff interposers may be “aligned” in “lines” along the longest of the three dimensions and may therefore be referred to as “linear” standoff interposers. Electrical connections may be made between interposers (standoff or planar interposer) and the pitch of the electrical connections may be between 1 micron and 50 micron or between 10 micron and 100 micron in some embodiments. Electrical connections between neighboring semiconductor interposers herein may be direct ohmic contacts which may include direct bonding/oxide bonding or adding a small amount of metal such as a pad. In the following it is understood that a substrate includes metal layers, vias and other passive components used for transfer of signals.
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FIG. 1A is a side view of a TSV-less (i.e., without any through silicon vias) assembly 55 (alternatively referred to herein as structure) in accordance with an exemplary embodiment of the present invention.Assembly 55 is shown as including, in part, asemiconductor die 50 mounted on ainterposer 90 via a multitude of electrical signal conductors (e.g., bumps).Interposer 90 is further shown, as including, in part, one or more redistribution layers 60 (RDL), and asubstrate 70. Although for simplicity only one such redistribution layer is shown inFIG. 1A , it is understood thatlayer 60 may include any number of redistribution later, collectively referred to herein as a redistribution layer. - Redistribution layer(s) 60 is shown as including 5
metal layers FIG. 1B is a side view of anothersubstrate 94 having a multitude ofelectrical signal conductors 99 and acavity 96 adapted to receiveassembly 55 therein.FIG. 1C shows assembly 55 after being disposed incavity 94. A multitude of wirebonds (two which, namely wirebonds 97 and 98 are shown inFIG. 1C ) may be used to transfer signals to and from silicon die 50 via the metal layers disposed inRDL 60. Alternatively, a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals between silicon die 50 andsubstrate 94 overcavity 96. Although for simplicity only five metal layers are shown inredistribution layer 60, it is understood thatlayer 60 may include any number of metal layers. -
FIG. 1E is a side view of aTSV-less assembly 100 in accordance with another exemplary embodiment of the present invention.Assembly 100 is shown as including, in part, semiconductor dies (device) 50 and 52 mounted oninterposer 90. Although exemplary embodiment ofassembly 100 is shown as including only two semiconductor devices, it is understood that an assembly, in accordance with embodiments of the present invention, may have any number of semiconductor devices. -
Semiconductor device 50 is shown as communicating with other devices, such asdevice 52, or to receive voltage/current supplies via a multitude ofelectrical signal conductors 58. Likewise,semiconductor device 52 is shown as communicating with other devices, such asdevice 50, or to receive voltage/current supplies via a multitude ofelectrical signal conductors 78.Interposer 90 is further shown, as including, in part, one or more redistribution layers 60 (RDL), and asubstrate 70. Although for simplicity only one such redistribution layer is shown inFIG. 1E , it is understood thatlayer 60 may include any number of redistribution later. Redistribution layer(s) 60 is shown as including 5metal layers semiconductor devices -
FIG. 1F is a side view of asubstrate 94 having a multitude ofelectrical signal conductors 99 and acavity 96 adapted to receiveassembly 100 therein.FIG. 1G shows assembly 100 after being disposed incavity 94. A multitude of wirebonds (two which, namely wirebonds 97 and 98 are shown inFIG. 1C ) may be used to transfer signals to, from or betweensilicon devices RDL 60. Alternatively, a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals to, from or betweensilicon devices substrate 94 overcavity 96. Although for simplicity only five metal layers are shown inredistribution layer 60, it is understood thatlayer 60 may include any number of metal layers.FIG. 1H is a top view of an exemplary embodiment ofassembly 100, showingdevices top metal layers 62, wirebonds 97, 98, andbonding pads 93. -
FIG. 2A shows anassembly 210 in accordance with another embodiment of the present invention.Devices interposer 225 form anassembly 235 that corresponds to and is formed in the same manner asassembly 100 shown inFIG. 1F . Similarly,devices interposer 220 form anassembly 245 that corresponds to and is formed in the same manner asassembly 100 shown inFIG. 1F .Assemblies substrate 214 to from anassembly 210.Devices assembly 210 are adapted to communicate with one another viawirebonds interposers assembly 210 and devices not formed onassembly 210. -
FIG. 2B shows anassembly 270 in accordance with another embodiment of the present invention.Assembly 270 is shown, as including, in part, twoassemblies assembly 235 shown inFIG. 2A . The devices disposed inassemblies wirebonds respective interposers assembly 270 and devices not formed onassembly 270. In one embodiment,substrates 275 disposed betweenassemblies interposers 220 and the devices mounted there to inhibit access to these devices. In yet another embodiment,substrates 275 is disposed along one of the edges ofassembly 235 to enable airflow betweenassemblies FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 2A, 2B ; accordingly, for simplicity and clarity, in the following and where applicable, only the differences between such embodiments are described. It is also understood that similar reference numbers may be used to identify the same elements in the Figures. -
FIG. 3A is a cross-section view of stacking of interposers in accordance with an exemplary embodiment. Anassembly 310 may include in part multiple assemblies, for example one according toassembly 105 and one according toassembly 210, stacked and separated using aBGA 315 having a ball size and pitch appropriate for providing enough clearance so that devices of the assemblies fit and function properly.Assembly 210 has clearance fromsubstrate 330 due toBGA 320. -
FIG. 3B is a cross-section view of stacking or interposers, using larger BGA ball sizes, in accordance with an exemplary embodiment. Anassembly 350 comprises stacked assemblies according toassembly 210.BGAs substrate 355.BGAs -
FIG. 3C is a cross-section view of stacking of interposers, using smaller BGA ball sizes, in accordance with an exemplary embodiment. Anassembly 360 comprises stacked assemblies according toassembly 210. The two assemblies are shown as separated by a thin side-substrate 380 and BGAs having smaller ball size and pitch.Larger BGA 370 provides clearance fromsubstrate 390. -
FIG. 4 illustrates arrangements of bump patterns used to mask critical signals and/or supplies in accordance with an exemplary embodiment.Bump pattern 420 includes in part critical signals orsupplies 460 and non-critical signals or supplies 470. According to one embodiment of the invention, critical signal/supply bumps 460 or traces may be shielded against probing or tampering by placing the critical signal or supply bumps on an inner most line of bumps, namely bumps 441-446 while the non-critical signals or supplies 470 are placed on an outer most line of bumps. Similarly, bumppattern 410 includes in part critical signals or supplies 440, and non-critical signals or supplies 430, 450. Similarly, signals 451-457 are shielded from probing or tampering by placing these signals on innermost line of the bumps. In another embodiment of this invention, critical signals or supplies 440 may be positioned on a line of bumps between the non-critical signals orsupplies -
FIG. 5A is an exemplary embodiment of an assembly in accordance with another exemplary embodiment of the present invention.Substrate 94 is adapted to have acavity 95 adapted to receive assembly 100 (SeeFIG. 1E ) andcavities 520 disposed either along the periphery or opposite edges ofsubstrate 94 to receivebumps 538 also formed onassembly 538. Sincebumps substrate 94, the signals used bydevices FIG. 5B shows various components ofFIG. 5A after they have been assembled together to formassembly 540.FIGS. 6A and 6B are respectively similar toFIGS. 5A and 5B except that inFIGS. 6A and 6B , bumps 538 are not placed in a cavity.FIG. 7 shows two assemblies 640 (seeFIG. 6B ) that are stacked together but separated viasubstrate 710. - The assembly shown in
FIG. 8B is similar to that shown inFIG. 8A except that in the assembly ofFIG. 8B ,semiconductor devices interposer 90, and a portion of each ofsubstrates copper layer 550. The remaining portions ofsubstrates substrates Substrate 94 is disposed abovedevices substrates Bumps 560 are used to transfer signals to or fromdevices bumps 99 for communication with devices external to the assembly. It is understood that transfer of signals betweenbumps substrate 94 using vias, and the like. The assembly ofFIG. 9 is similar to that shown inFIG. 8B except that inFIG. 9 wirebonds 935 are used to transfer signals between various metal layers disposed ininterposer 90 and bumps 560. -
FIG. 10A is an exemplary embodiment of anassembly 1000, in accordance with another embodiment of the present invention.Assembly 1000 includes, in part, a pair ofsubstrates 94A and 94B (each corresponding tosubstrate 90 as described above). Each substrate has a cavity formed on its top and bottom surfaces. For example, substrate 90A is shown as including a cavity 96Atop formed on its top surface and a cavity 96Abottom formed on its bottom surface. Likewise, substrate 90B is shown as including a cavity 96Btop formed on its top surface and a cavity 96Bbottom formed on its bottom surface. Interposer 90Atop has devices 50Atop, 52Atop as well as substrates 45Atop, 48Atop disposed thereon. Interposer 90Abottom has devices 50Abottom, 52Abottom as well as substrates 45Abottom, 48Abottom disposed thereon. Interposers 90Btop and 90Bbottom have similar devices and substrates thereon as shown.Bumps assembly 1000. InFIG. 10 , a copper heat spreader is disposed below substrates 45Abottom, 48Abottom and devices 50Abottom and 52Abottom. It is understood however, that a copper hear spreader may be disposed in other layers. -
FIG. 10B illustrates stacking and scaling up low profile thermally enhanced and secured interconnects in accordance with an exemplary embodiment. In this example, there are no cavities in thesubstrate 1050, instead aninterposer 1055 is attached to acopper heat spreader 1060 which is attached toside substrate 1065. It is understood thatinterposer 1055 does not have any TSVs. A secondaryflip chip substrate 1070 is used to route the signals and supplies from theinterposer 1055 the side-substrate 1065. In another embodiment, wirebonds are used to connect theinterposer 1055 to the side-substrate 1065 instead of secondaryflip chip substrates 1070. -
FIG. 11 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment.Substrate connector 1140 includes an array of fine pitch bumps 1130 and an array of coarse pitch bumps 1120. Agap 1110 between the fine pitch bumps 1130 and the coarse pitch bumps 1120 provides a bridge for connecting over a cavity. -
FIG. 12 is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment.Substrate connector 1140 includes a first array of fine pitch bumps 1130 and a second array of fine pitch bumps 1150. Agap 1110 between the first array of fine pitch bumps 1130 and the second array of fine pitch bumps 1150 provides a bridge for connecting over a cavity. -
FIG. 13A is a bump joint assembly between two substrates according to prior art.Substrate 1320 andsubstrate 1310 are connected usingbump 1330.FIG. 13B is a bump joint assembly between a substrate and a die according to prior art.Substrate 1320 and die 1340 are connected usingbump 1330.FIG. 13C is a bump joint assembly between two die according to prior art.Die 1340 and die 1350 are connected usingbump 1330. -
FIG. 14 is a top view of a landing pad used to connect components, and side view of a plurality of holes shape and depth used to enforce a connection between components in accordance with an exemplary embodiment.Landing pad 1410 includes ahole 1420.Landing pad 1410 can also include ahole 1430 that has a different shape and depth thanhole 1420. Similarly,landing pad 1410 can have ahole 1440 that has a different shape and depth thanholes -
FIG. 15A is a top view of a plurality of holes with uniform pitch, shape and depth in accordance with an exemplary embodiment.Landing pad 1510 includes an array ofholes 1515, each having the same pitch, shape, and depth. -
FIG. 15B is a top view of a plurality of holes with varying pitch, shape and depth in accordance with an exemplary embodiment.Landing pad 1520 includes an array of holes, includingholes -
FIG. 16 illustrates an assembly process used to assemble mask defined components and substrates without under bump metallization (UBM) in accordance with an exemplary embodiment.Components bumps spacers 1660. Thebumps bumps connection 1670 between thecomponents -
FIG. 17 illustrates an assembly process used to assemble mask defined components and substrates in accordance with an exemplary embodiment.Components bumps Conductive material 1750 partially fills a mask defined hole. After a reflow thebumps components -
FIG. 18A illustrates a plurality of wirebonded dies placed inside a substrate cavity in accordance with an exemplary embodiment.Assembly 1810 includes asubstrate 1820 with acavity 1825 created therein.Devices substrate 1820. -
FIG. 18B illustrates a plurality of wirebonded dies placed on a copper heat spreader in accordance with an exemplary embodiment. Inassembly 1850,devices substrate 1870. Asubstrate 1875 is assembled tosubstrate 1870 using bumps 1880. -
FIG. 19A illustrates a plurality of wirebonded dies placed side by side inside a substrate cavity in accordance with an exemplary embodiment.Assembly 1910 includes a stack of assemblies having asubstrate 1915 with acavity 1920 created therein.Multiple devices 1925 can be placed in thecavity 1920 and wirebonded 1930 to thesubstrate 1915. Assemblies are stacked and separated usingbumps 1935. -
FIG. 19B illustrates a plurality of wirebonded dies placed inside a substrate cavity side by side and on top of each other in accordance with an exemplary embodiment.Assembly 1940 is similar toassembly 1910, exceptmultiple devices 1945 are placed on top of one another within the substrate cavity. -
FIG. 19C illustrates a plurality of wirebonded dies placed side by side inside substrate cavities in accordance with an exemplary embodiment.Assembly 1950 comprises multiple stacked assemblies, each including a substrate having multiple cavities created therein. Devices are placed side by side within the cavities and are wirebonded to the substrate. -
FIG. 19D illustrates a plurality of wirebonded dies placed side by side and on top of each other inside substrate cavities in accordance with an exemplary embodiment. Assembly 1960 comprises multiple stacked assemblies and is similar toassembly 1950 except multiple devices are placed on top of one another within the substrate cavities. - It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
- Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosed embodiments. Additionally, a number of well-known processes and elements have not been described to avoid unnecessarily obscuring the embodiments described herein. Accordingly, the above description should not be taken as limiting the scope of the claims.
- Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the embodiments described, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
- As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a process” includes a plurality of such processes and reference to “the dielectric material” includes reference to one or more dielectric materials and equivalents thereof known to those skilled in the art, and so forth.
- Also, the words “comprise,” “comprising,” “include,” “including,” and “includes” when used in this specification and in the following claims are intended to specify the presence of stated features, integers, components, or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.
Claims (21)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/035,623 US10964676B2 (en) | 2008-09-06 | 2018-07-14 | Semiconductor structure and a method of making thereof |
US17/196,721 US11569208B2 (en) | 2015-05-20 | 2021-03-09 | Semiconductor structure and method for making thereof |
US17/959,373 US20230026177A1 (en) | 2015-05-20 | 2022-10-04 | Enhanced semiconductor structures |
US17/966,946 US20230041977A1 (en) | 2015-05-20 | 2022-10-17 | 3d heterogeneous integrations and methods of making thereof |
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/205,875 US8014166B2 (en) | 2008-09-06 | 2008-09-06 | Stacking integrated circuits containing serializer and deserializer blocks using through silicon via |
US13/192,217 US10236275B2 (en) | 2008-09-06 | 2011-07-27 | Stacking integrated circuits containing serializer and deserializer blocks using through silicon via |
US201462002794P | 2014-05-24 | 2014-05-24 | |
US201462015459P | 2014-06-22 | 2014-06-22 | |
US14/717,798 US9893004B2 (en) | 2011-07-27 | 2015-05-20 | Semiconductor interposer integration |
US201562166123P | 2015-05-25 | 2015-05-25 | |
US14/746,045 US9818680B2 (en) | 2011-07-27 | 2015-06-22 | Scalable semiconductor interposer integration |
US15/164,866 US10026720B2 (en) | 2015-05-20 | 2016-05-25 | Semiconductor structure and a method of making thereof |
US16/035,623 US10964676B2 (en) | 2008-09-06 | 2018-07-14 | Semiconductor structure and a method of making thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/164,866 Continuation US10026720B2 (en) | 2008-09-06 | 2016-05-25 | Semiconductor structure and a method of making thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/196,721 Division US11569208B2 (en) | 2015-05-20 | 2021-03-09 | Semiconductor structure and method for making thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180342489A1 true US20180342489A1 (en) | 2018-11-29 |
US10964676B2 US10964676B2 (en) | 2021-03-30 |
Family
ID=57587317
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/164,866 Active US10026720B2 (en) | 2008-09-06 | 2016-05-25 | Semiconductor structure and a method of making thereof |
US16/035,623 Active US10964676B2 (en) | 2008-09-06 | 2018-07-14 | Semiconductor structure and a method of making thereof |
US17/196,721 Active 2035-08-26 US11569208B2 (en) | 2015-05-20 | 2021-03-09 | Semiconductor structure and method for making thereof |
US17/229,866 Pending US20220293575A1 (en) | 2015-05-20 | 2021-04-14 | Secure semiconductor integration and method for making thereof |
US17/959,373 Pending US20230026177A1 (en) | 2015-05-20 | 2022-10-04 | Enhanced semiconductor structures |
US17/966,946 Pending US20230041977A1 (en) | 2015-05-20 | 2022-10-17 | 3d heterogeneous integrations and methods of making thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/164,866 Active US10026720B2 (en) | 2008-09-06 | 2016-05-25 | Semiconductor structure and a method of making thereof |
Family Applications After (4)
Application Number | Title | Priority Date | Filing Date |
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US17/959,373 Pending US20230026177A1 (en) | 2015-05-20 | 2022-10-04 | Enhanced semiconductor structures |
US17/966,946 Pending US20230041977A1 (en) | 2015-05-20 | 2022-10-17 | 3d heterogeneous integrations and methods of making thereof |
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US10026720B2 (en) | 2018-07-17 |
US11569208B2 (en) | 2023-01-31 |
US20230026177A1 (en) | 2023-01-26 |
US10964676B2 (en) | 2021-03-30 |
US20210242185A1 (en) | 2021-08-05 |
US20230041977A1 (en) | 2023-02-09 |
US20220293575A1 (en) | 2022-09-15 |
US20160372448A1 (en) | 2016-12-22 |
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