CN103681371A - Silica-based wafer level fan-out encapsulation method and silica-based wafer level fan-out encapsulation structure - Google Patents
Silica-based wafer level fan-out encapsulation method and silica-based wafer level fan-out encapsulation structure Download PDFInfo
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- CN103681371A CN103681371A CN201310729414.3A CN201310729414A CN103681371A CN 103681371 A CN103681371 A CN 103681371A CN 201310729414 A CN201310729414 A CN 201310729414A CN 103681371 A CN103681371 A CN 103681371A
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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Abstract
The invention relates to a silica-based wafer level fan-out encapsulation method and a silica-based wafer level fan-out encapsulation structure, and belongs to the technical field of semiconductor chip encapsulation. The encapsulation structure comprises a silicon base body (110) and an IC (Integrated Circuit) chip (200) with a plurality of electrodes (210), wherein each electrode (210) is provided with a plurality of metal poles/metal blocks (300), the other surface of the IC chip (200) is connected with the silicon base body (110) through adhesive (700), a plastic package layer is used for encapsulating, end faces of the metal poles/metal blocks (300) are exposed out of the plastic package layer, and the end faces of the metal poles/metal blocks (300) are provided with re-wiring metal layers (500) with independent wiring direction, adjacent re-wiring metal layers (500) extend to the outer sides of the electrodes (210), and the surfaces of the terminals of the re-wiring metal layers (500) are provided with solder ball bumps (600). According to the silica-based wafer level fan-out encapsulation method, the encapsulation structure is matched with pin pitch in posterior process, and meanwhile, wafer factories can develop the advanced process well to produce the IC chip with smaller size.
Description
Technical field
The present invention relates to a kind of silica-based wafer level fan-out method for packing and encapsulating structure thereof, belong to semiconductor die package technical field.
Background technology
Electronic Packaging has become the extremely important part of semicon industry.Nearly decades encapsulation technology development, each encapsulation factory is all using the miniaturization of encapsulation and high density as main R&D direction, large quantities of advanced persons' method for packing and encapsulating structure are applied to volume production.
As single chips encapsulation technology of extensive use, conventional package has presented packaging efficiency lowly at present gradually and cost continues soaring drawback.Wafer level packaging is as a kind of novel packaged type, because reducing significantly chip package size, and by industry-wide adoption.But any packaging technology all must be corresponding with follow-up SMT and PCB technique, and the pin pitch of wafer level WLCSP encapsulation is generally 0.4mm or 0.5mm, and this just makes wafer factory must consider the matching problem with last part technology.The restriction of the pin pitch of wafer level WLCSP encapsulation, is unfavorable for that wafer factory utilizes its advanced making technology that the size of chip is done littlely.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, provide a kind of and can match with the pin pitch of last part technology, can make wafer factory bring into play silica-based wafer level fan-out method for packing and encapsulating structure thereof that its advanced making technology is done littlely by the size of chip simultaneously.
The object of the present invention is achieved like this:
A kind of silica-based wafer level fan-out method for packing of the present invention, comprises following processing step:
IC disk with the IC chip of array arrangement is provided, on the electrode of described IC chip, forms metal column/metal derby array of vertical electrode;
By complete metal column/metal derby array IC disk thinning back side and cut into the IC chip with several metal column/metal derbies of single;
Carrier disk is provided, IC chip is bonding by Heraeus and carrier disk;
With plastic packaging material Plastic IC Packages chip, metal column/metal derby and Heraeus, and attenuate formation plastic packaging layer, the end face of metal column/metal derby exposes plastic packaging layer;
At the end face that exposes the metal column/metal derby of plastic packaging layer, interconnection metal layer is again set, on the surface of the terminal of described interconnection metal layer again, solder bumps is set;
To complete the carrier Wafer Thinning of encapsulation, and cut into the silica-based wafer level fan-out packaging structure of single.
Further, on the electrode of described IC chip, form metal column/metal derby array of vertical electrode, by following processing step, form:
1) on IC disk, apply photoresist;
2) on photoresist, by photoetching processes such as exposure, developments, on corresponding electrode, form photoresist opening figure;
3) plated metal in photoresist opening figure, and remove the invalid metal in photoresist surface by grinding;
4) with degumming process, remove remaining photoresist, expose the metal column/metal derby array on IC disk.
The silica-based wafer level fan-out packaging structure that a kind of silica-based wafer level fan-out method for packing of the present invention forms, comprise silica-based body and with the IC chip of several electrodes, several metal column/metal derbies are set on electrode described in each, and the another side of described IC chip is connected with silica-based body by Heraeus; Also comprise plastic packaging layer, described plastic packaging layer encapsulates the metal column/metal derby on IC chip, IC chip and Heraeus in the inner, the end face of described metal column/metal derby exposes plastic packaging layer, and at its end face, independently interconnection metal layer again of wiring trend is set, adjacent described interconnection metal layer again extends to electrode outside, and on the surface of the terminal of described interconnection metal layer again, solder bumps being set, the pitch L2 of the electrode of described IC chip is less than the pitch L1 of solder bumps.
Alternatively, the wire distribution distance of described interconnection metal layer is again not less than 20um.
Alternatively, the wire distribution distance of described interconnection metal layer is again 25～30um.
Alternatively, described silica-based body is tabular.
Alternatively, rounded, the rectangle of the cross section of described metal column/metal derby, hexagon or polygon.
Alternatively, described solder bumps is arranged in array.
Alternatively, the pitch L1 of described solder bumps is 0.4mm or 0.5mm.
Alternatively, described IC chip is more than two or two, and its model is identical or different.
IC chip of the present invention is connected with flat silica-based body by Heraeus, and by IC chip, metal column/metal derby and Heraeus plastic packaging in plastic packaging layer, by the trend of extending to electrode outside of interconnection metal layer again, the pitch of the electrode of expansion IC chip, forms silica-based wafer level fan-out packaging structure.IC chip passes through interconnection metal layer again and solder bumps is connected with extraneous, and silica-based body and plastic packaging layer give the enough intensity of IC chip, hardness protection.
the invention has the beneficial effects as follows:
1, encapsulation flow process of the present invention is simple, and whole encapsulation process completes by wafer level technique on disk, and production efficiency is higher, meets the trend that encapsulates industry development;
2, the present invention can make the chip realization of smaller szie match with the pin pitch of last part technology by electrode, the metal column/metal derby of IC chip and the wafer level fan-out structure that interconnection metal layer forms again, so that wafer factory brings into play its advanced making technology, the size of chip is done littlely;
3, the present invention is incorporated into pin (being the electrode of IC chip) several chips that spacing is less in a packaging body, the conventional pitch that electrode by IC chip, metal column/metal derby and the wafer level fan-out structure that interconnection metal layer forms again can be realized existing 0.4mm and 0.5mm encapsulates, can overcome SMT and PCB process limitations, realize system in package, meet the requirement of high density and small-sized package, meet the packaging trend of integrated circuit.
Accompanying drawing explanation
Fig. 1 is the flow chart of a kind of silica-based wafer level fan-out method for packing of the present invention;
Fig. 2 is the schematic diagram of the embodiment mono-of a kind of silica-based wafer level fan-out packaging structure of the present invention;
Fig. 3 is the electrode of middle IC chip of Fig. 2 and the schematic diagram of the fan-out location relation of solder bumps;
Fig. 4～Figure 13 is the schematic diagram of a kind of silica-based wafer level fan-out method for packing of the present invention (take embodiment mono-as example);
Figure 14 is the schematic diagram of the embodiment bis-of a kind of silica-based wafer level fan-out packaging structure of the present invention;
In figure:
Carrier wafer A 1,100
Silica-based body 110
IC wafer A 2
Electrode 210
Metal column/metal derby 300
Plastic packaging layer 410,410 '
Dielectric layer opening 511
Heraeus 700.
Embodiment
Referring to Fig. 1, a kind of silica-based wafer level fan-out method for packing of the present invention, comprises following processing step:
Step S101: the IC disk with the IC chip of array arrangement is provided, forms metal column/metal derby array of vertical electrode on the electrode of described IC chip;
Step S102: by complete metal column/metal derby array IC disk thinning back side and cut into the IC chip with several metal column/metal derbies of single;
Step S103: carrier disk is provided, IC chip is bonding by Heraeus and carrier disk;
Step S104: with plastic packaging material Plastic IC Packages chip, metal column/metal derby and Heraeus, and attenuate formation plastic packaging layer, the end face of metal column/metal derby exposes plastic packaging layer;
Step S105: at the end face that exposes the metal column/metal derby of plastic packaging layer, interconnection metal layer is again set, on the surface of the terminal of described interconnection metal layer again, solder bumps is set;
Step S106: will complete the carrier Wafer Thinning of encapsulation, and cut into the silica-based wafer level fan-out packaging structure of single.
A kind of silica-based wafer level fan-out method for packing of the present invention, can form following silica-based wafer level fan-out packaging structure:
Embodiment mono-, referring to Fig. 2 and Fig. 3
A kind of silica-based wafer level fan-out packaging structure of the present invention, comprises being flat silica-based body 110 and with the IC chip 200 of several electrodes 210, the pitch of electrode 210 is L2, pitch L2 because of the size of IC chip 200 or the number of electrode 210 different.The non-electrode surface of IC chip 200 is connected with silica-based body 110 by Heraeus 700, the bonding glue of the macromolecular material that Heraeus 700 is a kind of modification, play insulating effect simultaneously, can allocate flexibly according to process requirements, meet the device requirements such as some glue, glue spraying.On each electrode 210 of IC chip 200, several metal column/metal derbies 300 are set, the cross section of metal column/metal derby 300 is rounded, rectangle, hexagon or polygon, and its material is the good metals of electric conductivity such as copper, copper/nickel clad.Adopt plastic package process, metal column/metal derby 300 on IC chip 200, IC chip 200 and Heraeus 700 plastic packagings are got up, form plastic packaging layer 410, the end face of metal column/metal derby 300 exposes plastic packaging layer 410, and at its end face, independently interconnection metal layer 500 again of wiring trend is set.Adjacent interconnection metal layer again 500 extends to electrode 210 outsides, on the surface of the terminal of interconnection metal layer 500 again, solder bumps 600 is set, solder bumps 600 is arranged in array, and the pitch L1 of solder bumps 600 is fixed value, and L1 is generally 0.4mm or 0.5mm.Wafer factory utilizes its advanced making technology can the size of IC chip 200 be done more and more littlely, the pitch L2 of electrode 210 is more and more less, the wire distribution distance of interconnection metal layer 500 can accomplish to be not less than 20um more simultaneously, preferably, the wire distribution distance of interconnection metal layer 500 can be 25um～30um again, thereby realize in the situation that IC chip 200 is very little, the pitch L2 of the electrode 210 of IC chip 200 completes while being less than the pitch L1 of solder bumps 600 and the mating of back segment SMT or PCB technique equally.Interconnection metal layer 500 consists of dielectric layer and single-layer metal layer or consists of the metal level being electrically connected to each other between multilayer dielectric layer and multiple-layer stacked and adjacent layer again.In figure, take one dielectric layer 510 and layer of metal layer 520 is example.The material of multiple layer metal layer is metallic copper or titanium/copper, titanium tungsten/copper, aluminium/nickel/gold, aluminium/nickel/palladium/multi-layer metal structures such as gold.The material of dielectric layer is the resin with lithographic features, according to the actual needs of the resinous principle of each layer and technique, adjusts UV coefficient.This encapsulating structure can be connected by circuit board realizations such as solder bumps 600 and external substrate or PCB.
The silica-based wafer level fan-out method for packing of the embodiment of the present invention one, comprises following processing step:
As shown in Figure 4, provide the IC wafer A 2 with the IC chip 200 of array arrangement, its basic material is silicon, and each IC chip 200 is with several electrodes 210.
As shown in Figure 5 and Figure 6, form metal column/metal derby array of vertical electrode 210 on the electrode 210 of IC chip 200, the cross section of each metal column/metal derby 300 is rounded; Metal column/metal derby array forms by following processing step:
1) in IC wafer A 2, apply the photoresist that is not less than metal column/metal derby 300 height that will form;
2) on photoresist, by techniques such as exposure, developments, form photoresist opening figure on corresponding electrode 210, photoresist opening figure is the circle of hollow;
3) plated metal copper or metallic nickel in photoresist opening figure, and remove the invalid metal in photoresist surface by grinding, make the flush of metallic surface and photoresist;
4) with degumming process, remove remaining photoresist, form the metal column/metal derby 300 in IC wafer A 2.
By the thinning back side of above-mentioned IC wafer A 2 and cut into each of single with IC chips 200 of several metal column/metal derbies 300.
As shown in Figure 7 and Figure 8, provide carrier wafer A 1, IC chip 200 is attached in carrier wafer A 1 by Heraeus 700, IC chip 200 is arrayed in carrier wafer A 1.
As shown in Figure 9, with the said structure in 400 pairs of carrier wafer A 1 of plastic packaging material, carry out plastic packaging, plastic packaging material 400 by IC chip 200, metal column/metal derby 300 and Heraeus 700 embeddings within it.
As shown in figure 10, the plastic packaging material 400 on metal column/metal derby 300 end faces is carried out to reduction processing, until expose the end face of metal column/metal derby 300, form plastic packaging layer 410 '.
As shown in figure 11, end face at the metal column/metal derby 300 of said structure forms interconnection metal layer 500 again, the interconnection metal layer again 500 of individual layer of one dielectric layer 510 and layer of metal layer 520 of take in figure is example, and dielectric layer 510 is offered dielectric layer opening 511 in the terminal end surface of metal level 520.
As shown in figure 12, in the interior solder bumps 600 that arranges of dielectric layer opening 511, the pitch of solder bumps 600 is 0.4mm or 0.5mm.
As shown in figure 13, by carrier wafer A 1 attenuate of above-mentioned encapsulating structure, and cutting forms the silica-based wafer level fan-out packaging structure of single.
Embodiment bis-, referring to Figure 14
This embodiment bis-has similar encapsulating structure with embodiment mono-, and both differences are: the number that is arranged at the IC chip 200 of silica-based body 110 is more than two or two.IC chip 200 is arranged at a side of silica-based body 110, is two dimensional surface and arranges, and IC chip 200 models can be identical, can be also different, to realize the variation of the function of encapsulating structure.This encapsulating structure can be connected by circuit board realizations such as solder bumps 600 and external substrate or PCB.
Silica-based wafer level fan-out method for packing of the present invention and encapsulating structure thereof are not limited to above-described embodiment; any those skilled in the art without departing from the spirit and scope of the present invention; any modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all fall in the protection range that the claims in the present invention define.
Claims (10)
1. a silica-based wafer level fan-out method for packing, comprises following processing step:
Provide the IC disk (A2) with the IC chip (200) of array arrangement, at the upper metal column/metal derby array that forms vertical electrode (210) of electrode (210) of described IC chip (200);
By complete metal column/metal derby array IC disk (A2) thinning back side and cut into the IC chip (200) with several metal column/metal derbies (300) of single;
Carrier disk (A1) is provided, IC chip (200) is bonding by Heraeus (700) and carrier disk (A1);
With plastic packaging material (400) Plastic IC Packages chip (200), metal column/metal derby (300) and Heraeus (700), and attenuate formation plastic packaging layer (410), the end face of metal column/metal derby (300) exposes plastic packaging layer (410);
At the end face that exposes the metal column/metal derby (300) of plastic packaging layer (410), interconnection metal layer (500) is set again, on the surface of the terminal of described interconnection metal layer again (500), solder bumps (600) is set;
To complete carrier disk (A1) attenuate of encapsulation, and cut into the silica-based wafer level fan-out packaging structure of single.
2. silica-based wafer level fan-out method for packing according to claim 1, is characterized in that: the upper metal column/metal derby array that forms vertical electrode (210) of electrode (210) at described IC chip (200), forms by following processing step:
1) at the upper photoresist that applies of IC disk (A2);
2) on photoresist, by photoetching processes such as exposure, developments, at corresponding electrode (210), above form photoresist opening figure;
3) plated metal in photoresist opening figure, and remove the invalid metal in photoresist surface by grinding;
4) with degumming process, remove remaining photoresist, expose the metal column/metal derby array on IC disk (A2).
3. a silica-based wafer level fan-out packaging structure as claimed in claim 1 or 2, it is characterized in that: comprise silica-based body (110) and with the IC chip (200) of several electrodes (210), several metal column/metal derbies (300) are set on electrode described in each (210), and the another side of described IC chip (200) is connected with silica-based body (110) by Heraeus (700), also comprise plastic packaging layer (410), described plastic packaging layer (410) is by IC chip (200), metal column/metal derby (300) on IC chip (200) and Heraeus (700) encapsulation are in the inner, the end face of described metal column/metal derby (300) exposes plastic packaging layer (410), and at its end face, independently interconnection metal layer (500) again of wiring trend is set, adjacent described interconnection metal layer again (500) extends to electrode (210) outside, and on the surface of the terminal of described interconnection metal layer again (500), solder bumps (600) is set, the pitch L2 of the electrode (210) of described IC chip (200) is less than the pitch L1 of solder bumps (600).
4. silica-based wafer level fan-out packaging structure according to claim 3, is characterized in that: the wire distribution distance of described interconnection metal layer again (500) is not less than 20um.
5. silica-based wafer level fan-out packaging structure according to claim 4, is characterized in that: the wire distribution distance of described interconnection metal layer again (500) is 25～30um.
6. silica-based wafer level fan-out packaging structure according to claim 3, is characterized in that: described silica-based body (110) is tabular.
7. silica-based wafer level fan-out packaging structure according to claim 3, is characterized in that: the cross section of described metal column/metal derby (300) is rounded, rectangle, hexagon or polygon.
8. silica-based wafer level fan-out packaging structure according to claim 3, is characterized in that: described solder bumps (600) is arranged in array.
9. silica-based wafer level fan-out packaging structure according to claim 8, is characterized in that: the pitch L1 of described solder bumps (600) is 0.4mm or 0.5mm.
10. according to the silica-based wafer level fan-out packaging structure described in any one in claim 3 to 9, it is characterized in that: described IC chip (200) is more than two or two, and its model is identical or different.
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103527A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level semiconductor chip package process |
| CN104103529A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Fan out type square piece level semiconductor three dimension chip packaging technology |
| CN104103526A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level three-dimensional semiconductor chip package process |
| CN104576424A (en) * | 2014-12-10 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | Method for realizing fan-out wafer encapsulation by preparing bumps on chip in advance |
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| CN106098664A (en) * | 2016-06-12 | 2016-11-09 | 华天科技（昆山）电子有限公司 | A kind of embedded type semiconductor chip fan-out package structure and preparation method thereof |
| CN106257653A (en) * | 2015-06-17 | 2016-12-28 | 精材科技股份有限公司 | Wafer encapsulation body and manufacture method thereof |
| CN106373939A (en) * | 2016-11-18 | 2017-02-01 | 江阴长电先进封装有限公司 | Structure of package substrate and packaging method thereof |
| CN106920784A (en) * | 2017-03-31 | 2017-07-04 | 华进半导体封装先导技术研发中心有限公司 | The fan-out package structure and method for packing of a kind of power electronic devices |
| WO2017124670A1 (en) * | 2016-01-22 | 2017-07-27 | 中芯长电半导体（江阴）有限公司 | Packaging method and packaging structure for fan-out chip |
| CN109860065A (en) * | 2019-02-14 | 2019-06-07 | 南通通富微电子有限公司 | A kind of fan-out package method |
| CN109872979A (en) * | 2019-02-14 | 2019-06-11 | 南通通富微电子有限公司 | A kind of fan-out package device |
| CN109887848A (en) * | 2019-02-14 | 2019-06-14 | 南通通富微电子有限公司 | A kind of fan-out package method |
| CN109920765A (en) * | 2019-02-14 | 2019-06-21 | 南通通富微电子有限公司 | A kind of fan-out package device |
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| CN104103527B (en) * | 2014-07-22 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of improved fan-out square chip level semiconductor die package technique |
| CN104103529A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Fan out type square piece level semiconductor three dimension chip packaging technology |
| CN104103526A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level three-dimensional semiconductor chip package process |
| CN104103527A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level semiconductor chip package process |
| CN104103526B (en) * | 2014-07-22 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of improved fan-out square chip level 3 D semiconductor chip package process |
| CN104576424A (en) * | 2014-12-10 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | Method for realizing fan-out wafer encapsulation by preparing bumps on chip in advance |
| CN106257653A (en) * | 2015-06-17 | 2016-12-28 | 精材科技股份有限公司 | Wafer encapsulation body and manufacture method thereof |
| CN105226040A (en) * | 2015-09-10 | 2016-01-06 | 江阴长电先进封装有限公司 | A kind of encapsulating structure of silica-based module and method for packing thereof |
| US10593641B2 (en) | 2016-01-22 | 2020-03-17 | Sj Semiconductor (Jiangyin) Corporation | Package method and package structure of fan-out chip |
| WO2017124670A1 (en) * | 2016-01-22 | 2017-07-27 | 中芯长电半导体（江阴）有限公司 | Packaging method and packaging structure for fan-out chip |
| CN106098664A (en) * | 2016-06-12 | 2016-11-09 | 华天科技（昆山）电子有限公司 | A kind of embedded type semiconductor chip fan-out package structure and preparation method thereof |
| CN106373939B (en) * | 2016-11-18 | 2019-04-19 | 江阴长电先进封装有限公司 | A kind of structure and its packaging method of package substrate |
| CN106373939A (en) * | 2016-11-18 | 2017-02-01 | 江阴长电先进封装有限公司 | Structure of package substrate and packaging method thereof |
| CN106920784A (en) * | 2017-03-31 | 2017-07-04 | 华进半导体封装先导技术研发中心有限公司 | The fan-out package structure and method for packing of a kind of power electronic devices |
| WO2020147589A1 (en) * | 2019-01-15 | 2020-07-23 | 申广 | Novel manufacturing method of led chip package |
| CN109860065A (en) * | 2019-02-14 | 2019-06-07 | 南通通富微电子有限公司 | A kind of fan-out package method |
| CN109872979A (en) * | 2019-02-14 | 2019-06-11 | 南通通富微电子有限公司 | A kind of fan-out package device |
| CN109887848A (en) * | 2019-02-14 | 2019-06-14 | 南通通富微电子有限公司 | A kind of fan-out package method |
| CN109920765A (en) * | 2019-02-14 | 2019-06-21 | 南通通富微电子有限公司 | A kind of fan-out package device |
| CN112652585A (en) * | 2020-12-22 | 2021-04-13 | 东莞记忆存储科技有限公司 | Chip packaging structure and processing method thereof |
| CN112652584A (en) * | 2020-12-22 | 2021-04-13 | 东莞记忆存储科技有限公司 | DRAM chip packaging structure and processing method thereof |
| CN112820653A (en) * | 2020-12-30 | 2021-05-18 | 南通通富微电子有限公司 | Fan-out type packaging method |
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