CN106920784A - The fan-out package structure and method for packing of a kind of power electronic devices - Google Patents
The fan-out package structure and method for packing of a kind of power electronic devices Download PDFInfo
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- CN106920784A CN106920784A CN201710208788.9A CN201710208788A CN106920784A CN 106920784 A CN106920784 A CN 106920784A CN 201710208788 A CN201710208788 A CN 201710208788A CN 106920784 A CN106920784 A CN 106920784A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
The embodiment of the invention discloses the fan-out package structure and method for packing of a kind of power electronic devices, wherein the fan-out package structure of the power electronic devices includes：Chip carrier and chip, the surface bond of the back side of the chip and the chip carrier, the front of the chip have at least two electrodes and the conductive pole on the electrode；The chip is formed with plastic packaging layer, the surface of the plastic packaging layer and the flush of the conductive pole by plastic package process；The flush of dielectric layer and again wiring layer, the dielectric layer and the wiring layer again, the wiring layer again and the conductive pole directly contact are sequentially formed with the surface of the plastic packaging layer.Loss reduction the invention enables device for high-power power electronic under switching frequency high, heat dispersion is more preferable.
Description
Technical field
The present invention relates to encapsulation technology field, and in particular to a kind of fan-out package structure of power electronic devices and encapsulation
Method.
Background technology
With the progress of semiconductor fabrication process, the demand increased power electronic equipment capacity and to power electronics device
The performance and power requirement of part also more and more higher, thereby produce high pressure resistant, powerful power electronic devices.High-power electric
Electronic device has the superior functions such as high pressure, electric current are big, switching frequency is high, dynamic pressure drop is small, is applied to more and more
In all kinds of high and medium power power-converting devices, the leading device as modern power electronics technology.
Device for high-power power electronic also being devoted to high reliability, high efficiency and low-power consumption, wherein, high-power electric electricity
One of direction of sub- device low-power consumption is reduced by the switching loss that chip package is brought.For high-power electric and electronic device
Part, the method for packing for using at present includes that bilateral pin flat package (Dual Flat Package, DFP), dual inline type are sealed
Dress (Dual In-line Package, DIP) or four side pin flat package (Quad Flat Package with
Bumper, BQFP) etc., and use traditional wire bonding mode, i.e., using lametta, using heat, pressure, ultrasonic energy
To make metal lead wire and the tight soldering of substrate pads, the information mutual communication of the electric interconnection and chip chamber between chip and substrate is realized.
But as device for high-power power electronic chip is pressure-resistant and power increases, it is desirable to which what be can bear between pin is pressure-resistant
More and more higher, using the device for high-power power electronic of conventional packaging method, its integrated parameter is larger under switching frequency high, institute
The power problemses for bringing are also more and more significant.Additionally, the heat that chip is produced is difficult to be conducted from encapsulating structure, its radiating
Problem is also urgently to be resolved hurrily.
The content of the invention
In view of this, the embodiment of the present invention provides the fan-out package structure and method for packing of a kind of power electronic devices,
To solve loss and heat dissipation problem of the device for high-power power electronic under switching frequency high in the prior art.
On the one hand, a kind of fan-out package structure of power electronic devices is the embodiment of the invention provides, including：
Chip carrier and chip, the back side of chip and the surface bond of chip carrier, the front of chip have at least two
Electrode and the conductive pole on the electrode；
Chip is formed with plastic packaging layer, the surface of plastic packaging layer and the flush of conductive pole by plastic package process；
Dielectric layer and again wiring layer are sequentially formed with the surface of plastic packaging layer, the flush of dielectric layer and again wiring layer,
Wiring layer and conductive pole directly contact again.
Alternatively, the back side of chip includes eutectic weldering, sintering silver or high heat conduction with the mode of the surface bond of chip carrier
Glue is coated.
Alternatively, chip carrier includes metallic carrier, ceramic monolith and high heat conduction complex carrier.
Alternatively, chip is planar power electronic devices.
On the other hand, a kind of fan-out package method of power electronic devices is the embodiment of the invention provides, including：
A chip carrier and multiple chips are provided, the front of each chip has at least two electrodes, on each electrode
Make a conductive pole；
The back side of each chip is bonded with chip carrier, chip array is formed on chip carrier；
Plastic packaging, the surface of the plastic packaging layer of formation and the flush of conductive pole are carried out to chip by plastic package process；
Dielectric layer and again wiring layer are sequentially formed on the surface of plastic packaging layer, the flush of dielectric layer and again wiring layer,
Wiring layer and conductive pole directly contact again；
It is cut to multiple fan-out package structures without lead.
Alternatively, plastic packaging is carried out to chip by plastic package process, the surface of plastic packaging layer and the surface of conductive pole of formation are put down
Together, including：
Plastic packaging is carried out to chip by plastic package process, the conduction on plastic packaging layer covering chip and chip formed after solidification
Post；
By reduction process, the upper surface of plastic packaging layer is carried out thinning, be thinned to and expose conductive pole.
Alternatively, dielectric layer and again wiring layer are sequentially formed on the surface of plastic packaging layer, including：
Dielectric layer is formed on plastic packaging layer, perforate is etched to dielectric layer, to expose conductive pole and at least part of plastic packaging layer；
Wiring layer again is formed on the conductive pole for exposing and at least part of plastic packaging layer.
Alternatively, the back side of chip is bonded with the chip carrier, including：
The back side of chip is welded by eutectic, sintering silver or high-heat-conductivity glue are coated and is bonded with chip carrier.
Alternatively, chip carrier includes metallic carrier, ceramic monolith and high heat conduction complex carrier.
Alternatively, chip is planar power electronic devices.
The fan-out package structure and method for packing of power electronic devices provided in an embodiment of the present invention, by providing a core
Piece carrier and multiple chips, the back side of each chip are bonded with chip carrier, and chip array is formed on chip carrier；Each core
The front of piece has at least two electrodes, and a conductive pole is made on each electrode；Chip is moulded by plastic package process
Envelope, the surface of the plastic packaging layer of formation and the flush of conductive pole；Dielectric layer and again cloth are sequentially formed on the surface of plastic packaging layer
Line layer, the flush of dielectric layer and again wiring layer, then wiring layer and conductive pole directly contact；Multiple is cut to without lead
Fan-out package structure.Using above-mentioned technical method, a kind of fan-out package knot of the power electronic devices without lead is formed
Structure, the encapsulating structure directly can be fitted on circuit substrate, and the chip electrode for exposing is connected to realize the envelope with substrate pads
The electric interconnection of assembling structure and circuit substrate, therefore the power attenuation of encapsulating structure is reduced, especially for high-power electric
For electronic device, the fan-out package method of the power electronic devices without lead that the present invention is provided reduces high-power electric
Loss problem of the electronic device under switching frequency high；Additionally, in the fan-out package structure of present invention offer, chip carrier has
Conducted beneficial to the heat for producing chip, and the electrode of encapsulating structure is directly connected with the pad of circuit substrate so that
The heat that chip is produced is conducted by pad, solves the heat dissipation problem of encapsulating structure.
Brief description of the drawings
Fig. 1 is a kind of process chart of the fan-out package method of power electronic devices provided in an embodiment of the present invention；
Fig. 2 a be power electronic devices provided in an embodiment of the present invention fan-out package method in make conductive pole and cut open
Face structural representation；
Fig. 2 b are the vertical view of the fan-out package method chips carrier of power electronic devices provided in an embodiment of the present invention
Schematic diagram；
Fig. 2 c are cross-sectional views of Fig. 2 b along dotted line A-A'；
Fig. 2 d be power electronic devices provided in an embodiment of the present invention fan-out package method in formed plastic packaging layer cut open
Face structural representation；
Fig. 2 e be power electronic devices provided in an embodiment of the present invention fan-out package method in thinning plastic packaging layer cut open
Face structural representation；
Fig. 2 f be power electronic devices provided in an embodiment of the present invention fan-out package method in coating media layer cut open
Face structural representation；
Fig. 2 g are cuing open for the fan-out package method dielectric layer perforate of power electronic devices provided in an embodiment of the present invention
Face structural representation；
Fig. 2 h be power electronic devices provided in an embodiment of the present invention fan-out package method in form wiring layer again
Cross-sectional view；
Fig. 2 i be power electronic devices provided in an embodiment of the present invention fan-out package method in cuing open after cutting technique
Face structural representation；
Fig. 3 is a kind of schematic diagram of the fan-out package structure of power electronic devices provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention is illustrate only in description, accompanying drawing and not all.
Fig. 1 is a kind of process chart of the fan-out package method of power electronic devices provided in an embodiment of the present invention.
As shown in figure 1, the fan-out package method of the power electronic devices of the present embodiment offer includes：
S110, one chip carrier of offer and multiple chips, the front of each chip have at least two electrodes, in each electricity
It is extremely upper to make a conductive pole.
S120, the back side of each chip is bonded with chip carrier, chip array is formed on chip carrier.
S130, plastic packaging is carried out to chip by plastic package process, the surface of the plastic packaging layer of formation and the flush of conductive pole.
S140, plastic packaging layer surface on sequentially form dielectric layer and again wiring layer, the surface of dielectric layer and again wiring layer
Concordantly, then wiring layer and conductive pole directly contact.
S140, it is cut to multiple fan-out package structures without lead.
The fan-out package method of power electronic devices provided in an embodiment of the present invention, realizes the nothing of power electronic devices
Lead packages so that encapsulating structure directly can be fitted on circuit substrate, the chip electrode for exposing be connected with substrate pads with
The electric interconnection of the encapsulating structure and circuit substrate is realized, so as to reduce the power attenuation of encapsulating structure, especially for big
For power power electronic device, the fan-out package method without lead that the present embodiment is provided reduces high-power electric and electronic
Loss problem of the device under switching frequency high, in the method for packing that the present embodiment is provided, chip carrier is conducive to producing chip
Raw heat is conducted, and the electrode of encapsulating structure is directly connected with the pad of circuit substrate so that the heat that chip is produced
Amount is conducted by pad, solves the heat dissipation problem of encapsulating structure.
Fig. 2 a to Fig. 2 i be according to the fan-out package method of power electronic devices provided in an embodiment of the present invention each
Structural representation formed in processing step.Electricity provided in an embodiment of the present invention is specifically described with reference to Fig. 2 a to Fig. 2 i
Power electronic device is fanned out to method for packing.
First, there is provided a chip carrier 210 and multiple chips 220, the front of each chip 220 has at least two electrodes
221, the present embodiment is illustrated so that each chip 220 has three electrodes 221 as an example, and one is made on each electrode 221
Conductive pole 230, as shown in Figure 2 a, Fig. 2 a be power electronic devices provided in an embodiment of the present invention fan-out package method in make
Make the cross-sectional view of conductive pole, conductive pole 230 is formed on electrode 221, is electrically connected with electrode 221, after preventing
Continue the damage that may be caused to electrode 221 when carrying out thinning plastic packaging layer process.Alternatively, conductive pole is copper post, copper post have compared with
Electric conductivity high, can draw electrode, realize the electrical connection of electrode and external pads or other structures.
The back side of each chip 220 is bonded with chip carrier 210, and chip array is formed on chip carrier, such as Fig. 2 b
Shown, Fig. 2 b are that the vertical view of the fan-out package method chips carrier of power electronic devices provided in an embodiment of the present invention is illustrated
Figure.Fan-out package method provided in an embodiment of the present invention can be packaged to multiple chips, can on chip carrier key
Conjunction forms chip array, according to the present embodiment provide chip packaging method encapsulate after the completion of the chip array is cut with
Form single fan-out package structure.Following examples of the present invention are illustrated by taking the encapsulation process of two chips as an example.
Fig. 2 c are cross-sectional views of Fig. 2 b along dotted line A-A'.As shown in Figure 2 c, the back side of chip 220 carries with chip
Body 210 is bonded, and the front of chip 220 has three electrodes 221 and the conductive pole 230 on each electrode 221.
Alternatively, the back side of chip 220 is welded by eutectic, sintering silver or high-heat-conductivity glue are coated and is bonded with chip carrier 210.
Eutectic weldering refers to the phenomenon that eutectic solder occurs the fusion of eutectic thing at relatively low temperature, and eutectic alloy directly becomes from solid-state
To liquid, and without the plastic stage, to realize that chip is connected with the bonding of chip carrier.Sintering silver refers to by sintering silver paste
Realize that chip is connected with the bonding of chip carrier.Or being bonded for chip and chip carrier can be realized by coating high-heat-conductivity glue
Connection.In Fig. 2 c 240 can for eutectic solder, sintering silver paste or high-heat-conductivity glue, can also be other can realize chip with
The material of chip carrier bonding connection.
Alternatively, chip carrier includes metallic carrier, ceramic monolith and high heat conduction complex carrier.Metallic carrier has higher
Thermal conductivity, can by chip produce heat rapidly conduct, its material can be copper or molybdenum.Chip carrier may be used also
Being other thermal conductivitys material high, such as ceramic monolith and high heat conduction complex carrier, it is also possible to which the heat for producing chip is fast
Conduct fastly, solve the heat dissipation problem of prior art.
Alternatively, the chip in the present embodiment is planar power electronic devices, the electrode of planar power electronic devices
At grade.The fan-out package method that the present embodiment is provided can apply to third generation semi-conducting material, for example, be carbonized
Silicon substrate and gallium nitride base power power electronic device, itself have the advantages that high pressure resistant, resistance to high current, are carried using the present embodiment
After the fan-out package method of confession, while low and good heat dissipation is lost under there is switching frequency high.
Fig. 2 d be power electronic devices provided in an embodiment of the present invention fan-out package method in formed plastic packaging layer cut open
Face structural representation, as shown in Figure 2 d, plastic packaging is carried out to chip 220 by plastic package process, forms plastic packaging layer 250, shape after solidification
Into plastic packaging layer 250 thickness higher than conductive pole 230 height.
Plastic packaging is to replace a kind of technology of metal, glass or ceramics encapsulating electronic component with plastics, and plastic package process can be with
Lower the manufacturing cost of chip package, save noble metal and alloy, the weight of encapsulating structure can be mitigated again.Conventional capsulation material
Including epoxies capsulation material and silicone capsulation material, the hardness of epoxies capsulation material is high, and wearability is good, high pressure resistant；Silicon
The heat endurance of ketone capsulation material is good, and reliability is high, and the capsulation material in the present embodiment can use above-mentioned one of both.
Fig. 2 e be power electronic devices provided in an embodiment of the present invention fan-out package method in thinning plastic packaging layer cut open
Face structural representation, as shown in Figure 2 e, by reduction process, carries out thinning to the upper surface of plastic packaging layer 250, is thinned to and exposes electricity
Conductive pole 230 on pole 221, to the damage of electrode 221 when conductive pole 230 can prevent thinning.
Fig. 2 f be power electronic devices provided in an embodiment of the present invention fan-out package method in coating media layer cut open
Face structural representation, as shown in figure 2f, dielectric layer 260 is formed on the plastic packaging layer 250 after thinning.
Fig. 2 g are cuing open for the fan-out package method dielectric layer perforate of power electronic devices provided in an embodiment of the present invention
Face structural representation.As shown in Figure 2 g, perforate is etched to dielectric layer 260, to expose conductive pole 230 and at least part of plastic packaging layer.
Fig. 2 h be power electronic devices provided in an embodiment of the present invention fan-out package method in form wiring layer again
Cross-sectional view, as shown in fig. 2h, by electroplating technology, makes wiring layer 270 again, then wiring layer 270 on chip 220
With the directly contact of conductive pole 230.The flush of wiring layer 270 and dielectric layer 260 again so that encapsulating structure surfacing, just
In laminating.
Fig. 2 i be power electronic devices provided in an embodiment of the present invention fan-out package method in cuing open after cutting technique
Face structural representation, is cut to multiple fan-out package structures 200 without lead.Alternatively, each fan-out package knot
A chip 220 can be included in structure 200, will chip array cut into the encapsulating structure with single chip；Or, each
Chip array can be cut into many according to the actual requirements comprising multiple chips 220 in fan-out package structure 200
The encapsulating structure of chip.
So far, the encapsulation of power electronic devices is completed, the fan-out package structure without lead is formed, can be by the encapsulation knot
Structure is directly fitted on circuit substrate, and the wiring layer again for exposing directly is connected with substrate pads, therefore reduces encapsulating structure
Power attenuation, especially for device for high-power power electronic for, reduce its loss problem under switching frequency high；This
Outward, in the encapsulating structure that the present invention is provided, chip carrier is conducive to conducting the heat that chip is produced, and encapsulating structure
Wiring layer again be directly connected with the pad of circuit substrate so that chip produce heat conducted by pad, solve
The heat dissipation problem of encapsulating structure.
Fig. 3 is a kind of schematic diagram of the fan-out package structure of power electronic devices provided in an embodiment of the present invention, this reality
The encapsulating structure for applying example offer is formed according to the encapsulation of above-mentioned method for packing, and the encapsulating structure includes：
Chip carrier 310 and chip 320, the back side of chip 320 and the surface bond of chip carrier 310, chip 321 is just
Face has at least two electrodes 321 and the conductive pole on the electrode 330；
Chip 320 is formed with plastic packaging layer 350 by plastic package process, and the surface of plastic packaging layer 350 is put down with the surface of conductive pole 330
Together；
Dielectric layer 360 and again wiring layer 370, again dielectric layer 360 and wiring layer are sequentially formed with the surface of plastic packaging layer 350
370 flush, then wiring layer 370 and the directly contact of conductive pole 330.
Alternatively, the mode of the surface bond of the back side of chip 320 and chip carrier 310 include eutectic weldering, sintering silver or
High-heat-conductivity glue is coated.
Alternatively, chip carrier 310 includes metallic carrier, ceramic monolith and high heat conduction complex carrier.
Alternatively, chip 320 is planar power electronic devices.
Above-mentioned encapsulating structure can perform the method that any embodiment of the present invention is provided, and the encapsulating structure has and above-mentioned core
The method for packing identical beneficial effect of piece, the encapsulating structure is the encapsulating structure without lead, can directly be fitted in circuit base
On plate, the chip electrode for exposing is connected to realize the electric interconnection of the encapsulating structure and circuit substrate, therefore drop with substrate pads
The low power attenuation of encapsulating structure, especially for device for high-power power electronic for, reduce high-power electric and electronic
Loss problem of the chip under switching frequency high；Additionally, in the fan-out package structure of present invention offer, chip carrier is conducive to
The heat that chip is produced is conducted, and the chip electrode of encapsulating structure is directly connected with the pad of circuit substrate so that
The heat that chip is produced is conducted by pad, solves the heat dissipation problem of encapsulating structure.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
More other Equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. the fan-out package structure of a kind of power electronic devices, it is characterised in that including：
Chip carrier and chip, the surface bond of the back side of the chip and the chip carrier, the front of the chip has
At least two electrodes and the conductive pole on the electrode；
The chip is formed with plastic packaging layer, the surface of the plastic packaging layer and the flush of the conductive pole by plastic package process；
The table of dielectric layer and again wiring layer, the dielectric layer and the wiring layer again is sequentially formed with the surface of the plastic packaging layer
Face is concordant, the wiring layer again and the conductive pole directly contact.
2. encapsulating structure according to claim 1, it is characterised in that the table of the back side of the chip and the chip carrier
The mode of face bonding includes eutectic weldering, sintering silver or high-heat-conductivity glue coating.
3. encapsulating structure according to claim 1, it is characterised in that the chip carrier includes that metallic carrier, ceramics are carried
Body and high heat conduction complex carrier.
4. encapsulating structure according to claim 1, it is characterised in that the chip is planar power electronic devices.
5. a kind of fan-out package method of power electronic devices, it is characterised in that including：
A chip carrier and multiple chips are provided, the front of each chip has at least two electrodes, in each electricity
It is extremely upper to make a conductive pole；
The back side of each chip is bonded with the chip carrier, chip array is formed on the chip carrier；
Plastic packaging, the surface of the plastic packaging layer of formation and the flush of the conductive pole are carried out to the chip by plastic package process；
The table of dielectric layer and again wiring layer, the dielectric layer and the wiring layer again is sequentially formed on the surface of plastic packaging layer
Face is concordant, the wiring layer again and the conductive pole directly contact；
It is cut to multiple fan-out package structures without lead.
6. method for packing according to claim 5, it is characterised in that described to be moulded to the chip by plastic package process
Envelope, the surface of the plastic packaging layer of formation and the flush of the conductive pole, including：
Plastic packaging is carried out to the chip by plastic package process, the plastic packaging layer formed after solidification is covered on the chip and the chip
The conductive pole；
By reduction process, the upper surface of plastic packaging layer is carried out thinning, be thinned to and expose the conductive pole.
7. method for packing according to claim 5, it is characterised in that described to be sequentially formed on the surface of plastic packaging layer
Dielectric layer and again wiring layer, including：
The plastic packaging layer on form dielectric layer, to the dielectric layer etch perforate, with expose the conductive pole and at least partly
The plastic packaging layer；
Wiring layer again is formed in the conductive pole for exposing and at least partly described plastic packaging layer.
8. method for packing according to claim 5, it is characterised in that the back side of the chip and the chip carrier key
Close, including：
The back side of the chip is welded by eutectic, sintering silver or high-heat-conductivity glue are coated and is bonded with the chip carrier.
9. method for packing according to claim 5, it is characterised in that the chip carrier includes that metallic carrier, ceramics are carried
Body and high heat conduction complex carrier.
10. method for packing according to claim 5, it is characterised in that the chip is planar power electronic devices.
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| US20090039496A1 (en) * | 2007-08-10 | 2009-02-12 | Infineon Technologies Ag | Method for fabricating a semiconductor and semiconductor package |
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| CN105489516A (en) * | 2016-01-22 | 2016-04-13 | 中芯长电半导体（江阴）有限公司 | Packaging method of fan-out type chip, and packaging structure |
| CN206789535U (en) * | 2017-03-31 | 2017-12-22 | 华进半导体封装先导技术研发中心有限公司 | A kind of fan-out package structure of power electronic devices |
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| US20090039496A1 (en) * | 2007-08-10 | 2009-02-12 | Infineon Technologies Ag | Method for fabricating a semiconductor and semiconductor package |
| CN103681371A (en) * | 2013-12-26 | 2014-03-26 | 江阴长电先进封装有限公司 | Silica-based wafer level fan-out encapsulation method and silica-based wafer level fan-out encapsulation structure |
| CN105489516A (en) * | 2016-01-22 | 2016-04-13 | 中芯长电半导体（江阴）有限公司 | Packaging method of fan-out type chip, and packaging structure |
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