CN217881492U - Double-base-island packaging device - Google Patents
Double-base-island packaging device Download PDFInfo
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- CN217881492U CN217881492U CN202221102292.6U CN202221102292U CN217881492U CN 217881492 U CN217881492 U CN 217881492U CN 202221102292 U CN202221102292 U CN 202221102292U CN 217881492 U CN217881492 U CN 217881492U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a double-base-island packaging device, which comprises a main base island, a secondary base island, a high-power chip and a control chip, wherein the secondary base island and the high-power chip are mutually independently distributed on the top surface of the main base island, and the control chip is positioned on the top surface of the secondary base island; the secondary base island comprises a first metal plating layer and an insulating substrate, wherein the first metal plating layer covers the top surface of the insulating substrate; the main base island is a metal substrate, and the control chip is fixed on the first metal coating of the secondary base island. The packaging device improves the electrical isolation performance between chips through the secondary base island formed by arranging the insulating substrate on the main base island, reduces the electric leakage risk, improves the heat dissipation effect of the device due to the fact that the heat dissipation area is improved to some extent, reduces the temperature difference between the high-power chip and the control chip and prolongs the service life of the device.
Description
Technical Field
The utility model relates to an integrated circuit encapsulation technical field, concretely relates to two base island encapsulation devices.
Background
In the integrated circuit packaging technology, the size of a device is reduced by adopting a sealing technology, the sealing technology of two chips at present adopts a single-base-island frame or a double-base-island frame for sealing, and the two chips are packaged on one base island on the single-base-island frame, so that the creepage distance between the chips is small, good electrical isolation cannot be formed, and the reliability of the device is poor. In the double-base-island framework, in order to achieve good electrical isolation, the single base island is divided into two base islands, and in the case of fixed size, the heat dissipation area of the device can be reduced, so that the internal temperature of the device is increased, the temperature difference between two chips is increased, and the service life of the device can be further influenced.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art not enough, the utility model provides a two base island encapsulation devices, the encapsulation device has improved the electrical isolation performance between the chip through set up secondary base island on main base island, has reduced the electric leakage risk, and the heat radiating area of this kind of encapsulation device promotes to some extent than prior art's heat radiating area simultaneously, has improved the radiating effect of device, can reduce the difference in temperature between high power chip and the control chip simultaneously, has prolonged the life of device.
The utility model provides a double-base-island packaging device, which comprises a main base island, a secondary base island, a high-power chip and a control chip, wherein the secondary base island and the high-power chip are mutually independently distributed on the top surface of the main base island, and the control chip is positioned on the top surface of the secondary base island;
the secondary base island comprises a first metal plating layer and an insulating substrate, wherein the first metal plating layer covers the top surface of the insulating substrate;
the main base island is a metal substrate, and the control chip is fixed on the first metal coating of the secondary base island.
Further, the orthographic projection area of the secondary island is S1, the orthographic projection area of the control chip is S2, and the constraint relationship between S1 and S2 is as follows: s2 is more than or equal to 1.5 and less than or equal to S1 and less than or equal to 3 and S2.
Further, the height of the control chip after the control chip and the secondary base island are connected in a matching manner is h1, the height of the high-power chip is h2, and the constraint relationship between h1 and h2 is as follows: h1 is less than or equal to h2.
Further, the secondary base island further comprises a second metal plating layer, and the second metal plating layer covers the bottom surface of the insulating substrate.
Further, the first metal plating layer and the second metal plating layer are copper plating layers.
Further, the secondary base island is fixed on the main base island based on viscose, or the secondary base island is fixed on the main base island by welding.
Furthermore, a plurality of connecting pins are arranged around the main base island;
the connecting pins are electrically connected with the top surface electrodes of the control chip based on the connecting welding wires.
Furthermore, the connecting pins are electrically connected with the top surface electrode of the high-power chip based on connecting welding wires.
Further, the control chip comprises a first electrode, a second electrode and a third electrode, wherein the first electrode and the second electrode are top surface electrodes, and the third electrode is a bottom surface electrode;
or the first electrode, the second electrode, and the third electrode are top surface electrodes.
Furthermore, the high-power chip comprises a fourth electrode, a fifth electrode and a sixth electrode, wherein the fourth electrode, the fifth electrode and the sixth electrode are top surface electrodes.
Further, the control chip is fixed on the top surface of the secondary base island based on a conductive adhesive;
or the control chip is fixed on the top surface of the secondary base island based on the adhesive cement.
Furthermore, the fifth electrode is electrically connected with the first metal plating layer based on a connecting welding wire.
Furthermore, the sixth electrode is electrically connected with the top surface of the main base island based on a connecting bonding wire.
The utility model provides a two base island encapsulation devices, the encapsulation device has improved the electric isolation performance between the chip through set up the secondary base island that insulating substrate formed on main base island, the electric leakage risk has been reduced, regard the top surface of main base island as the cooling surface simultaneously, make the heat radiating area of encapsulation device promote to some extent, thereby make the radiating effect of device improve to some extent, reduce the temperature between high-power chip and control chip on the device, in addition, make the difference in temperature of high-power chip and control chip reduce, thereby improve the reliability of device, the life of device has been prolonged.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a double-base island frame in a first embodiment of the present invention;
fig. 2 is a top view of a dual-island packaged device structure according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a control chip according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a package structure of a dual island device according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
The first embodiment is as follows:
fig. 1 shows the utility model discloses in the embodiment of the utility model discloses two basic island seal device structure schematic diagrams, fig. 2 shows the utility model discloses in the embodiment of double-base island seal device structure top view, two basic island frame includes main basic island 1, secondary basic island 2, high power chip 4 and control chip 5, high power chip 4 with secondary basic island 2 mutual independence distributes on the different positions of main basic island 1 top surface, control chip 5 is fixed on the 2 top surfaces of secondary basic island, control chip 5 is located on the 2 top surfaces of secondary basic island.
Further, the operating power of the high-power chip 4 is higher than that of the control chip 5, the high-power chip 4 has a large size and a high operating power, the control chip 5 has a small size and a low operating power, the control chip 5 and the high-power chip 4 are connected and packaged in a cascode structure, and the control chip 5 can drive and control the operation of the high-power chip 4.
Further, the high power chip 4 may be, but is not limited to, a gallium nitride (GaN) chip, and the control chip 5 may be, but is not limited to, a silicon (Si) MOS chip.
Further, the orthographic projection area of the secondary base island 2 is S1, the orthographic projection area of the control chip 5 is S2, and the constraint relationship between S1 and S2 is: s2 is not less than 1.5 ANG, S1 is not more than 3 ANG, S2. The area of the secondary base island 2 is adjusted to be suitable for control chips 5 with different sizes.
Specifically, the height of the control chip 5 after the control chip and the secondary base island 2 are connected in a matching manner is h1, the height of the high-power chip 4 is h2, and the constraint relationship between h1 and h2 is as follows: h1 is less than or equal to h2. The height of the control chip 5 is lower than that of the high-power chip 4, so that the difficulty of wire bonding between the high-power chip 4 and the control chip 5 can be reduced, and the phenomenon that the whole thickness of the packaging device is too large is avoided.
Specifically, fig. 3 shows the embodiment of the utility model provides an in the secondary base island structure schematic diagram, secondary base island 2 includes insulating substrate 22, insulating substrate 22 can be ceramic substrate, insulating substrate 22 also can be for glass substrate, secondary base island 2 is fixed main base island 1 is on the surface, secondary base island 2 is insulating material, can reach electrical isolation's effect, has reduced the electric leakage risk.
Specifically, the secondary base island 2 includes a first metal plating layer 21, an insulating substrate 22 and a second metal plating layer 23, where the insulating substrate 22 may be a ceramic substrate, and the insulating substrate 22 may also be a glass substrate, so as to achieve an electrical isolation effect.
Specifically, the secondary base island 2 is a double-sided copper-clad substrate, a copper-clad layer is covered on the top surface of the secondary base island 2 to form the first metal plating layer 21, and a copper-clad layer is covered on the bottom surface of the secondary base island 2 to form the second metal plating layer 23.
Furthermore, the first metal plating layer 21 is convenient for electrical connection with the chip electrode, and the heat dissipation area of the device is increased.
Specifically, the main base island 1 is a metal substrate, and the second metal plating layer 23 is in contact with the top surface of the main base island 1, so that heat conduction is facilitated, and the temperature difference between the high-power chip 4 and the control chip 5 is reduced.
Specifically, the secondary base island 2 is fixed on the main base island 1 through an adhesive, and the adhesive may be PES hot melt adhesive film, PO hot melt adhesive film, epoxy adhesive, or the like.
Further, the secondary base island 2 can also be fixed on the main base island 1 by welding, so that the connection between the secondary base island 2 and the main base island 1 is more stable.
Specifically, the high-power chip 4 is a chip with a horizontal structure, and a top electrode of the high-power chip 4 is electrically connected with the main base island 1 based on a connecting wire.
Specifically, the control chip 5 is a vertical chip, the control chip 5 may be fixed on the top surface of the secondary base island 2 by adhering a conductive adhesive, and the bottom electrode of the control chip 5 may be electrically connected to the first metal plating layer 21 based on the conductive adhesive.
Further, the control chip 5 may be a chip with a horizontal structure, and the control chip 5 is fixed on the first metal plating layer 21 based on adhesive cement connection.
Further, the top electrode of the control chip 5 is electrically connected to the first metal plating layer 21 based on a bonding wire, or the top electrode of the control chip 5 is connected to the top electrode of the high-power chip 4 based on a bonding wire.
Specifically, the package device further includes a plurality of connection pins 3, the connection pins 3 include a first pin 31, a second pin 32, a third pin 33, and a fourth pin 34, and the first pin 31, the second pin 32, the third pin 33, and the fourth pin 34 are electrically connected to the top surface electrode of the control chip 5 based on connection bonding wires.
Furthermore, the number of the connecting pins of the packaging device can be adjusted according to the structural design of the device.
Specifically, the secondary base island 2 is connected to the main base island 1, when the packaged device works, the power of the high-power chip is higher than that of the control chip, and the temperature between the high-power chip 4 and the control chip 5 is close to each other by arranging the secondary base island, so that the temperature difference inside the device is reduced, and the reliability of the device is improved.
Furthermore, according to the actual operation temperature requirement of the device, the temperature difference between the high-power chip 4 and the control chip 5 can be regulated and controlled by adjusting the thickness of the secondary base island 2.
Specifically, the control chip 5 includes a first electrode 51, a second electrode 52 and a third electrode 53, the first electrode 51 and the second electrode 52 are disposed on the top surface of the control chip 5, and the third electrode 53 is disposed on the bottom surface of the control chip 5.
Specifically, the first electrode 51 is connected to the first pin 31 based on bonding wires, and the second electrode 52 is connected to the second pin 32, the third pin 33, and the fourth pin 34 based on bonding wires. The third electrode 53 is electrically connected to the first metal plating layer 21 on the top surface of the secondary base island 2 based on the conductive paste.
Specifically, the high power chip 4 includes a fourth electrode 41, a fifth electrode 42 and a sixth electrode 43, the fifth electrode 42, the fourth electrode 41 and the sixth electrode 43 are disposed on the top surface of the high power chip 4, and the fourth electrode 41 is connected to the first metal plating layer 21 of the secondary base island 2 based on a bonding wire; the fifth electrode 42 is connected to the first electrode 51 based on a bonding wire, and the sixth electrode 43 is electrically connected to the main island 1 based on a bonding wire.
Further, the sixth electrode 43 is electrically connected to the main base island 1, and is directly connected to an external circuit through the main base island 1.
Further, the main base island 1 is connected with the first electrode 43 of the high-power chip 4, the device can reduce the arrangement of connecting pins, and the size of the main base island 1 can be increased under the condition that the size of the packaging device is fixed, so that the heat dissipation area of the device is increased, the heat dissipation efficiency of the device is ensured, and the service life of the device is ensured.
Specifically, the fourth electrode 41 is connected to the third electrode 53 through the first metal plating layer 21 on the top surface of the secondary base island 2, and the fifth electrode 42 is connected to the first pin 31 through the first electrode 51.
Further, the connection pin 3 facilitates the connection of the packaged device to other devices and to an external circuit, the sixth electrode 43 is connected to the top surface of the main island 1, and the bottom of the main island 1 facilitates the connection of the packaged device to the external circuit.
Specifically, the sixth electrode 43 is electrically connected to the main base island 1 based on a bonding wire, and the number of connection pins is reduced, so that the area of the package device is increased, the heat dissipation area of the package device can be increased, heat generation of the device is reduced, and the service life of the device is ensured.
Further, according to the heat dissipation requirement of the device, the size of the secondary base island 2 may be adjusted, for example, the size of the secondary base island 2 is reduced, and the contact area between the secondary base island 2 and the main base island 1 is reduced, so that the heat dissipation area of the device is increased, and the heat dissipation capability of the device is improved.
Example two:
fig. 4 shows a schematic diagram of a package of a dual-island device in an embodiment of the present invention, and in this embodiment, the difference from the first embodiment is that the connection pin 3 further includes a fifth pin 35, a sixth pin 36, a seventh pin 37, and an eighth pin 38.
Specifically, the fourth electrode 41, the sixth electrode 43 and the fifth electrode 42 are disposed on the top surface of the high power chip 4, and the sixth electrode 43 is connected to the fifth pin 35, the sixth pin 36, the seventh pin 37 and the eighth pin 38 based on bonding wires.
Further, by providing the fifth pin 35, the sixth pin 36, the seventh pin 37, and the eighth pin 38, the main base island is insulated, and good electrical isolation between the main base island and the secondary base island is formed.
The embodiment of the utility model provides a two base island encapsulation devices, the encapsulation device is through setting up the secondary base island 2 that insulating substrate formed on main base island 1 for the heat radiating area of encapsulation device promotes to some extent, thereby makes the radiating effect of device improve to some extent, reduces the temperature between high power chip and control chip on the device, makes the difference in temperature of high power chip and control chip reduce simultaneously, thereby improves the reliability of device, has prolonged the life of device.
Example three:
in this implementation, will the embodiment of the utility model provides a two base island encapsulated device and two base island encapsulated device of tradition and single base island encapsulated device carry out the comparison, and the chip temperature contrast result that generates heat that obtains is as follows:
in this embodiment, the high power chip 4 is a gallium nitride (GaN) chip, and the control chip 5 is a silicon (Si) Mos chip.
Further, by last table can, the utility model provides an among the two base island packaged device, high power chip 4's the temperature that generates heat is 67.414 ℃, is less than the 4 temperature 67.647 ℃ of high power chip 4's in the single base island packaged device temperature 67.556 ℃ and the two base island packaged device of tradition high power chip 4, the utility model provides a two base island packaged device's 5 temperatures of control chip are 65.760 ℃, and are 1.654 ℃ with the 4 temperature difference of high power chip, are less than the single base island's the chip difference in temperature 2.303 ℃ and two base island chip difference in temperature 2.615 ℃ of tradition. Can obtain by last table, the embodiment of the utility model provides a double-base island encapsulation chip radiating effect is better than single-base island chip and the radiating effect of traditional double-base island chip, effectively reduces generating heat of high power chip 4, reduces the difference in temperature of high power chip 4 and control chip 5, improves the reliability of device, guarantees the life of device.
In addition, the above detailed description is made on a double-base island packaging device provided by the embodiment of the present invention, and a specific example should be adopted herein to explain the principle and the implementation manner of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.
Claims (13)
1. The double-base-island packaged device is characterized by comprising a main base island, a secondary base island, a high-power chip and a control chip, wherein the secondary base island and the high-power chip are independently distributed on the top surface of the main base island, and the control chip is positioned on the top surface of the secondary base island;
the secondary base island comprises a first metal plating layer and an insulating substrate, wherein the first metal plating layer covers the top surface of the insulating substrate;
the main base island is a metal substrate, and the control chip is fixed on the first metal coating of the secondary base island.
2. The dual island packaged device of claim 1, wherein the forward projection area of the secondary island is S1, the forward projection area of the control chip is S2, and the constraint relationship between S1 and S2 is: s2 is not less than 1.5 ANG, S1 is not more than 3 ANG, S2.
3. The dual island packaged device as claimed in claim 1, wherein the height of the control chip after the control chip and the secondary island are connected is h1, the height of the high power chip is h2, and the constraint relationship between h1 and h2 is: h1 is less than or equal to h2.
4. The dual island encapsulated device of claim 1, wherein said secondary island further comprises a second metallization layer overlying a bottom surface of said insulating substrate.
5. The double island encapsulated device of claim 4 wherein said first metal plating layer and said second metal plating layer are copper plating layers.
6. The dual base island encapsulated device of claim 1, wherein said secondary base island is adhesively secured to said main base island or said secondary base island is solder secured to said main base island.
7. The dual-base island packaged device according to claim 1, wherein a plurality of connection pins are disposed around the main base island;
the connecting pins are electrically connected with the top surface electrodes of the control chip based on the connecting welding wires.
8. The dual-island packaged device according to claim 7, wherein the plurality of connection pins are electrically connected to the top surface electrode of the high power chip based on bonding wires.
9. The dual island encapsulated device of claim 8 wherein the control chip comprises a first electrode, a second electrode, and a third electrode, the first and second electrodes being top surface electrodes, the third electrode being a bottom surface electrode;
or the first electrode, the second electrode, and the third electrode are top surface electrodes.
10. The dual island encapsulated device of claim 9, wherein the high power chip comprises a fourth electrode, a fifth electrode, and a sixth electrode, the fourth electrode, fifth electrode, and sixth electrode being top surface electrodes.
11. The dual island packaged device of claim 1 wherein the control chip is affixed to the top surface of the secondary island based on a conductive paste;
or the control chip is fixed on the top surface of the secondary base island based on the adhesive cement.
12. The dual island encapsulated device of claim 10, wherein the fifth electrode is electrically connected to the first metallization layer based on a bond wire;
or the fifth electrode is electrically connected with the third electrode based on a connecting welding wire.
13. The dual island packaged device of claim 10, wherein the sixth electrode is electrically connected to the top surface of the main island based on a bonding wire;
or the sixth electrode is electrically connected with the connecting pin based on a connecting welding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221102292.6U CN217881492U (en) | 2022-05-09 | 2022-05-09 | Double-base-island packaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221102292.6U CN217881492U (en) | 2022-05-09 | 2022-05-09 | Double-base-island packaging device |
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| Publication Number | Publication Date |
|---|---|
| CN217881492U true CN217881492U (en) | 2022-11-22 |
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| CN202221102292.6U Active CN217881492U (en) | 2022-05-09 | 2022-05-09 | Double-base-island packaging device |
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- 2022-05-09 CN CN202221102292.6U patent/CN217881492U/en active Active
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