CN211238226U - Power semiconductor package device - Google Patents
Power semiconductor package device Download PDFInfo
- Publication number
- CN211238226U CN211238226U CN201922166561.XU CN201922166561U CN211238226U CN 211238226 U CN211238226 U CN 211238226U CN 201922166561 U CN201922166561 U CN 201922166561U CN 211238226 U CN211238226 U CN 211238226U
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- CN
- China
- Prior art keywords
- circuit layer
- ceramic substrate
- chip
- power semiconductor
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
Abstract
The utility model provides a power semiconductor packaging device, this power semiconductor packaging device includes: the first ceramic substrate is provided with a first circuit layer on a first surface; the chip is arranged on the first circuit layer and is electrically connected with the first circuit layer; a second ceramic substrate, wherein a second circuit layer is arranged on a second surface of the second ceramic substrate; the second circuit layer is electrically connected with the chip and the first circuit layer respectively. In the technical scheme, the ceramic substrate is adopted to bear the chip, the circuit layer on the ceramic substrate is used for replacing a thick aluminum wire in the prior art, the reliability of the chip during connection is improved, meanwhile, the heat dissipation effect of the chip during working is improved through the ceramic substrate, and the heat dissipation effect of the chip is improved through the arrangement of the ceramic substrates on the two sides of the chip respectively.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially involves a power semiconductor package device.
Background
With the continuous development of chip manufacturing technology, the miniaturization and integration degree of a power device is higher and higher, the power density is also improved continuously, and the requirement on heat dissipation is higher and higher; the chip in the prior art adopts a traditional packaging mode of semi-packaging frame and aluminum wire welding, but the packaging mode has low heat dissipation efficiency and can not meet the requirement of reliability.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present invention provides a power semiconductor package device for effectively improving the heat dissipation effect and reliability of a chip.
The utility model provides a power semiconductor packaging device, this power semiconductor packaging device includes: the first ceramic substrate is provided with a first circuit layer on a first surface; the chip is arranged on the first circuit layer and is electrically connected with the first circuit layer; a second ceramic substrate, wherein a second circuit layer is arranged on a second surface of the second ceramic substrate; the second circuit layer is electrically connected with the chip and the first circuit layer respectively.
In the technical scheme, the ceramic substrate is adopted to bear the chip, the circuit layer on the ceramic substrate is used for replacing a thick aluminum wire in the prior art, the reliability of the chip during connection is improved, meanwhile, the heat dissipation effect of the chip during working is improved through the ceramic substrate, and the heat dissipation effect of the chip is improved through the arrangement of the ceramic substrates on the two sides of the chip respectively.
In a specific possible implementation, the power semiconductor package device further comprises an encapsulation layer, the encapsulation layer is arranged between the first ceramic substrate and the second ceramic substrate, and the encapsulation layer wraps the chip. The device is wrapped by the arranged packaging layer, so that the reliability of the power semiconductor packaging device is improved.
In a specific embodiment, the first circuit layer is provided with a first pad, and the second circuit layer is provided with a second pad; the first circuit layer is electrically connected with the chip through the first bonding pad; the second circuit layer is electrically connected with the chip through the second bonding pad. And the chip is electrically connected with the two ceramic substrates through the bonding pad.
In a specific embodiment, the first bonding pad and the second bonding pad are respectively connected with the chip by soldering through solder paste. The reliability of welding is improved.
In a specific embodiment, the second ceramic substrate is smaller than the first ceramic substrate, and the second ceramic substrate covers the chip. The heat dissipation effect of the chip is improved.
In a specific possible embodiment, the first circuit layer is connected with at least two pins, and the pins extend out of the first ceramic substrate. And is connected with an external circuit through pins.
In a specific embodiment, at least one bump is disposed on the first circuit layer, and the first circuit layer and the second circuit layer are electrically connected through the at least one bump. The electrical connection is achieved through the bumps.
In a specific implementation, the number of the bumps is two, and the two bumps are arranged on two sides of the chip.
In a specific embodiment, the bump is a copper bump. The reliability of the electrical connection is ensured.
In a specific embodiment, the first ceramic substrate and the second ceramic substrate are both double-sided copper-clad ceramic substrates. The heat dissipation effect of the chip is improved.
Drawings
Fig. 1 is a schematic structural diagram of a power semiconductor package device according to an embodiment of the present invention;
FIG. 2 is a schematic front view of a power semiconductor package device;
fig. 3 is a schematic backside view of a power semiconductor package device.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
As shown in fig. 1, fig. 1 shows a schematic structural diagram of a power semiconductor package device provided by an embodiment of the present application; the power semiconductor package device shown in fig. 1 mainly includes a plurality of stacked layer structures, and the plurality of stacked layer structures include: a first ceramic substrate 5, a chip 3, a second ceramic substrate 2 and a packaging layer 1. The first ceramic substrate 5 is used for carrying the chip 3 and the second ceramic substrate 2. The surface of the first ceramic substrate 5 for bearing the chip 3 is a first surface, a first circuit layer is arranged on the first surface, the chip 3 is arranged on the first circuit layer and is electrically connected with the first circuit layer, when the first circuit layer is specifically arranged, the first circuit layer is provided with a first bonding pad, the first circuit layer is electrically connected with the chip 3 through the first bonding pad, when welding is carried out, the first bonding pad is connected with the chip 3 in a welding mode through tin paste, and when the chip 3 is fixedly connected with the first ceramic substrate 5, the electric connection between the chip 3 and the first ceramic substrate is also achieved.
With continued reference to fig. 1, the first circuit layer is further provided with at least one bump 4, in fig. 1, the number of the bumps 4 is two, the two bumps 4 and the chip 3 are provided in the same layer and are arranged on two sides of the chip 3, and the two bumps 4 are used for electrically connecting with the second ceramic substrate 2. In the present embodiment, the shape of the bump 4 is not particularly limited, and may be the rectangular parallelepiped or the square with a flat surface.
With continued reference to fig. 1, at least two leads 6 are connected to the first circuit layer, and the leads 6 extend out of the first ceramic substrate 5 and are used for connection with an external circuit. In fig. 1, the number of the pins 6 is three, and the three pins 6 are respectively connected with the chip 3 and the two bumps 4 in a one-to-one correspondence manner, so as to facilitate connection with an external circuit.
With continued reference to fig. 1, a second ceramic substrate 2 is stacked with a chip 3 and bumps 4, as shown in fig. 2, fig. 2 shows a schematic front view of a power semiconductor package device, the second ceramic substrate 2 is smaller in size than the first ceramic substrate 5, but the second ceramic substrate 2 covers the chip 3 and also covers the two bumps 4. When the second ceramic substrate 2 is disposed, the second ceramic substrate has a second surface, and a second circuit layer is disposed on the second surface and electrically connected to the chip 3 and the first circuit layer. When in connection, the second circuit layer is provided with a second bonding pad; the second circuit layer is electrically connected to the chip 3 through a second bonding pad, and the second bonding pad is connected to the chip 3 through solder during specific soldering. Meanwhile, the second circuit layer is also electrically connected with the first circuit layer, in the concrete implementation, the first circuit layer and the second circuit layer are electrically connected through at least one salient point 4, and when the number of the salient points 4 is two, the two salient points 4 are respectively connected with the second circuit layer in a welding manner.
In the above technical solution, the first ceramic substrate 5 and the second ceramic substrate 2 are both double-sided copper-clad ceramic substrates. That is, the other surface of the first ceramic substrate 5 facing the first circuit layer also has a copper-clad layer, and the other surface of the second ceramic substrate 2 facing the second circuit layer also has a copper-clad layer. Chip 3 is at the during operation, conducts away the heat through two ceramic substrates that lie in chip 3 upper and lower both sides, has improved the radiating efficiency through covering the copper layer simultaneously. It can be seen from the above description that the double-sided copper-clad ceramic substrate is used to replace the base island of the lead frame, the chip is welded on the ceramic substrate, the insulation between the internal chip 3 and the outside is realized through the ceramic substrate, and the heat dissipation efficiency is remarkably improved. In addition, replace thick aluminium wire with two-sided copper-clad ceramic plate, realize chip 3 and substrate pin 6's being connected, avoided the chip 3 damage that the aluminium wire welding brought, the electric leakage scheduling problem, promote the overcurrent ability of product by a wide margin, improved the reliability of product, through ceramic substrate heat conduction, realize two-sided ceramic heat dissipation, greatly reduced the thermal resistance of device simultaneously.
With continued reference to fig. 1, 2 and 3, fig. 3 shows a schematic backside view of chip 3. The power semiconductor packaging device provided by the embodiment of the application further comprises a packaging layer 1, and the packaging layer 1 can be resin or other insulating materials. When using, packaging layer 1 is between first ceramic substrate 5 and second ceramic substrate 2 to parcel chip 3, thereby protection chip 3, in addition, packaging layer 1 forms for the preparation of heat conduction material, and packaging layer 1 is connected with the second face of first ceramic substrate 5's first face second ceramic substrate 2 respectively, can go out the heat transfer that chip 3 produced.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A power semiconductor package device, comprising:
the first ceramic substrate is provided with a first circuit layer on a first surface;
the chip is arranged on the first circuit layer and is electrically connected with the first circuit layer;
a second ceramic substrate, wherein a second circuit layer is arranged on a second surface of the second ceramic substrate; the second circuit layer is electrically connected with the chip and the first circuit layer respectively.
2. The power semiconductor package device of claim 1, further comprising an encapsulation layer between the first ceramic substrate and the second ceramic substrate, the encapsulation layer encapsulating the chip.
3. The power semiconductor package device of claim 2, wherein the first circuit layer is provided with first pads and the second circuit layer is provided with second pads;
the first circuit layer is electrically connected with the chip through the first bonding pad;
the second circuit layer is electrically connected with the chip through the second bonding pad.
4. The power semiconductor package device of claim 3, wherein the first and second bonding pads are respectively solder bonded to the die with solder paste.
5. The power semiconductor package device of claim 2, wherein the second ceramic substrate is smaller than the first ceramic substrate, and the second ceramic substrate covers the chip.
6. The power semiconductor package device of claim 1, wherein the first circuit layer is connected with at least two pins, and the pins extend out of the first ceramic substrate.
7. The power semiconductor package device according to any one of claims 1 to 6, wherein at least one bump is disposed on the first circuit layer, and the first circuit layer and the second circuit layer are electrically connected through the at least one bump.
8. The power semiconductor package device of claim 7, wherein the number of said bumps is two, and said two bumps are arranged on two sides of said chip.
9. The power semiconductor package device of claim 7, wherein said bump is a copper bump.
10. The power semiconductor package device of claim 7, wherein the first ceramic substrate and the second ceramic substrate are both double-sided copper-clad ceramic substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922166561.XU CN211238226U (en) | 2019-12-05 | 2019-12-05 | Power semiconductor package device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922166561.XU CN211238226U (en) | 2019-12-05 | 2019-12-05 | Power semiconductor package device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211238226U true CN211238226U (en) | 2020-08-11 |
Family
ID=71926879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922166561.XU Active CN211238226U (en) | 2019-12-05 | 2019-12-05 | Power semiconductor package device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211238226U (en) |
-
2019
- 2019-12-05 CN CN201922166561.XU patent/CN211238226U/en active Active
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