CN216015357U - Packaging structure of low-internal-resistance ultra-thin power device - Google Patents
Packaging structure of low-internal-resistance ultra-thin power device Download PDFInfo
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- CN216015357U CN216015357U CN202122373409.6U CN202122373409U CN216015357U CN 216015357 U CN216015357 U CN 216015357U CN 202122373409 U CN202122373409 U CN 202122373409U CN 216015357 U CN216015357 U CN 216015357U
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- conductive metal
- semiconductor chip
- packaging structure
- metal sheet
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 238000003466 welding Methods 0.000 claims abstract description 25
- 238000005538 encapsulation Methods 0.000 claims abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 claims description 3
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 239000004033 plastic Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
The utility model discloses a packaging structure of low ultra-thin type power device of internal resistance, its technical scheme main points are: packaging structure of low internal resistance ultra-thin type power device, including fin, semiconductor chip, the plastic-envelope body and dress piece base island, the positive first electrode Source of semiconductor chip welds with the one end of second conductive metal piece, the positive second electrode Gate of semiconductor chip welds with the one end of first conductive metal piece, the encapsulation is equipped with the welding end of dress piece base island front, semiconductor chip, first conductive metal piece and second conductive metal piece in the plastic-envelope body, fin and dress piece base island back expose outside the plastic-envelope body. The utility model discloses the structure adopts conductive metal piece as the direct electrode welding with semiconductor chip of pin, can reduce device encapsulation parasitic resistance, increases device overcurrent ability, can strengthen the heat-sinking capability of device again, reduces the encapsulation thermal resistance, has improved the reliability of device encapsulation.
Description
Technical Field
The utility model relates to a semiconductor package field, in particular to ultra-thin type power device's of low internal resistance packaging structure.
Background
The semiconductor device is continuously developed, the semiconductor chip enters the times of several haustoria, the size is more and more miniaturized, the parasitic resistance of the packaging structure of the traditional semiconductor device is larger, some of the parasitic resistance even exceeds the internal resistance of the chip, in addition, the packaging thermal resistance of the semiconductor device is larger, the packaging thermal resistance determines the maximum power loss of the device, and if the packaging thermal resistance and the parasitic resistance can be effectively reduced, the current capacity and the power of the MOSFET device can be greatly improved. Therefore, in addition to the development of new MOSFET chip structure designs and process technologies, packaging techniques, processes, and manufacturing methods of semiconductor devices are also important.
The package of traditional semiconductor device MOSFET product generally utilizes gold thread, silver alloy line, copper line, palladium copper line, aluminium wire as the lead wire with semiconductor chip and pin welding to realize electrical connection, but adopt the metal wire welding mode to have many defects:
1. in order to meet the requirement of high voltage or large current output, a plurality of thick wires are often adopted for welding the source electrode of the MOSFET as a connecting wire; the grid bears less current, and a thin gold wire, a copper wire, an alloy wire or a thin aluminum wire is usually adopted as a connecting wire; therefore, for the same packaging form, different metal leads are needed, lead frames or welding tools with different electroplated layers are needed to be selected according to the types of the metal leads, and the aluminum wire machine is expensive in equipment, so that the manufacturing cost is high; because of the wire bonding mode, the connecting wire needs to have radian, so the product volume can be increased, and the material is wasted.
2. Aiming at the problems that the area of a plurality of MOSFET chips is small, the wire bonding is difficult, and the design of a lead frame limits the position and the angle of lead welding, so that no wire bonding method is available;
3. the comparison between the conventional Wire Bonding and the designed Clip Bonding process RDSON pair is shown in the attached figure 1 of the specification.
Based on the existing problems of the welding mode and the comparison of the novel Cl ip packaging process, domestic and foreign major factories continuously optimize and improve the welding process or replace the traditional metal wire with a metal belt and other methods so as to solve the problems caused by metal wire welding and reduce the parasitic resistance and the volume of device packaging.
SUMMERY OF THE UTILITY MODEL
To the problem mentioned in the background art, the present invention is directed to provide a package structure of a low internal resistance ultra-thin power device to solve the problem mentioned in the background art.
The above technical purpose of the present invention can be achieved by the following technical solutions:
the utility model provides a low internal resistance ultra-thin type power device's packaging structure, includes fin, semiconductor chip, the plastic-envelope body and dress piece base island, the positive first electrode Source of semiconductor chip welds with the one end of second conductive metal piece, the positive second electrode Gate of semiconductor chip welds with the one end of first conductive metal piece, the encapsulation is equipped with the welding end that dress piece base island openly, semiconductor chip, first conductive metal piece and second conductive metal piece in the plastic-envelope body, fin and dress piece base island back expose outside the plastic-envelope body, the other end of first conductive metal piece and second conductive metal piece stretches out the plastic-envelope body as the pin.
Preferably, the first conductive metal sheet and the second conductive metal sheet are copper sheets, copper alloy sheets, iron-nickel alloy sheets, aluminum sheets or aluminum alloy sheets, and the surfaces of the first conductive metal sheet and the second conductive metal sheet are provided with copper, silver, iron-nickel or nickel-phosphorus coatings.
Preferably, the thickness of the first conductive metal sheet and the second conductive metal sheet is 0.1mm-5 mm.
Preferably, the semiconductor chip is a silicon-based MOSFET chip.
Preferably, the package structure is suitable for DFN or PDFN.
Preferably, the chip mounting base islands are one or more, the chip mounting base islands are insulated from one another, a semiconductor chip is welded on each chip mounting base island, and a conductive metal sheet is welded on an electrode on the front surface of each semiconductor chip.
To sum up, the utility model discloses mainly have following beneficial effect:
the utility model discloses to the problem that the encapsulation of low power semiconductor device exists that switches on, provide a low packaging structure who switches on power semiconductor device, this structure adopts electrically conductive sheetmetal as the direct electrode welding with semiconductor chip of pin, can reduce device encapsulation parasitic resistance, and increase device overcurrent ability can strengthen the heat-sinking capability of device again, reduces the encapsulation thermal resistance, has improved the reliability of device encapsulation. The utility model has simple process and high production efficiency, and can improve the reliability of the product; the utility model discloses a structure easily encapsulates, can realize the disposable machine-shaping of the inside interconnection of encapsulation.
Drawings
Fig. 1 is a schematic structural diagram of a comparison document of the present invention;
fig. 2 is a rear view of an embodiment of the present invention;
FIG. 3 is a block diagram of an embodiment of the present invention;
FIG. 4 is a flow chart of the production process of an embodiment of the present invention;
FIG. 5 is a diagram of an actual product according to an embodiment of the present invention;
description of the drawings: the chip comprises an A-radiating fin, a B-MOSFET chip, a C-plastic package body, M-chip solder, a D-first conductive metal sheet Gate electrode, an E-second conductive metal sheet Source electrode, an F-chip mounting base island and a G-Drain electrode pin.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1 to 5, a package structure of a low internal resistance ultra-thin power body device includes a heat sink a, a semiconductor chip B, a plastic package body C and a package substrate island F, wherein a first electrode Source on the front surface of the semiconductor chip B is welded to one end of a second conductive metal sheet E, a second electrode Gate on the front surface of the semiconductor chip B is welded to one end of a first conductive metal sheet D, the package substrate island F front surface, the semiconductor chip B, the welding end of the first conductive metal sheet D and the welding end of the second conductive metal sheet E are packaged in the plastic package body C, the heat sink a and the package substrate island F back surface are exposed outside the plastic package body C, and the other end of the first conductive metal sheet D and the second conductive metal sheet E extends out of the plastic package body C as a pin.
The first conductive metal sheet D and the second conductive metal sheet E are copper sheets, copper alloy sheets, iron-nickel alloy sheets, aluminum sheets or aluminum alloy sheets, and the surfaces of the first conductive metal sheet D and the second conductive metal sheet E are provided with copper, silver, iron-nickel or nickel-phosphorus coatings.
The thickness of the first conductive metal sheet D and the second conductive metal sheet E is 0.1mm-5 mm.
The semiconductor chip B is a silicon-based MOSFET chip.
The packaging form suitable for the packaging structure is DFN or PDFN.
The semiconductor chip packaging structure comprises a chip packaging substrate F, a plurality of chip packaging substrates F, a plurality of semiconductor chips B and a plurality of conductive metal sheets, wherein the number of the chip packaging substrates F is one or more, the plurality of the chip packaging substrates F are insulated, each chip packaging substrate F is welded with a semiconductor chip B, and the electrode on the front surface of each semiconductor chip B is welded with a conductive metal sheet.
The embodiment also provides a manufacturing method of the packaging structure of the low-internal-resistance ultra-thin power device, which comprises the following steps:
the method comprises the following steps: dividing the semiconductor wafer pasted with the film into single semiconductor chips B in a scribing mode;
step two: providing a semiconductor chip B and a chip-mounting base island F, wherein the front surface of the semiconductor chip B is provided with a first electrode Source and a second electrode Gate, the back surface of the semiconductor chip B is provided with a third electrode Drain, the chip-mounting base island F comprises a front surface and a back surface, the front surface and the semiconductor chip Drain are connected, and the back surface is provided with a radiating fin A;
step three: welding a third electrode Drain on the back surface of the semiconductor chip B to the front surface of the chip-on-substrate F through the solder M; providing two conductive metal sheets, welding one end of a first conductive metal sheet D to a first electrode Source on the front surface of the semiconductor chip B through a conductive material, and welding one end of a second conductive metal sheet E to a second electrode Gate on the front surface of the semiconductor chip B through a welding material;
step four: the front surface of the chip-mounting base island F, the semiconductor chip B, one end of a first conductive metal sheet D and one end of a second conductive metal sheet E are wrapped by epoxy resin C with insulating property, and the other ends of the first conductive metal sheet D and the second conductive metal sheet E are used as pins of a semiconductor device and extend out of the plastic package body C;
step five: post-curing, namely placing the chip after plastic packaging into a constant-temperature oven for curing;
step six: removing flash; softening the flash by using softening liquid, and then removing flash in full-automatic high-pressure water spraying equipment;
step seven: electroplating tin: electroplating a layer of tin on the surface of the lead frame outside the encapsulation;
step eight: cutting ribs into single pieces by punching or cutting;
step nine: and packaging and taking out after testing the braid.
And in the third step, the first conductive metal sheet D and the second conductive metal sheet E are simultaneously welded on the electrode on the front surface of the semiconductor chip B.
The chip welding material M and the pin welding material are soft solder and tin paste, and the welding mode is diffusion welding or sintering welding.
The first conductive metal sheet D and the second conductive metal sheet E are connected through a support part, and the support part is removed through punching or cutting after the plastic package body C is encapsulated.
Wherein, the utility model discloses to the problem that the encapsulation of low power semiconductor device exists, provide a low packaging structure who switches on power semiconductor device, this structure adopts the electrically conductive sheetmetal as the direct electrode welding with semiconductor chip of pin, can reduce device encapsulation parasitic resistance, and increase device overcurrent ability can strengthen the heat-sinking capability of device again, reduces the encapsulation thermal resistance, has improved the reliability of device encapsulation. The utility model has simple process and high production efficiency, and can improve the reliability of the product; the utility model discloses a structure easily encapsulates, can realize the disposable machine-shaping of the inside interconnection of encapsulation.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The utility model provides a packaging structure of ultra-thin novel power device of low internal resistance which characterized in that: including fin (A), semiconductor chip (B), plastic-sealed body (C) and dress piece base island (F), the positive first electrode Source of semiconductor chip (B) welds with the one end of the electrically conductive sheetmetal of second (E), the positive second electrode Gate of semiconductor chip (B) welds with the one end of first electrically conductive sheetmetal (D), encapsulation is equipped with dress piece base island (F) openly in plastic-sealed body (C), semiconductor chip (B), the welding end of first electrically conductive sheetmetal (D) and the electrically conductive sheetmetal of second (E), fin (A) and dress piece base island (F) back expose outside plastic-sealed body (C), the other end of first electrically conductive sheetmetal (D) and the electrically conductive sheetmetal of second (E) stretches out outside plastic-sealed body (C) as the pin.
2. The packaging structure of the ultra-thin novel power device with low internal resistance of claim 1, characterized in that: the first conductive metal sheet (D) and the second conductive metal sheet (E) are copper sheets, copper alloy sheets, iron-nickel alloy sheets, aluminum sheets or aluminum alloy sheets, and the surfaces of the first conductive metal sheet (D) and the second conductive metal sheet (E) are provided with copper, silver, iron-nickel or nickel-phosphorus coatings.
3. The packaging structure of the ultra-thin novel power device with low internal resistance of claim 1, characterized in that: the thickness of the first conductive metal sheet (D) and the second conductive metal sheet (E) is 0.1mm-5 mm.
4. The packaging structure of the ultra-thin novel power device with low internal resistance of claim 1, characterized in that: the semiconductor chip (B) is a silicon-based MOSFET chip.
5. The packaging structure of the ultra-thin novel power device with low internal resistance of claim 1, characterized in that: the packaging structure is suitable for packaging DFN or PDFN.
6. The packaging structure of the ultra-thin novel power device with low internal resistance of claim 1, characterized in that: the chip mounting base islands (F) are one or more, the chip mounting base islands (F) are insulated, semiconductor chips (B) are welded on the chip mounting base islands (F), and conductive metal sheets are welded on electrodes on the front surfaces of the semiconductor chips (B).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122373409.6U CN216015357U (en) | 2021-09-29 | 2021-09-29 | Packaging structure of low-internal-resistance ultra-thin power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122373409.6U CN216015357U (en) | 2021-09-29 | 2021-09-29 | Packaging structure of low-internal-resistance ultra-thin power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216015357U true CN216015357U (en) | 2022-03-11 |
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ID=80523118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122373409.6U Active CN216015357U (en) | 2021-09-29 | 2021-09-29 | Packaging structure of low-internal-resistance ultra-thin power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216015357U (en) |
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2021
- 2021-09-29 CN CN202122373409.6U patent/CN216015357U/en active Active
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| TR01 | Transfer of patent right |
Effective date of registration: 20240312 Address after: No. 3000, Qiantangjiang Road, Qidong Economic Development Zone, Nantong City, Jiangsu Province, 226200 Patentee after: JIANGSU JIEJIE MICROELECTRONICS Co.,Ltd. Country or region after: China Address before: 214000 b-221, China Sensor Network International Innovation Park, 200 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province Patentee before: Jiejie Microelectronics (Wuxi) Technology Co.,Ltd. Country or region before: China |