CN207753000U - A kind of gallium nitride device - Google Patents
A kind of gallium nitride device Download PDFInfo
- Publication number
- CN207753000U CN207753000U CN201721770787.5U CN201721770787U CN207753000U CN 207753000 U CN207753000 U CN 207753000U CN 201721770787 U CN201721770787 U CN 201721770787U CN 207753000 U CN207753000 U CN 207753000U
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- Prior art keywords
- gallium nitride
- chip
- substrate
- cabling
- silicon chip
- Prior art date
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- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Junction Field-Effect Transistors (AREA)
Abstract
The utility model provides a kind of gallium nitride device, and the gallium nitride device includes：Design covering copper pcb board (ceramics or aluminium base cover copper pcb board) and being welded on the silicon chip and gallium nitride chip covered on copper pcb board for cabling, it is connected by the way of Cascode between silicon chip and gallium nitride chip, wherein, on covering copper pcb board, gallium nitride chip is inverted in be covered on copper pcb board the silicon chip formal dress.Gallium nitride device mainly realizes the electrical connection between the gallium nitride chip and the silicon chip using the cabling covered on copper pcb board；Wherein, the silicon chip drain electrode directly with cover the pad solder in copper pcb board interior cabling；Source electrode, grid and the drain electrode of the gallium nitride chip are located towards on the face for covering copper pcb board, and the source electrode of the gallium nitride chip, grid and drain electrode directly with cover the pad solder in copper pcb board interior cabling.The preparation process of above-mentioned gallium nitride device is simple, good heat dissipation effect.
Description
Technical field
The utility model is related to technical field of semiconductors, especially a kind of gallium nitride device.
Background technology
GaN HEMT (high electron mobility transistor) are known as third generation power semiconductor.Since silicon physics is special
The limitation of sign, GaN HEMT will gradually replace most applications of the silicon device in field of power electronics, further increase electric power
The efficiency and reduction volume of electronic system reduce manufacturing cost.
The silicon semiconductor PN junction generated on silicon-based wafer is " vertical structure ", so three poles of mosfet transistor
It is distributed in as " vertical structure " in two planes up and down of transistor semiconductor chip.
The semiconductor PN generated on the gallium nitride material above wafer can be " planar structure ", so GaN HEMT
Three poles be distributed in the approximately the same plane of transistor semiconductor chip.
Currently, transistor has two kinds of D-Mode (depletion type) and E-Mode (enhanced).Its drain D of the transistor of D-Mode
It is usually in normally opened low resistance state between source S, and is usually between its drain D of the transistor of E-Mode and source S normal
The high-impedance state closed.In the circuit topology of power electronics, for effectively control and it is easy to use, it usually needs switching device be in it is normally closed
High-impedance state, so common is all the transistor of E-Mode.So the gallium nitride chip (GAN HEMT) of D-Mode must lead to
The connection type for crossing Cascode (cascade) becomes normally closed high-impedance state, could easily and effectively be directly applied to power electronics
In circuit topology.The connection type of Cascode is as shown in Figure 1A, and left side is the silicon core of low pressure field-effect tube (LVMOS) in Figure 1A
Piece, right side are the gallium nitride chip (D-Mode GAN HEMT) of depletion type.
There is provided a kind of D-Mode devices of Cascode connection types in the prior art, which is that take will be low
Pressure silicon chip and gallium nitride chip are attached on the bottom plate of different materials respectively, or by low pressure silicon chip formal dress in package support or gold
Belong on bottom plate, by gallium nitride chip formal dress on package support or metal base plate, then between two chips and chip and envelope
Between dress holder pin Cascode connections are carried out with the mode of routing.
Prior art is described in detail as follows in conjunction with Figure 1B：
Pedestal A1 is a block of metal (metal top layer is conductive, and bottom is insulation), is attached with silicon chip A3 and nitrogen thereon
Change gallium chip A2.In encapsulation process, by the grid of the source electrode (Source, S) of silicon chip A3 and gallium nitride chip A2 (Gate,
G it) connects together, the source electrode B3 as gallium nitride device cascade tube is drawn.Due to the drain electrode (Drain, D) of silicon chip A3
In bottom, and pedestal A1 is a block of metal, needs the drain electrode of silicon chip A3 and the source electrode of gallium nitride A2 being attached together, such as
Shown in B1 in Figure 1B.It is drawn the grid of silicon chip A3 as the gate electrode of gallium nitride device cascade tube, in Figure 1B
Shown in B2.Drain electrode by the drain electrode of gallium nitride chip A2 as gallium nitride device cascade tube is drawn, such as the B4 institutes in Figure 1B
Show.
The vertical view that the prior art completes the gallium nitride device cascade tube after encapsulation is as shown in Figure 2.Nitrogen after being encapsulated in Fig. 2
Change putting in order for the electrode of gallium device cascade tube and is followed successively by grid (ends G), source electrode (ends S) and drain electrode (ends D).
The shortcomings that prior art, is as follows：
(1) bottom surfaces silicon chip A3 are silicon materials；And the bottom surface of gallium nitride chip A2 may be that silicon, silicon carbide or sapphire are brilliant
Physa by silicon chip and the weldering of gallium nitride chip patch or is pasted onto on the holder or bottom plate of same material or different materials, prepares
There are problems for technique and heat dissipation；
(2) device of above-mentioned Cascode connections is encapsulated, complex process and cost are higher；
(3) power device as same overload current, gallium nitride chip A2 areas are more much smaller than silicon chip area, i.e. A2
For the bonding pad area of line it is also much smaller, the efficient weld area and line line of overload current ability and tie point on chip
Diameter is related with item number.So device considers routing technological requirement in preparation process in Figure 1B, the weldering on A2 chips for connection
Disc area is several times bigger than practical routing line contact area.
(4) it can only be attached by the way of routing between two chips of A3 and A2, complex process is of high cost, mistake
The load bigger routing line footpath of electric current is thicker, item number is more.
For this purpose, the problem of a kind of gallium nitride device that can be solved the above problems of offer becomes current urgent need to resolve.
Utility model content
For the problems of the prior art, the utility model provides a kind of gallium nitride device.
In a first aspect, the utility model provides a kind of gallium nitride device, including substrate and Cascode grades are associated in the substrate
On silicon chip and gallium nitride chip, on the substrate, the gallium nitride chip is inverted in the base to the silicon chip formal dress
On plate.That is, gallium nitride device includes：Substrate and formal dress are welded on the nitridation of silicon chip, face-down bonding on substrate on substrate
Gallium chip, is connected between silicon chip and gallium nitride chip by the way of Cascode.
Optionally, the silicon chip and the gallium nitride chip are mounted on the same face of the substrate.
Optionally, gallium nitride device mainly realizes the gallium nitride chip and the silicon core using the cabling on the substrate
Electrical connection between piece；
For example, the silicon chip drain electrode directly with the pad solder in the substrate interior cabling；
Source electrode, grid and the drain electrode of the gallium nitride chip are located towards on the face of the substrate, and the gallium nitride core
The source electrode of piece, grid and drain electrode directly with the pad solder in the substrate interior cabling.
Optionally, the pad of the drain electrode of the silicon chip and source electrode of the gallium nitride chip, grid and drain electrode weldering
Disk is close with the area of pad on the cabling in corresponding substrate.
Specifically, the pad on substrate can also be suitably larger than the pad on gallium nitride chip, silicon chip, according to reality
Border needs to adjust.
Optionally, the silicon chip drain electrode and the gallium nitride chip source electrode respectively in substrate 1 first cabling
Pad solder；
And/or
One end pad solder of one second cabling in the grid and substrate of the gallium nitride chip, second cabling it is another
Pad solder one source package pin in one end draws one first lead from the source electrode of the silicon chip and makes first lead
End is welded in the other end pad of second cabling；
And/or
One end pad solder of a third cabling in the drain electrode of the gallium nitride chip and substrate, the third cabling it is another
The drain electrode packaging pin of one end pad solder one；
And/or
The grid of the silicon chip draws one second lead and using the end of second lead as gate package pin.
Optionally, the substrate is single layer, bilayer or multilayer PCB circuit board.
The utility model has the advantage that：
1) gallium nitride device of the utility model, when Cascode is cascaded, silicon chip formal dress is on substrate, gallium nitride core
Piece is inverted on substrate, and then mainly realizes the electrical connection between gallium nitride chip and silicon chip by the cabling on substrate,
And then the preparation process of gallium nitride device is simple, good heat dissipation effect.
2) since gallium nitride chip is inverted on substrate, the pad face in gallium nitride chip for connection can all effectively
It is welded on the pad on the cabling of substrate such as pcb board, realizes that effective connection area of overload current maximizes.
3) since mainly to use the cabling on substrate to realize electrical between gallium nitride chip and silicon chip for gallium nitride device
Connection reduces most of routing in the Cascode encapsulation of the prior art, solves gallium nitride device and is making TO encapsulation space-times
Between upper routing the problem of intersecting.It is removed except TO (Transistor Outline, transistor package) encapsulation at the same time it can also realize
SOT (Small Outline Transistor, small outline transistor), QFN (Quad Flat Package, small-sized square are flat
Face encapsulate) etc. forms encapsulation.
Description of the drawings
Figure 1A is the cascade schematic diagrams of Cascode in the prior art；
Figure 1B is the cascade schematic diagrames of Cascode of gallium nitride device in the prior art；
Fig. 2 is the schematic diagram after prior art Cascode cascade encapsulation；
Fig. 3 is the schematic diagram of gallium nitride device in the utility model embodiment 1；
Fig. 4 is the schematic diagram of cabling inside substrate in the utility model embodiment 1.
Specific implementation mode
It is below in conjunction with the accompanying drawings, right by specific implementation mode in order to understand in order to preferably explain the utility model
The utility model is described in detail.
To be better understood from the content of the utility model, the partial words used in the utility model are explained as follows：
Formal dress：Upward by the front (face for including electrode) of chip, bottom is directly welded on package support or substrate；
Upside-down mounting：Chip top and bottom are overturn, positive (face for including electrode) downward, the electrode on front, which is directly welded at, to be set
On the pcb board for counting connection cabling；
GaN HEMT：GaN high electron mobility transistor；
Depletion type (D-MODE) Gan HEMT chips are usually in normally opened low resistance state, hereinafter referred to as nitrogen between D and S
Change gallium chip；
The silicon chip of low pressure field-effect tube (LVMOS), hereinafter referred to as silicon chip or LVMOS chips.
It should be noted that routing refers to being connected two electrodes by gage system in the utility model embodiment.
Pad solder in the utility model embodiment specifically refers to not by the way of routing by the electrical connection of two pads, for example,
It can realize that pad solder is realized in welding or adhesive means by solder mode.
Embodiment 1
As shown in figure 3, the gallium nitride device of the present embodiment includes：Substrate, silicon chip 001 and gallium nitride chip 002, and
Including source package pin, gate package pin and drain electrode packaging pin；Wherein, silicon chip formal dress is on substrate, gallium nitride core
Piece is inverted on substrate, realizes the Cascode cascade systems used between silicon chip and gallium nitride chip.Silicon is shown in Fig. 4
Chip formal dress is welded on the position A2 of position A1 and gallium nitride chip face-down bonding on substrate on substrate.
In the present embodiment, drain D, source S and the grid G of gallium nitride chip are respectively positioned on the same face of chip.In Fig. 3 and figure
In 4, drain D, source S and the grid G of gallium nitride chip are located towards on the face of substrate.The drain D of silicon chip is located towards base
On the face of plate.It is the same face that gallium nitride chip and silicon chip are located at substrate shown in Fig. 3 and Fig. 4.
Specifically, in gallium nitride device, the main cabling using on substrate is realized between gallium nitride chip and silicon chip
Electrical connection；For example, silicon chip drain electrode directly with the pad solder in substrate interior cabling；Source electrode, the grid of gallium nitride chip
With drain electrode be located towards on the face of substrate, and the source electrode of gallium nitride chip, grid and drain electrode directly in substrate interior cabling
Pad solder.
Dashed region is the pad on chip in Fig. 3, and the solid line region of silicon chip and gallium nitride chip position is silicon respectively
The shape of chip and gallium nitride chip is illustrated, and solid line region is the pad of substrate upward wiring in Fig. 4, and what dashed region indicated is
The band of position of chip.
With reference to shown in Fig. 4, the drain D of silicon chip is welded on the pad D1 of first one end cabling C1 of substrate, gallium nitride core
The source S of piece is welded on the pad D2 of the first cabling C1 other ends in substrate；
The grid G of gallium nitride chip is welded on the pad D3 of second one end cabling C2 of substrate, and the second cabling C2's is another
End pad D6 is for welding above-mentioned source package pin；
The drain D of gallium nitride chip is welded on the pad D4 of one end third cabling C3 of substrate, and third cabling C3's is another
End pad D7 is for welding above-mentioned drain electrode packaging pin.
Based on above-mentioned structure, the present embodiment by three foundation plate interior cablings (such as C1, C2, C3) and two leads (such as
First lead B1, the second lead B2) realize that the Cascode between silicon chip and gallium nitride chip is cascaded.As shown in figure 3, silicon core
The source S of piece draws the second lead B2, and the pad D6 on the end welding substrate of second lead B2 is (as shown in figure 4, i.e. second
One end pad D6 of cabling C2)；
As shown in figure 4, the grid G of silicon chip draws the first lead B1, on the end welding substrate of first lead B1
Pad D5, pad D5 are for welding above-mentioned gate package pin.
As a result, in figs. 3 and 4, what D1 to D7 was all made of is the pad on substrate, and C1, C2, C3 are walking in basic
Line, B1 are the first lead, and B2 is the second lead.
Silicon chip formal dress, gallium nitride chip upside-down mounting in the present embodiment, and the poles D of silicon chip is made to be directly welded at substrate
On, three electrodes of gallium nitride chip are directly welded on substrate, so that gallium nitride device mainly uses substrate interior cabling
It is attached, reduction relatively mostly uses the defect that routing mode connects in the prior art.That is, the encapsulating structure of above-mentioned gallium nitride device
The problem of capable of effectively reducing in existing Cascode cascades using more routing, so that simple for process.
In addition, in practical applications, the pad of the drain electrode of the silicon chip and source electrode of gallium nitride chip, grid and drain electrode
Pad is close with the area of pad on the cabling in corresponding substrate, for this purpose, the gallium nitride device of the present embodiment dissipates
Thermal effect is good, and can bear more high current, solves the contact area limiting overload electric current that routing exists in the prior art
Defect.
In addition, the substrate in the present embodiment is the internal substrate with metal routing, internal cabling is presented on substrate
Pad.In practical applications, substrate is exactly pcb board.The pcb board can be single side pcb board or double-sided PCB board.Alternatively, pcb board
Can be single layer, bilayer or multilayer structure.Preferably, substrate can be design cabling cover copper pcb board (ceramics or aluminium base
Cover copper pcb board).
Gallium nitride chip in above-described embodiment can be the chip of depletion type structure, and gallium nitride device is Enhanced Configuration
Device.LVMOS and D-Mode Gan HEMT are become E-Mode by above-described embodiment by specific topological structure connection type.
In above-mentioned any embodiment when substrate is pcb board, substrate interior cabling can use top layer cabling or bottom cabling in substrate,
The top layer cabling in preferable substrate is realized in practice.
Finally it should be noted that：Above-described each embodiment is merely to illustrate the technical solution of the utility model, rather than
It is limited；Although the utility model is described in detail with reference to the foregoing embodiments, those skilled in the art
It should be understood that：It can still modify to the technical solution recorded in previous embodiment, or to which part or whole
Technical characteristic carries out equivalent replacement；And these modifications or substitutions, it does not separate the essence of the corresponding technical solution the utility model
The range of each embodiment technical solution.
Claims (7)
1. a kind of gallium nitride device, including substrate and Cascode cascade silicon chip and gallium nitride chip on the substrate,
It is characterized in that,
The silicon chip formal dress on the substrate, the gallium nitride chip upside-down mounting on the substrate, the gallium nitride chip
Source electrode, grid and drain electrode be located towards on the face of the substrate, and the source electrode of the gallium nitride chip, grid and drain electrode it is straight
It connects and the pad solder in the substrate interior cabling.
2. gallium nitride device according to claim 1, which is characterized in that the silicon chip and gallium nitride chip installation
On the same face of the substrate.
3. gallium nitride device according to claim 1, which is characterized in that
The electrical connection between the gallium nitride chip and the silicon chip is realized using the cabling on the substrate；
Wherein, the silicon chip drain electrode directly with the pad solder in the substrate interior cabling.
4. gallium nitride device according to claim 3, which is characterized in that
The pad of the drain electrode of the silicon chip and source electrode of the gallium nitride chip, grid and drain electrode pad with respectively
The area of pad is close on cabling in the corresponding substrate.
5. according to claim 1-4 any one of them gallium nitride devices, which is characterized in that the drain electrode of the silicon chip and described
The source electrode of gallium nitride chip respectively with the pad solder in substrate 1 first cabling；
And/or
One end pad solder of one second cabling in the grid and substrate of the gallium nitride chip, the other end of second cabling
One source package pin of pad solder draws one first lead from the source electrode of the silicon chip and makes the end of first lead
It is welded in the other end pad of second cabling；
And/or
One end pad solder of a third cabling in the drain electrode of the gallium nitride chip and substrate, the other end of the third cabling
The drain electrode packaging pin of pad solder one；
And/or
The grid of the silicon chip draws one second lead and using the end of second lead as gate package pin.
6. gallium nitride device according to claim 5, which is characterized in that the substrate is single layer, bilayer or multilayer PCB electricity
Road plate.
7. according to claim 1-4 any one of them gallium nitride devices, which is characterized in that the substrate be single layer, bilayer or
Multilayer PCB circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721770787.5U CN207753000U (en) | 2017-12-18 | 2017-12-18 | A kind of gallium nitride device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721770787.5U CN207753000U (en) | 2017-12-18 | 2017-12-18 | A kind of gallium nitride device |
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| Publication Number | Publication Date |
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| CN207753000U true CN207753000U (en) | 2018-08-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109935561A (en) * | 2017-12-18 | 2019-06-25 | 镓能半导体（佛山）有限公司 | A kind of packaging method of gallium nitride device and gallium nitride device |
-
2017
- 2017-12-18 CN CN201721770787.5U patent/CN207753000U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109935561A (en) * | 2017-12-18 | 2019-06-25 | 镓能半导体（佛山）有限公司 | A kind of packaging method of gallium nitride device and gallium nitride device |
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Granted publication date: 20180821 Termination date: 20201218 |