CN209357719U - A kind of package structure of semiconductor device with low thermal resistance - Google Patents
A kind of package structure of semiconductor device with low thermal resistance Download PDFInfo
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- CN209357719U CN209357719U CN201920247774.2U CN201920247774U CN209357719U CN 209357719 U CN209357719 U CN 209357719U CN 201920247774 U CN201920247774 U CN 201920247774U CN 209357719 U CN209357719 U CN 209357719U
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- thermal resistance
- potting resin
- bonding region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model belongs to technical field of semiconductor encapsulation, a kind of package structure of semiconductor device with low thermal resistance, including semiconductor chip, lead frame and potting resin, lead frame includes metab and pin, the semiconductor chip back side is welded on metab, potting resin lid seals on a semiconductor die, exposed portion pin and part metals pedestal, the pin of exposing is folded upward at extension, and pin end is plane, plane and potting resin surface are in same plane or angle o, and pin end is welded in PCB circuit board；Surface curvature of the pin of the utility model encapsulating structure to potting resin, pin is directly welded in PCB circuit board, and potting resin is contacted with PCB circuit board, and metab heat dissipation is connect with radiator upwardly, it can effectively be radiated by metab and radiator, the thermal resistance of semiconductor devices in the electronic device is greatly reduced, reduces the temperature rise of device, improves device reliability and electronic apparatus system reliability.
Description
Technical field
The utility model relates to package structure of semiconductor device, especially a kind of semiconductor packages with low thermal resistance
Structure belongs to semiconductor device packaging technique field.
Background technique
Semiconductor devices is finally used in PCB circuit board, passes through the route design and semiconductor devices on circuit board
The configuration connection of equal electronic components, can form complete circuit framework, to provide function required for electronic equipment.Semiconductor device
Whether reliably whether connection determines the function of electronic equipment normally between part and circuit board.
Currently, usually having through-hole type and two kinds of patch type between conventional semiconductors power device and circuit board.Through-hole type connects
It connects as shown in Figure 1, in process of production, through-hole type connection needs human weld, and welding efficiency is low, at high cost, and welding process
In often semiconductor devices is caused to damage since manual operation is improper, cause production yield low.And paster type encapsulation
Semiconductor devices be easier to realize electronic equipment mass automatic production, therefore, more and more semiconductor devices use
Patch type is attached with circuit board.For semiconductor power device, using typical paster type encapsulation (such as TO-252,
TO-263 encapsulation) semiconductor power device when directly carrying out electrology characteristic connection with circuit board, the metab of chip (company
Connect MOSFET drain electrode) it needs to weld on circuit boards, the metab for needing high current to flow through chip gets to entire electronics
In route, packaged resistance is increased, as shown in Figure 2.But since semiconductor power device is own power in system work
Very big, other than connecting with the necessary electrology characteristic of circuit board, the heat dissipation characteristics and heat sink conception of semiconductor devices are also very big
The normal use of device is affected in degree.Using the semiconductor power device of the packing forms such as traditional TO-252, TO-263,
Heat dissipation path on circuit board includes two: 1, heat is ultimately conducted in environment by chip by potting resin, radiator；2,
Heat is ultimately conducted in environment by chip by metab, PCB circuit board, radiator.Then, potting resin and PCB electricity
The thermal resistance of road plate is all very big, causes semiconductor power device heat that cannot effectively radiate, and device temperature increases, vulnerable.
In addition to this, the metab area of traditional TO-252, TO-263 encapsulation is smaller, and thermal capacitance is smaller, and chip is caused to exist
Higher temperature overshot is had under transient high power state, causes device vulnerable.
Therefore the packing forms of a kind of low thermal resistance, high heat capacity are needed, to meet system requirements.
Summary of the invention
The utility model, which is directed to after conventional package between semiconductor power device and circuit board, connects existing problems, mentions
For a kind of package structure of semiconductor device and its manufacturing method with low thermal resistance, the pin of the encapsulating structure is to potting resin
Surface curvature enables pin to be directly welded in PCB circuit board, and potting resin is contacted with PCB circuit board, and metab
Heat dissipation is connect with radiator upwardly, can effectively be radiated by metab with radiator in this way, be significantly reduced semiconductor device
The thermal resistance of part in the electronic device reduces the temperature rise of device, the device reliability and electronic apparatus system reliability of raising.
To realize the above technical purpose, the technical solution of the utility model is: a kind of semiconductor devices with low thermal resistance
Encapsulating structure, including semiconductor chip, lead frame and potting resin, which is characterized in that the lead frame includes metal bottom
Seat and the pin connecting with the metab, the back side of the semiconductor chip are welded on metab, the encapsulation tree
Rouge lid is enclosed in the semiconductor core on piece, exposed portion pin and part metals pedestal, and the pin of exposing is folded upward at extension, and
Pin end is plane, and the plane and potting resin surface are in same plane, and the pin end is welded on PCB circuit board
On.
Further, the metab includes the area slide glass Ji Dao and frame body area, the semiconductor chip back side weldering
It connects in the area slide glass Ji Dao, the semiconductor chip front is connect by metal lead wire with bonding region, the bonding region and pin
Connection.
Further, the potting resin lid is enclosed on the area slide glass Ji Dao, bonding region and metal lead wire, exposes frame body
Area and part pin.
Further, the back side of the metab is radiating surface, and the radiating surface is connect by felt pad with cooling fin；
The lower section of the PCB circuit board is equipped with cooling fin.
Further, the semiconductor chip includes MOSFET chip, igbt chip or diode.
Further, for MOSFET chip, the back side of the MOSFET chip is drain electrode, and front is equipped with grid and source
Pole, electricity is connected between grid and the first bonding region, and electricity is connected between source electrode and the second bonding region, and drain electrode passes through slide glass Ji Dao
Area is connected with second pin electricity；For igbt chip, the back side of the igbt chip is collector, and front is equipped with grid and hair
Emitter-base bandgap grading, electricity is connected between grid and the first bonding region, and electricity is connected between emitter and the second bonding region, and collector passes through load
Chip base island area is connected with second pin electricity；For diode, the front of the diode is anode, and the back side is cathode, anode
Electricity is connected between the second bonding region, and cathode is connected by the area slide glass Ji Dao with second pin electricity.
Further, first bonding region is connect with the first pin, and the second bonding region is connect with third pin, and second draws
Foot is arranged between the first pin and third pin.
Further, the angle θ is 0 ~ 8 degree.
Further, the lead frame include TO-220 lead frame, TO-247 lead frame, TO-3P lead frame,
TO-251 lead frame, TO-262 lead frame.
In order to further realize the above technical purpose, the utility model also proposes a kind of semiconductor devices with low thermal resistance
The production method of encapsulating structure, which comprises the steps of:
A. multiple semiconductor chips and row lead wire frame are chosen, the row lead wire frame includes multiple connections arranged side by side
The lead frame of arrangement；
B., the back side of the semiconductor chip is successively mounted on to the load of each lead frame in the row lead wire frame
Chip base island area；
C. the semiconductor chip front electrode is bonded by metal lead wire with corresponding bonding region；
D. the row lead wire frame for being welded with semiconductor chip is subjected to plastic packaging and encapsulating with potting resin, exposes lead
The frame body area of frame and part pin；
E. the row lead wire frame after encapsulating is subjected to hot setting；
F. the redundancy potting resin that do not encapsulated in region on the row lead wire frame is removed；
G. the lead frame for not encapsulating region on the row lead wire frame is carried out tin plating；
H. the row lead wire frame is subjected to rib cutting processing, the frame connection part between cutting removal lead frame, shape
At the device cell after multiple independent encapsulatings；
I. pin is extended to potting resin surface curvature, so that pin end and potting resin surface are in same flat
Face；
J. the test of specified parameter is carried out to above-mentioned every independent device cell, and to meeting test specification requirement
Device carries out laser typewriting on its potting resin surface；
K. the pin of the device cell after encapsulating is welded in PCB circuit board.
Further, which is characterized in that in the step d, the pin includes first be electrically connected with the first bonding region
Pin, the third pin being electrically connected with the second bonding region and the second pin between the first pin, third pin, the encapsulation
The top of semiconductor chip, metal lead wire, bonding region and second pin above the resin package area slide glass Ji Dao.
Compared with conventional semiconductor devices encapsulating structure, the utility model is had the advantage that
1) compared with traditional through-hole type packaged type, when the utility model is connect with PCB circuit board, through-hole weldering is not needed
It connects, pin end plane need to be only welded on pcb board, production yield high-efficient, at low cost is high；
2) it compared with conventional patch formula packaged type, when the utility model is connect with PCB circuit board, does not need chip
Metab is welded on pcb board, and on the one hand upward by metab, while the radiating surface in the area slide glass Ji Dao passes through felt pad
It connect with cooling fin, on the other hand the pin end plane of bending is welded on pcb board, while connecing cooling fin below pcb board；
Therefore, heat dissipation path of the utility model semiconductor devices in PCB circuit board includes: that 1, heat is sealed by semiconductor chip process
Dress resin, PCB circuit board, cooling fin are ultimately conducted in environment；2, heat is by semiconductor chip by metab, insulation
Pad, radiator are ultimately conducted in environment；Since metab and felt pad thermal resistance are very low, the 2nd article of heat dissipation path becomes device
The main heat sink path of part, and there is extremely low thermal resistance, the thermal resistance of semiconductor devices in the electronic device is significantly reduced, is reduced
The temperature rise of device, the device reliability and electronic apparatus system reliability of raising；
3) the utility model metab has biggish area and volume, has bigger thermal capacitance, makes device in moment height
Apparent temperature overshot is not had under power rating, improves the reliability of device；
4) lead frame of the utility model is applicable to the tradition such as TO-220, TO-247, TO-3P, TO-262, TO-251
Encapsulating lead, without again to lead frame be opened, and may be implemented it is conllinear with the producing line of above-mentioned packing forms, be not necessarily to volume
Outer increase process complexity and processing cost, have many advantages, such as that production cost is low, easy to use, have high cost performance.
Detailed description of the invention
Fig. 1 is that tradition TO-220 encapsulates the structural relation schematic diagram connecting with PCB circuit board.
Fig. 2 is that tradition TO-263 encapsulates the structural relation schematic diagram connecting with PCB circuit board.
Fig. 3 is the semiconductor device structure schematic diagram of 1 TO-220 of embodiment encapsulation.
Fig. 4 is the semiconductor devices three-dimensional perspective that embodiment 1 is packaged with MOSFET chip.
Fig. 5 a is the overlooking structure diagram that embodiment 1 is packaged with MOSFET chip.
Fig. 5 b is the overlooking structure diagram that embodiment 1 is packaged with IGBT and diode chip for backlight unit.
Fig. 6 is the side structure schematic view after the encapsulation of embodiment 1.
Fig. 7 is the structural relation schematic diagram that the semiconductor chip after the encapsulation of embodiment 1 is connect with PCB circuit board.
Fig. 8 is the semiconductor device structure schematic diagram of 2 TO-227 of embodiment encapsulation.
Fig. 9 is the semiconductor device structure schematic diagram of 3 TO-3P of embodiment encapsulation.
Figure 10 is the semiconductor device structure schematic diagram of 4 TO-251 of embodiment encapsulation.
Figure 11 is the semiconductor device structure schematic diagram of 5 TO-262 of embodiment encapsulation.
Figure 12 is the semiconductor device structure schematic diagram of 6 TO-220 of embodiment encapsulation.
Figure 13 is the semiconductor device structure schematic diagram of 7 TO-247 of embodiment encapsulation.
Figure 14 is the semiconductor device structure schematic diagram of 8 TO-3P of embodiment encapsulation.
Detailed description of the invention: 1- semiconductor chip, 2- metab, the area 21- slide glass Ji Dao, 22- frame body area, 3- encapsulation tree
Rouge, 4- pin, 5-PCB circuit board, 6- bonding region, 7- felt pad, 8- cooling fin.
Specific embodiment
Below with reference to specific drawings and examples, the utility model is described in further detail.
The utility model embodiment not limited to the following, each figure of institute's reference is to be able to pair in the following description
The content of the utility model is understood and is synoptically indicated to shape, size and positional relationship.That is, this is practical new
Type be not limited to each figure illustrate shown in shape, size and positional relationship.
Embodiment 1: it uses and encapsulates identical lead frame with traditional TO-220；
As shown in Fig. 3, Fig. 4 and Fig. 6, a kind of package structure of semiconductor device with low thermal resistance, including semiconductor chip
1, lead frame and potting resin 3, the lead frame include metab 2 and the pin 4 that connect with the metab 2,
The metab 2 includes the area slide glass Ji Dao 21 and frame body area 22, and 1 back side of semiconductor chip is welded on slide glass Ji Dao
In area 21,1 front of semiconductor chip is connect by metal lead wire with bonding region 6, and the bonding region 6 is connect with pin 4, institute
It states the lid of potting resin 3 to be enclosed in the area slide glass Ji Dao 21, package semiconductor chip 1, bonding region 6 and metal lead wire expose frame sheet
Body area 22 and part pin 4, the pin 4 of exposing is bent to 3 surface direction of potting resin to be extended, and 4 end of pin is plane, institute
It states plane and 3 surface of potting resin and is in same plane or angle o with 3 surface of potting resin, the angle θ is 0 ~ 8 degree, is facilitated and PCB
Circuit board 5 is welded；
As shown in fig. 7,4 end of pin is welded in PCB circuit board 5, the area slide glass Ji Dao 21 of the metab 2
The back side is radiating surface, and the radiating surface is connect by felt pad 7 with cooling fin 8；The lower section of the PCB circuit board 5 is equipped with heat dissipation
Piece 8；
In the present embodiment 1, as shown in Figure 5 a, the semiconductor chip 1 is MOSFET chip, the grid of MOSFET chip front side
Pole is electrically connected by metal lead wire with the first bonding region, and source electrode is electrically connected by metal lead wire with the second bonding region, the first bonding
Area, the second bonding region are connect with the first pin, third pin respectively, and the drain electrode at the back side is connected by the area slide glass Ji Dao and second pin
It connects；As shown in Figure 5 b, the semiconductor chip 1 includes being welded on the igbt chip in 21 left side of the area slide glass Ji Dao and being welded on right side
Diode, the positive grid of igbt chip is electrically connected by metal lead wire with the first bonding region, and emitter passes through metal lead wire
It is electrically connected with the second bonding region, the first bonding region, the second bonding region are connect with the first pin, third pin respectively, the collection at the back side
Electrode is connect by the area slide glass Ji Dao with second pin；The positive anode of diode is electrically connected by metal lead wire and the second bonding region
It connects, the second bonding region is connect with third pin, and the cathode at the back side is connect by the area slide glass Ji Dao with second pin；
Embodiment 2: it uses and encapsulates identical lead frame with traditional TO-247；
As shown in figure 8, same as Example 1, on the semiconductor devices after the encapsulation, three pins are set to encapsulation
The surface curvature of rouge 3, and pin end is in same plane or angle o, the side with 3 surface of potting resin with 3 surface of potting resin
Just it is welded with PCB circuit board 5；
Embodiment 3: it uses and encapsulates identical lead frame with traditional TO-3P；
As shown in figure 9, same as Example 1, on the semiconductor devices after the encapsulation, three pins are set to encapsulation
The surface curvature of rouge 3, and pin end is in same plane or angle o, the side with 3 surface of potting resin with 3 surface of potting resin
Just it is welded with PCB circuit board 5；
Embodiment 4: it uses and encapsulates identical lead frame with traditional TO-251；
As shown in Figure 10, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to encapsulation
The surface curvature of resin 3, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin,
It is convenient to be welded with PCB circuit board 5；
Embodiment 5: it uses and encapsulates identical lead frame with traditional TO-262；
As shown in figure 11, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to encapsulation
The surface curvature of resin 3, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin,
It is convenient to be welded with PCB circuit board 5；
Embodiment 6: it uses and encapsulates identical lead frame with traditional TO-220；
As shown in figure 12, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to encapsulation
The surface curvature of resin 3, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin,
It is convenient to be welded with PCB circuit board 5；
Embodiment 7: it uses and encapsulates identical lead frame with traditional TO-247；
As shown in figure 13, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to encapsulation
The surface curvature of resin 3, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin,
It is convenient to be welded with PCB circuit board 5；
Embodiment 8: it uses and encapsulates identical lead frame with traditional TO-3P；The frame body area of the lead frame
Without hole.
As shown in figure 14, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to encapsulation
The surface curvature of resin 3, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin,
It is convenient to be welded with PCB circuit board 5；
2 ~ embodiment of embodiment 13 is same as Example 1, and 4 end of pin is welded in PCB circuit board 5, the metal
21 back side of the area slide glass Ji Dao of pedestal 2 is radiating surface, and the metab 2 is connect by felt pad 7 with cooling fin 8；The PCB
The lower section of circuit board 5 is equipped with cooling fin 8；
The production method of package structure of semiconductor device of one of the embodiment as above with low thermal resistance, including walk as follows
It is rapid:
A. multiple semiconductor chips 1 and row lead wire frame are chosen, the row lead wire frame includes multiple connections arranged side by side
The lead frame of arrangement；
B. the back side of the semiconductor chip 1 is successively mounted on each lead frame in the row lead wire frame
The area slide glass Ji Dao 21；
C. 1 front electrode of semiconductor chip is bonded by metal lead wire with corresponding bonding region 6；
D. the row lead wire frame for being welded with semiconductor chip 1 is subjected to plastic packaging and encapsulating with potting resin, exposes lead
The frame body area 22 of frame and part pin 4；
The pin 4 includes that the first pin being electrically connected with the first bonding region, the third being electrically connected with the second bonding region are drawn
Foot and the second pin between the first pin, third pin, the potting resin 3 wrap up partly leading above the area slide glass Ji Dao 21
The top of body chip 1, metal lead wire, bonding region 6 and second pin;
E. the row lead wire frame after encapsulating is subjected to hot setting；
F. the redundancy potting resin that do not encapsulated in region on the row lead wire frame is removed, i.e., flash is removed；
G. the lead frame for not encapsulating region on the row lead wire frame is carried out tin plating；
H. the row lead wire frame is subjected to rib cutting processing, the frame connection part between cutting removal lead frame, shape
At the device cell after multiple independent encapsulatings；
I. pin 4 is extended to 3 surface curvature of potting resin, so that 4 end of pin and 3 surface of potting resin are in same
One plane；
J. the test of specified parameter is carried out to above-mentioned every independent device cell, and to meeting test specification requirement
Device carries out laser typewriting on its potting resin surface；
K. the pin 4 of the device cell after encapsulating is welded in PCB circuit board 5.
When the utility model is connect with PCB circuit board 5, the end of pin 4 and PCB circuit board 5 are welded, 3 table of potting resin
Face is directly contacted with PCB circuit board 5, and the heat dissipation of the area slide glass Ji Dao 21 of metab 2 is connect with radiator 8 upwardly；At this point, half
The heat dissipation path of conductor device includes: that 1, heat is finally passed by semiconductor chip by potting resin, PCB circuit board, cooling fin
It is directed in environment；2, heat is ultimately conducted in environment by semiconductor chip by metab, felt pad, radiator；Due to
Metab and felt pad thermal resistance are very low, and the 2nd article of heat dissipation path becomes the main heat sink path of device, and has extremely low heat
Resistance, significantly reduces the thermal resistance of semiconductor devices in the electronic device, reduces the temperature rise of device, the device reliability of raising and
Electronic apparatus system reliability；Connection between the semiconductor power device of the utility model, with PCB circuit board 5 is easier full
The demand of sufficient electronic equipment mass automatic production.
The utility model metab 2 has biggish area and volume, has bigger thermal capacitance, makes device in moment Gao Gong
Apparent temperature overshot is not had under rate state, improves the reliability of device.
The conventional packages lead frames such as the utility model compatible TO-220, TO-247, TO-3P, TO-262, TO-251, nothing
Again lead frame need to be opened, and may be implemented it is conllinear with the producing line of above-mentioned packing forms, it is complicated without additional process
Degree and processing cost, have many advantages, such as that production cost is low, easy to use, have high cost performance.
The utility model and embodiments thereof are described above, description is not limiting, shown in the drawings
It also is one of the embodiments of the present invention, actual structure is not limited to this.All in all if this field it is general
Logical technical staff is enlightened by it, without deviating from the purpose of the present invention, is not inventively designed and is somebody's turn to do
The similar frame mode of technical solution and embodiment, all should belong to the protection range of the utility model.
Claims (8)
1. a kind of package structure of semiconductor device with low thermal resistance, including semiconductor chip (1), lead frame and potting resin
(3), which is characterized in that the lead frame includes metab (2) and the pin (4) connecting with the metab (2), institute
The back side for stating semiconductor chip (1) is welded on metab (2), and potting resin (3) lid is enclosed in the semiconductor chip
(1) on, exposed portion pin (4) and part metals pedestal (2), the pin (4) of exposing are folded upward at extension, and pin (4) end
End is plane, and the plane and potting resin (3) surface are in same plane or angle o with potting resin (3) surface, described to draw
Foot (4) end is welded on PCB circuit board (5).
2. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that the gold
Belonging to pedestal (2) includes the area slide glass Ji Dao (21) and frame body area (22), and semiconductor chip (1) back side is welded on slide glass base
In island area (21), the semiconductor chip (1) front is connect by metal lead wire with bonding region (6), the bonding region (6) with draw
Foot (4) connection.
3. a kind of package structure of semiconductor device with low thermal resistance according to claim 2, which is characterized in that the envelope
Dress resin (3) lid is enclosed on the area slide glass Ji Dao (21), bonding region (6) and metal lead wire, exposes frame body area (22) and part
Pin (4).
4. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that the gold
The back side for belonging to pedestal (2) is radiating surface, and the radiating surface is connect by felt pad (7) with cooling fin (8)；The PCB circuit board
(5) lower section is equipped with cooling fin (8).
5. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that described half
Conductor chip includes MOSFET chip, igbt chip or diode.
6. a kind of package structure of semiconductor device with low thermal resistance according to claim 5, which is characterized in that for
MOSFET chip, the back side of the MOSFET chip are drain electrode, and front is equipped with grid and source electrode, between grid and the first bonding region
Electricity is connected, and electricity is connected between source electrode and the second bonding region, and drain electrode is connected by the area slide glass Ji Dao with second pin electricity；It is right
In igbt chip, the back side of the igbt chip is collector, and front is equipped with grid and emitter, grid and the first bonding region it
Between electricity be connected, electricity is connected between emitter and the second bonding region, and collector passes through the area slide glass Ji Dao and second pin electricity
It is connected；For diode, the front of the diode is anode, and the back side is cathode, electricity phase between anode and the second bonding region
Even, cathode is connected by the area slide glass Ji Dao with second pin electricity；First bonding region is connect with the first pin, the second bonding
Area is connect with third pin, and second pin is arranged between the first pin and third pin.
7. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that the θ
Angle is 0 ~ 8 degree.
8. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that described to draw
Wire frame includes that TO-220 lead frame, TO-247 lead frame, TO-3P lead frame, TO-251 lead frame, TO-262 draw
Wire frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109727943A (en) * | 2019-02-27 | 2019-05-07 | 无锡新洁能股份有限公司 | A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance |
| WO2024051228A1 (en) * | 2022-09-09 | 2024-03-14 | 苏州汇川控制技术有限公司 | Power device and power apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727943A (en) * | 2019-02-27 | 2019-05-07 | 无锡新洁能股份有限公司 | A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance |
| WO2024051228A1 (en) * | 2022-09-09 | 2024-03-14 | 苏州汇川控制技术有限公司 | Power device and power apparatus |
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