CN219832657U - Packaging structure of laminated chip - Google Patents
Packaging structure of laminated chip Download PDFInfo
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- CN219832657U CN219832657U CN202320192009.1U CN202320192009U CN219832657U CN 219832657 U CN219832657 U CN 219832657U CN 202320192009 U CN202320192009 U CN 202320192009U CN 219832657 U CN219832657 U CN 219832657U
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- chip
- conductive pad
- electrode pin
- connecting column
- packaging
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000017525 heat dissipation Effects 0.000 claims description 10
- 239000000945 filler Substances 0.000 claims description 9
- 239000000565 sealant Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005476 soldering Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The utility model relates to the field of semiconductors, in particular to a packaging structure of a laminated chip, which comprises a first chip, a substrate and a first connecting conductive pad, wherein a packaging layer is arranged at the upper end of the substrate, a first front electrode pin is arranged at the lower end of a packaging groove, a first connecting column is fixed at the upper end of the first front electrode pin, the first chip is arranged at the upper end of the first connecting column, the first conductive pad is arranged at the upper end of the first chip, a fourth connecting column is arranged at the lower end of the first conductive pad, a second back electrode pin is arranged at the lower end of the fourth connecting column, a second front electrode pin is arranged at the upper end of the substrate, and the upper end of the third connecting conductive pad is connected with the second chip.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a package structure for stacked chips.
Background
The integrated circuit chip is an electronic element comprising a silicon substrate, at least one circuit, a fixed sealing ring, a grounding ring and at least one protection ring, along with the rapid development of the semiconductor industry, the miniaturization of electronic products is thinner and thinner to meet the requirements of users and the higher and higher product performance and memory, along with the improvement of the requirements of the market on the integration level of power devices, the chip stacking technology can lead the packaging volume to be smaller and the power density of the products to be improved.
In the related art, in order to ensure the electric and heat conduction performance of the power device, many traditional packaging technologies use copper sheets as connection, and due to the stacking of 2 layers of chips and copper sheets, the chips and the copper sheets are easy to incline in the reflow soldering operation process, so that the uneven solder layer affects the reliability of the product, and meanwhile, due to the inclination of the chips and the pollution of soldering flux, the higher solder joint is insufficient and is not welded, therefore, we propose a packaging structure of a laminated chip.
The above information disclosed in this background section is only for the understanding of the background of the inventive concept and, therefore, it may contain information that does not form the prior art.
Disclosure of Invention
The utility model aims to provide a packaging structure of a laminated chip, which solves the problems that the traditional packaging technology proposed in the background technology uses copper sheets for connection, the chip and the copper sheets are easy to incline in the reflow soldering operation process due to the stacking of 2 layers of chips and copper sheets, the uneven solder layer affects the reliability of a product, and simultaneously, the chip incline and the pollution of soldering flux cause high solder joint cold joint and no soldering.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the utility model provides a packaging structure of stromatolite chip, includes first chip, second chip, base plate and first connection conductive pad, the installation of base plate upper end is provided with the encapsulation layer, the inside encapsulation groove that is provided with of encapsulation layer, the left side lower extreme installation of encapsulation groove is provided with first positive electrode pin, the fixed first spliced pole that is provided with in upper end of first positive electrode pin, the upper end connection of first spliced pole is provided with first connection conductive pad, first connection conductive pad upper end connection is provided with first chip, first chip upper end is fixed and is provided with the third spliced pole, the fixed first conductive pad that is provided with in upper end of third spliced pole, the right side lower extreme installation of first conductive pad is provided with the fourth spliced pole, the lower extreme installation of fourth spliced pole is provided with first back electrode pin, the lower extreme of first back electrode pin is fixed with the up end of base plate and is provided with the second positive electrode pin, the upper end central point of base plate is connected and is provided with the second electrode pin, the upper end connection of second positive electrode pin is provided with the second connection pad and second chip upper end is connected with the second conductive pad.
In some embodiments, a second connection post is disposed between the upper end of the second chip, a second conductive pad is disposed at the upper end of the second connection post, a fifth connection post is disposed at the lower end of the right side of the second conductive pad, the lower end of the fifth connection post is disposed at the upper end of the second back electrode pin, and the lower end of the second back electrode pin is disposed at the upper end face of the substrate.
In some embodiments, a third connection conductive pad is connected to an upper end of the second conductive pad, and an upper end of the third connection conductive pad is connected to a right lower end of the first chip.
In some embodiments, a plurality of groups of gas channels are formed on the side surface of the packaging layer, and a plurality of groups of lattice pads are fixedly arranged on the side surface of the packaging layer.
In some embodiments, a block-shaped bonding pad is arranged at the connection part of the upper end of the substrate and the packaging layer.
In some embodiments, a heat dissipation filler is filled and arranged between the first chip and the second chip in the packaging groove, and the heat dissipation filler is heat-conducting insulating pouring sealant.
The beneficial effects of the utility model are as follows:
according to the utility model, the plurality of groups of connecting columns and electrode pins are arranged, so that each electrode of the first chip and the second chip can be led to the corresponding pin for rearrangement, the packaging design is more flexible, the packaging structure area is smaller, the integration level is higher, the heat dissipation filler is arranged around the first chip and the second chip, the heat dissipation capacity of the chip can be improved, the working temperature of the chip is reduced, and meanwhile, the plurality of groups of conductive pads and the connecting conductive pads are arranged, so that the conductive performance of the structure can be improved through larger current.
Drawings
Fig. 1 is a schematic structural diagram of a package structure of a stacked chip according to the present utility model;
fig. 2 is a schematic top view of a package layer of a package structure of a stacked chip according to the present utility model.
In the figure: 1 is a packaging layer, 2 is a first connecting conductive pad, 3 is a first connecting column, 4 is a lattice type bonding pad, 5 is a first front electrode pin, 6 is a second connecting conductive pad, 7 is a second chip, 8 is a second conductive pad, 9 is a second connecting column, 10 is a heat radiation filler, 11 is a second back electrode pin, 12 is a first back electrode pin, 13 is a substrate, 14 is a block type bonding pad, 15 is a gas channel, 16 is a first conductive pad, 17 is a third connecting conductive pad, 18 is a first chip, 19 is a packaging groove, 20 is a third connecting column, 21 is a fourth connecting column, 22 is a second front electrode pin, and 23 is a fourth connecting column.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments.
It should be noted that, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like refer to an azimuth or a positional relationship based on that shown in the drawings, or that the inventive product is commonly put in place when used, merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present utility model.
In the description of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1 and 2, a package structure of stacked chips includes a first chip 18, a second chip 7, a substrate 13 and a first connection conductive pad 2, wherein a package layer 1 is installed at the upper end of the substrate 13, a package groove 19 is installed inside the package layer 1, a first front electrode pin 5 is installed at the lower end of the left side of the package groove 19, a first connection column 3 is fixedly arranged at the upper end of the first front electrode pin 5, the first connection conductive pad 2 is connected and arranged at the upper end of the first connection column 3, the first chip 18 is connected and arranged at the upper end of the first connection conductive pad 2, a third connection column 20 is fixedly arranged at the upper end of the first chip 18, a first conductive pad 16 is fixedly arranged at the upper end of the third connection column 20, a fourth connection column 21 is installed at the lower end of the first conductive pad 16, a first back electrode pin 12 is fixedly arranged at the lower end of the fourth connection column 21, a second front electrode pin 22 is fixedly arranged at the central position of the upper end of the substrate 13, a second front electrode pin 22 is fixedly arranged at the upper end of the second connection column 22, and the second connection pad 6 is connected and the upper end of the second connection conductive pad 6 is arranged at the upper end of the second chip 6.
In the embodiment of the utility model, as shown in fig. 1, the upper end of the second chip 7 is provided with the second connecting column 9, the upper end of the second connecting column 9 is provided with the second conductive pad 8, the lower end of the right side of the second conductive pad 8 is provided with the fifth connecting column 23 in a connecting way, the lower end of the fifth connecting column 23 is connected with the upper end of the second back electrode pin 11, the lower end of the second back electrode pin 11 is connected with the upper end face of the substrate 13, and the arranged second conductive pad 8 improves the conductive performance of the second chip 7 and improves the current bearing capacity of the structure to a certain extent.
In the embodiment of the utility model, as shown in fig. 1, the upper end of the second conductive pad 8 is connected with a third connection conductive pad 17, the upper end of the third connection conductive pad 17 is connected with the lower right end of the first chip 18, a plurality of groups of gas channels 15 are formed on the side surface of the packaging layer 1, a plurality of groups of matrix type bonding pads 4 are fixedly arranged on the side surface of the packaging layer 1, and a plurality of groups of circuits are arranged inside the packaging layer 1, so that the packaging structure is electrically connected with the outside.
In the embodiment of the utility model, as shown in fig. 1, a block-shaped bonding pad 14 is arranged at the joint of the upper end of a substrate 13 and a packaging layer 1, a heat dissipation filler 10 is filled in a packaging groove 19 between a first chip 18 and a second chip 7, and the heat dissipation filler 10 is heat conduction insulating pouring sealant, and has good heat conduction performance, excellent insulativity, excellent electrical performance, good adhesion and good surface gloss after solidification.
In this embodiment, a plurality of groups of connection columns and electrode pins are provided, so that each electrode of the first chip 18 and the second chip 7 can be led to the corresponding pin to be rearranged, the packaging design is more flexible, the packaging structure area is smaller, the integration level is higher, the heat dissipation filler 10 is arranged around the first chip 18 and the second chip 7, the heat dissipation capacity of the chip can be improved, the temperature of the chip during operation is reduced, and meanwhile, the plurality of groups of conductive pads and the connection conductive pads are arranged, and the conductive performance of the structure is improved through larger current.
The foregoing is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any person skilled in the art, who is within the scope of the present utility model, should make equivalent substitutions or modifications according to the technical scheme of the present utility model and the inventive concept thereof, and should be covered by the scope of the present utility model.
Claims (6)
1. The utility model provides a packaging structure of stromatolite chip, includes first chip (18), second chip (7), base plate (13) and first connection conductive pad (2), its characterized in that: the packaging structure is characterized in that a packaging layer (1) is arranged at the upper end of the substrate (13), a packaging groove (19) is formed in the packaging layer (1), a first front electrode pin (5) is arranged at the lower end of the left side of the packaging groove (19), a first connecting column (3) is fixedly arranged at the upper end of the first front electrode pin (5), a first connecting conductive pad (2) is arranged at the upper end of the first connecting column (3), a first chip (18) is arranged at the upper end of the first connecting conductive pad (2), a third connecting column (20) is fixedly arranged at the upper end of the first chip (18), a first conductive pad (16) is fixedly arranged at the upper end of the third connecting column (20), a fourth connecting column (21) is arranged at the lower end of the right side of the first conductive pad (16), a first back electrode pin (12) is arranged at the lower end of the fourth connecting column (21), a first back electrode pin (12) is fixedly arranged at the upper end face of the substrate (13), a second conductive pad (22) is arranged at the upper end of the first back electrode pin (12), and a second conductive pad (6) is fixedly arranged at the upper end of the second front electrode pin (6).
2. The packaging structure of the laminated chip according to claim 1, wherein a second connecting column (9) is arranged at the upper end of the second chip (7), a second conductive pad (8) is arranged at the upper end of the second connecting column (9), a fifth connecting column (23) is arranged at the lower end of the right side of the second conductive pad (8) in a connecting manner, the lower end of the fifth connecting column (23) is connected with the upper end of a second back electrode pin (11), and the lower end of the second back electrode pin (11) is connected with the upper end face of the substrate (13).
3. The packaging structure of the laminated chip according to claim 2, wherein a third connection conductive pad (17) is connected to the upper end of the second conductive pad (8), and the upper end of the third connection conductive pad (17) is connected to the right lower end of the first chip (18).
4. The packaging structure of the laminated chip according to claim 1, wherein a plurality of groups of gas channels (15) are formed on the side surface of the packaging layer (1), and a plurality of groups of lattice pads (4) are fixedly arranged on the side surface of the packaging layer (1).
5. The packaging structure of the laminated chip according to claim 1, wherein a block-shaped bonding pad (14) is arranged at the connection part of the upper end of the substrate (13) and the packaging layer (1).
6. The packaging structure of the laminated chip according to claim 1, wherein a heat dissipation filler (10) is filled in the packaging groove (19) between the first chip (18) and the second chip (7), and the heat dissipation filler (10) is a heat conduction insulating pouring sealant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320192009.1U CN219832657U (en) | 2023-02-13 | 2023-02-13 | Packaging structure of laminated chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320192009.1U CN219832657U (en) | 2023-02-13 | 2023-02-13 | Packaging structure of laminated chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219832657U true CN219832657U (en) | 2023-10-13 |
Family
ID=88284164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320192009.1U Active CN219832657U (en) | 2023-02-13 | 2023-02-13 | Packaging structure of laminated chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219832657U (en) |
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2023
- 2023-02-13 CN CN202320192009.1U patent/CN219832657U/en active Active
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