CN219163395U - 3D stacks up packaging structure - Google Patents
3D stacks up packaging structure Download PDFInfo
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- CN219163395U CN219163395U CN202223104766.3U CN202223104766U CN219163395U CN 219163395 U CN219163395 U CN 219163395U CN 202223104766 U CN202223104766 U CN 202223104766U CN 219163395 U CN219163395 U CN 219163395U
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Abstract
The utility model discloses a 3D stacked package structure, which is provided with first solder balls of a multi-chip package body so as to be connected with an external device. The arrangement of the first metal wiring layer, the second metal wiring layer and the metal connecting column of the conductive structure is convenient for reducing the lead bonding distance of the lead bonding chip on one hand, and has high integration level; on the other hand in order to be convenient for through the setting of second metal wiring layer, realize the Z to interconnect between wire bonding chip, multichip package body, the fan-out chip package body three, can shorten electric connection, be favorable to the performance of chip function. And the lead bonding chip and the fan-out chip are arranged in the chip package body so as to realize 3D stacking of multiple chips. The fan-out chip package body is arranged between the first solder balls, so that the space in the package structure is fully utilized while interconnection with the multi-chip package body is realized, the integration level is higher, and the reduction of the package volume is facilitated. The first plastic layer is arranged so as to play a role in protection.
Description
Technical Field
The utility model relates to a 3D stacked package structure.
Background
With the development of miniaturization, high density, high reliability and low power consumption of electronic products, 3D packaging with multiple chips and devices integrated in the same packaging body becomes a new direction meeting the technical development, wherein the laminated 3D packaging has wide application prospect due to the characteristics of high integration level, light weight, small packaging size, low manufacturing cost and the like.
Chinese publication No. CN109786347a discloses a fan-out package structure of a chip and a packaging method, which includes a plurality of metal terminals, a first chip, a second chip, a lead, a package layer, a lead-out layer, etc., and is capable of realizing signal interconnection of stacking multiple chips in Z direction through the plurality of metal terminals. However, when the fan-out three-dimensional package is stacked in the vertical direction of different types of chips, the overall package size is large, which is not beneficial to being applied to smaller electronic products. In addition, the chip is electrically connected with the outside for a long time, so that the function of the chip is affected.
Therefore, how to overcome the above-mentioned drawbacks has become an important issue to be solved by the person skilled in the art.
Disclosure of Invention
The utility model overcomes the defects of the technology and provides a 3D stacking and packaging structure.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
a 3D stacked package structure, comprising:
the multi-chip package comprises a conductive structure 11 for interconnecting an upper-layer package component and a lower-layer package component, and a first solder ball 12 connected with the bottom of the conductive structure 11, wherein the conductive structure 11 comprises a first metal wiring layer 111 exposed on the upper surface of the multi-chip package, a second metal wiring layer 112 connected with the first solder ball 12, and a metal connecting column 113 for vertically communicating the first metal wiring layer 111 with the second metal wiring layer 112;
a wire bonding chip 2, wherein the wire bonding chip 2 is connected to the upper surface of the multi-chip package in a stacking way, and a first bonding pad 21 is arranged on the upper surface of the wire bonding chip 2;
a lead 3, the lead 3 electrically connecting the first pad 21 to the first metal wiring layer 111;
a first molding layer 4 for covering the components above the multi-chip package;
the fan-out chip package 5 is disposed between the first solder balls 12 and connected to the second metal wiring layer 112 in a flip-chip manner.
Preferably, the multi-chip package further includes a first chip 13 and a second chip 14, the lower end surfaces of the first chip 13 and the second chip 14 are connected with a glue layer 15, the second metal wiring layer 112 is covered with a solder mask layer 16 for insulating protection between the same layers, and a second plastic layer 17 is disposed between the first metal wiring layer 111 and the glue layer 15.
Preferably, the adhesive layer 15 is provided with a plurality of first via holes 151 for communicating the chip with the second metal wiring layer 112, and the first via holes 151 are filled with conductive metal.
Preferably, the solder mask layer 16 is provided with a plurality of first openings 161 for connecting the first solder balls 12 with the second metal wiring layer 112, and a plurality of second openings 162 for connecting the fan-out chip package 5 with the second metal wiring layer 112.
Preferably, the exposed portions of the first metal wiring layer 111 and the second metal wiring layer 112 are provided with an oxidation preventing layer for preventing oxidation.
Preferably, the fan-out chip package 5 includes a third chip 51, a third plastic layer 52 for wrapping the third chip 51, and a third metal wiring layer 53 connected to the bottom of the third chip 51, where a portion of the third metal wiring layer 53 exposed is connected to a second solder ball 54.
Preferably, the height of the first solder balls 12 is greater than the height of the fan-out chip package 5, and an installation space capable of being used for the fan-out chip package 5 to be flipped under the multi-chip package is provided between the first solder balls 12.
Preferably, the number of the wire bonding chips 2 is N, wherein N is more than or equal to 1.
Preferably, the adhesive layer 15 is a DAF layer.
Preferably, the material of the lead 3 is gold, copper, aluminum or a combination thereof.
Compared with the prior art, the utility model has the beneficial effects that:
1. the multi-chip package is simple in structure and easy to realize, and the multi-chip package is arranged so as to package various chips into a whole. The arrangement of the first solder balls facilitates connection with external components/external devices to facilitate use of the package structure itself. The arrangement of the first metal wiring layer, the second metal wiring layer and the metal connecting column of the conductive structure is convenient for reducing the lead bonding distance of the lead bonding chip on one hand and has high integration level; on the other hand in order to be convenient for through the setting of second metal wiring layer, realize the Z to interconnect between wire bonding chip, multichip package body, the fan-out chip package body three, can shorten electric connection, be favorable to the performance of chip function. The arrangement of the wire bonding chip and the fan-out chip package is convenient for stacking and connecting the wire bonding chip and the fan-out chip package on the multi-chip package so as to realize 3D stacking of multiple chips. The fan-out chip package bodies are arranged between the first solder balls, so that the fan-out chip package bodies are convenient to interconnect with the multi-chip package bodies, meanwhile, the space in the package structure is fully utilized, the integration level is high, and the reduction of the package volume is facilitated. The first plastic sealing layer is arranged so as to protect the components covered inside the first plastic sealing layer and is arranged so as to be integrally packaged with the multi-chip packaging body.
2. The first chip and the second chip of the multi-chip package body are arranged, so that a plurality of chips can be integrated into a whole, and integration of the multiple chips is realized; the arrangement of the adhesive layer is convenient for bonding the first chip and the second chip, and reduces the offset of the chip after the chip is mounted. The arrangement of the solder mask layer is convenient for the insulation protection between the same-layer metals and prevents the parts which are not welded from being connected by soldering tin. The second plastic sealing layer is arranged so as to play a role in insulating and protecting the parts covered on the inner part.
Drawings
Fig. 1 is a schematic diagram of a package structure of the present disclosure.
Fig. 2 is a schematic diagram of a multi-chip package according to the present disclosure.
Fig. 3 is a schematic diagram of a fan-out chip package according to the present disclosure.
Detailed Description
The following examples are provided to illustrate the features of the present utility model and other related features in further detail to facilitate understanding by those skilled in the art:
as shown in fig. 1 to 3, a 3D stacked package structure includes:
the multi-chip package comprises a conductive structure 11 for interconnecting an upper-layer package component and a lower-layer package component, and a first solder ball 12 connected with the bottom of the conductive structure 11, wherein the conductive structure 11 comprises a first metal wiring layer 111 exposed on the upper surface of the multi-chip package, a second metal wiring layer 112 connected with the first solder ball 12, and a metal connecting column 113 for vertically communicating the first metal wiring layer 111 with the second metal wiring layer 112;
a wire bonding chip 2, wherein the wire bonding chip 2 is connected to the upper surface of the multi-chip package in a stacking way, and a first bonding pad 21 is arranged on the upper surface of the wire bonding chip 2;
a lead 3, the lead 3 electrically connecting the first pad 21 to the first metal wiring layer 111;
a first molding layer 4 for covering the components above the multi-chip package;
the fan-out chip package 5 is disposed between the first solder balls 12 and connected to the second metal wiring layer 112 in a flip-chip manner.
The multi-chip package is simple in structure and easy to realize, and the multi-chip package is arranged so as to package various chips into a whole. The first solder balls 12 are provided to facilitate connection with external components/devices to facilitate use of the package structure itself. The arrangement of the first metal wiring layer 111, the second metal wiring layer 112, and the metal connection pillars 113 of the conductive structure 11 is convenient for reducing the wire bonding distance of the wire bonding chip 2, and has high integration; on the other hand, the second metal wiring layer 112 is convenient for realizing the Z-direction interconnection among the wire bonding chip 2, the multi-chip package body and the fan-out chip package body 5, so that the electrical connection can be shortened, and the function of the chip can be exerted. The wire bonding chip 2 and the fan-out chip package 5 are arranged so as to be conveniently stacked and connected on the multi-chip package, so that 3D stacking of multiple chips is conveniently realized. The fan-out chip package 5 is arranged between the first solder balls 12, so that the space in the package structure is fully utilized while interconnection with the multi-chip package is realized, the integration level is high, and the reduction of the package volume is facilitated. The first plastic layer 4 is provided so as to protect the components covered inside, and so as to be integrally packaged with the multi-chip package.
As shown in fig. 2, in the implementation, the multi-chip package further includes a first chip 13 and a second chip 14, the lower end surfaces of the first chip 13 and the second chip 14 are connected with a glue layer 15, the second metal wiring layer 112 is covered with a solder mask layer 16 for insulating protection between the same layers of metals, and a second plastic sealing layer 17 is disposed between the first metal wiring layer 111 and the glue layer 15.
As described above, the first chip 13 and the second chip 14 of the multi-chip package are arranged so as to integrate a plurality of chips, thereby realizing integration of multiple chips; the glue layer 15 is provided to facilitate adhesion of the first chip 13 and the second chip 14, and reduce offset after chip mounting. The provision of the solder mask layer 16 facilitates insulation protection between the same layer of metal, preventing parts that are not to be soldered from being connected by solder. The second plastic layer 17 is provided so as to provide insulation protection for the components covered inside.
As shown in fig. 2, the adhesive layer 15 is provided with a plurality of first via holes 151 for communicating the chip with the second metal wiring layer 112, and the first via holes 151 are filled with conductive metal. As such, to facilitate conductive interconnection of the chips within the multi-chip package with the second metal wiring layer 112. In specific implementation, the pins at the bottom of the first chip 13 and the pins at the bottom of the second chip 14 are connected with the conductive metal in the first via 151 and then connected with the second metal wiring layer 112, so as to realize interconnection between chips.
As shown in fig. 2, in the implementation, the solder mask layer 16 is provided with a plurality of first openings 161 for connecting the first solder balls 12 with the second metal wiring layer 112, and a plurality of second openings 162 for connecting the fan-out chip package 5 with the second metal wiring layer 112. In this manner, portions of the second metal wiring layer 112 are conveniently exposed to facilitate conductive interconnection of the multi-chip package with the component/external device through the second metal wiring layer 112.
As shown in fig. 2, the exposed portions of the first metal wiring layer 111 and the second metal wiring layer 112 are provided with an oxidation preventing layer for preventing oxidation. Therefore, the oxidation of the metal wiring layer exposed outside can be prevented, and the reliability of the packaging structure can be improved.
As shown in fig. 3, in the implementation, the fan-out chip package 5 includes a third chip 51, a third plastic layer 52 for wrapping the third chip 51, and a third metal wiring layer 53 connected to the bottom of the third chip 51, where a portion of the third metal wiring layer 53 exposed outside is connected to a second solder ball 54. Thus, the multi-chip package is convenient to stack and connect, so that the multi-chip package is convenient to stack in 3D, fan-out type packaging is used, the multi-chip package can be directly flipped without using a packaging carrier plate, and the integration level is high.
In this way, the height of the first solder balls 12 is greater than the height of the fan-out chip package 5, and an installation space for the fan-out chip package 5 to flip-chip below the multi-chip package is provided between the first solder balls 12. In this way, when the multi-chip package is provided with the first solder balls 12, the fan-out chip package 5 can be directly connected under the multi-chip package in a flip-chip manner, so that the space between the first solder balls 12 can be fully utilized, the integration level is high, and the reduction of the package volume is facilitated. In specific implementation, after the wire bonding chip 2 and the multi-chip package are encapsulated by the first plastic encapsulation layer 4, the multi-chip package is turned over by 180 degrees, so that the bottom surface of the multi-chip package faces upwards, and then the fan-out chip package 5 is reversely arranged between the first solder balls 12 and connected with the second metal wiring layer 112. The multi-chip package designs the circuit pattern of the second metal wiring layer 112 in advance, so that the first solder balls 12 can not obstruct the flip-chip of the fan-out chip package 5.
In the implementation, the number of the wire-bonded chips 2 is N, where N is greater than or equal to 1. Thus facilitating the integration of more chips.
In this embodiment, the adhesive layer 15 is a DAF layer. Therefore, the problem that the current soft solder and the adhesive sheet are used for ultra-small and ultra-thin chips and cannot be used for stacking and packaging can be solved, so that the soft solder and the adhesive sheet can be conveniently adhered to the chips, and a stable 3D stacking and packaging structure can be realized.
In the above embodiments, the material of the lead 3 is gold, copper, aluminum or a combination thereof. In this way, it is possible to function as a conductive interconnect.
As described above, the present disclosure protects a 3D stacked package structure, and all technical schemes identical or similar to the present disclosure should be shown as falling within the scope of the present disclosure.
Claims (10)
1. A 3D stacked package structure, characterized by comprising:
the multi-chip package comprises a conductive structure (11) for interconnecting an upper-layer package component and a lower-layer package component, and a first solder ball (12) connected with the bottom of the conductive structure (11), wherein the conductive structure (11) comprises a first metal wiring layer (111) exposed on the upper surface of the multi-chip package, a second metal wiring layer (112) connected with the first solder ball (12), and a metal connecting column (113) for vertically communicating the first metal wiring layer (111) with the second metal wiring layer (112);
the wire bonding chip (2), the wire bonding chip (2) is connected to the upper surface of the multi-chip package in a stacking way, and a first bonding pad (21) is arranged on the upper surface of the wire bonding chip (2);
-a lead (3), said lead (3) electrically connecting said first pad (21) to said first metal wiring layer (111);
a first plastic layer (4) for covering the components above the multi-chip package;
the fan-out chip package (5) is arranged between the first solder balls (12) and is connected with the second metal wiring layer (112) in a flip-chip mode.
2. The 3D stacked package structure according to claim 1, wherein the multi-chip package body further comprises a first chip (13) and a second chip (14), the lower end surfaces of the first chip (13) and the second chip (14) are connected with a glue layer (15), the second metal wiring layer (112) is covered with a solder mask layer (16) for insulating protection between the same-layer metals, and a second plastic sealing layer (17) is arranged between the first metal wiring layer (111) and the glue layer (15).
3. The 3D stacked package structure according to claim 2, wherein the glue layer (15) is provided with a plurality of first via holes (151) for communicating the chip with the second metal wiring layer (112), and the first via holes (151) are filled with conductive metal.
4. The 3D stacked package structure according to claim 2, wherein the solder mask layer (16) is provided with a plurality of first openings (161) for connecting the first solder balls (12) and the second metal wiring layer (112), and a plurality of second openings (162) for connecting the fan-out chip package (5) and the second metal wiring layer (112).
5. A 3D stacked package structure according to claim 1, characterized in that the exposed portions of the first metal wiring layer (111) and the second metal wiring layer (112) are provided with an oxidation preventing layer for preventing oxidation.
6. The 3D stacked package structure according to claim 1, wherein the fan-out chip package body (5) includes a third chip (51), a third plastic layer (52) for wrapping the third chip (51), and a third metal wiring layer (53) connected to a bottom of the third chip (51), and a second solder ball (54) is connected to an exposed portion of the third metal wiring layer (53).
7. The 3D stacked package structure according to claim 1, wherein the height of the first solder balls (12) is greater than the height of the fan-out chip package (5), and an installation space capable of allowing the fan-out chip package (5) to be flipped under the multi-chip package is provided between the first solder balls (12).
8. The 3D stacked package structure of claim 1, wherein the number of wire-bonded chips (2) is N, wherein N is equal to or greater than 1.
9. A 3D stacked package structure according to claim 2 or 3, characterized in that the glue layer (15) is a DAF layer.
10. A 3D stacked package structure according to claim 1, characterized in that the material of the leads (3) is gold or copper or aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223104766.3U CN219163395U (en) | 2022-11-22 | 2022-11-22 | 3D stacks up packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223104766.3U CN219163395U (en) | 2022-11-22 | 2022-11-22 | 3D stacks up packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219163395U true CN219163395U (en) | 2023-06-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223104766.3U Active CN219163395U (en) | 2022-11-22 | 2022-11-22 | 3D stacks up packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN219163395U (en) |
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- 2022-11-22 CN CN202223104766.3U patent/CN219163395U/en active Active
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