407446407446
發明領域： 本發明係有關一種電子裝置之 法· ’尤指具有球狀閘排（BaH 子裝置及其形成之方法。 發明背景： 封.裝構造及其形成的方 Array ; BGA)封裝之電. 地提：電路技術的進步’以及晶片上電路功能不斷 件體積積體電路之發展走向高度集積化，所以，元 1千體積愈來愈縮小，而功能卻兪 凡 體電路的封愈來愈強大’因此，整個積 电岭们封裝也愈來愈小，但積 只 點卻愈來愈多，然巾，一個單路曰3片需求的電路端 限制，不是I^11 ^ 積體電路晶片由於面積的 片的電路端點一旦增加，對庫=電路晶 之電路佈局的問題，通常採；多慮對應 服多電路輪屮她々Ba 不甩夕層印刷電路板基材’以克 並排，然後加U °題。習知之多晶片封裝是以兩顆晶片 倍略小ΰ j ^裝，其總面積相當於傳統單顆包裝的兩 '點，但仍佔有較大之面積。 略大 點 増加有限的面^ ^困擾，本發明便是在基板（SUbStrate) 形成的方法，掸Γ，提供一種簡易的多晶片封裝構造及其 封裝輸出端數目^積體電路封裝的電路輸出端數目達傳統 上、下堆聶式射^ —倍以上，詳言之，本發明係採用晶片 _ 、法，所以面積大小只比傳統之單顆封裝 發明目的與概述： 号务明主潑 要目的即在提出一種增加積體電路單一封Field of the Invention: The present invention relates to a method of an electronic device. "Especially has a ball gate (BaH sub-device and method of forming it. Background of the invention: encapsulation. Package structure and formed square array; BGA) package electrical Tips: Advances in circuit technology, and the development of circuit functions on the chip continue to increase the volume of integrated circuits. Therefore, the volume of 1,000 yuan is shrinking, but the functions are more and more sealed. Powerful '. Therefore, the package of the entire Jaeger Ridge is getting smaller and smaller, but there are more and more points. However, a single circuit is limited by the demand for 3 circuit ends, not an I ^ 11 ^ integrated circuit chip. Due to the increase in the area of the circuit end points of the chip, the problem of the circuit layout of the library = circuit crystal is usually adopted; more consideration should be given to the service of multiple circuit wheels. She does not remove the printed circuit board substrate. Then add U ° questions. The conventional multi-chip package is packaged with two chips, which is slightly smaller than the package size. Its total area is equivalent to two points of a traditional single package, but it still occupies a larger area. Slightly larger, plus limited surface ^^ ^ The present invention is a method for forming a substrate (SUbStrate), 掸 Γ, provides a simple multi-chip package structure and the number of package output terminals ^ circuit output terminals of integrated circuit packaging The number reaches more than the traditional upper and lower stacking Nie-type shots ^-times, in detail, the present invention uses the wafer method, so the area size is only larger than the traditional single package. The purpose and summary of the invention: That is to propose a single increase in integrated circuit
407446 五、發明說明(2) 裝之電路輸出端數目之裝置。 本發明之另一目的係在提供一種多晶片堆疊封裝之技 術0 本發明使用上下堆疊的晶片，安裝於基板上，下層晶 片藉著凸塊（bump)連接至.基板上，上層晶片藉著引線 — (wire bond)連接至基板上，更可於堆疊的晶片之間，置 入導電物（conductor) ’以加強散熱、隔離電磁干擾 (Ele'ctro-Magnetic Interference; EMI)及訊號間的交錯 干擾（cross talk)。 為了對本發明之目的、技術内容、特徵及其所達成之 功效有更進一步之瞭解與認識，謹佐以較佳之實施例圖式 及配合詳細之說明，說明如后： 圖式簡單說明： 1,圖式說明：. 第1圖為一實施例之示意圖。 第2圖為一具有球狀閘排封裝實施例之剖視圖。 第3圖為第2圖所示實施例之電路連接之示意圖 第4圖為具有金屬板之一實施例。 第5圖為具有金屬板之另一實施例。 第6圖為具有腳架導電金屬板之各種實施例。 第7圖為第2圖所示實施例之封裝流程圖。 2.圖號說明： lr 電路端407446 V. Description of the invention (2) Device for the number of circuit output terminals installed. Another object of the present invention is to provide a multi-chip stacked package technology. The present invention uses stacked wafers mounted on a substrate, and the lower wafer is connected to the substrate through bumps. The upper wafer is connected to the substrate through leads. — (Wire bond) is connected to the substrate, and a conductor can be placed between the stacked chips to enhance heat dissipation and isolate electromagnetic interference (Ele'ctro-Magnetic Interference; EMI) and interleaving interference between signals (Cross talk). In order to further understand and understand the purpose, technical content, features and achieved effects of the present invention, I would like to provide a detailed description of the preferred embodiment and the detailed description, as described below: Brief description of the diagram: 1, Description of the drawings: Fig. 1 is a schematic diagram of an embodiment. FIG. 2 is a cross-sectional view of an embodiment with a ball gate package. Figure 3 is a schematic diagram of the circuit connection of the embodiment shown in Figure 2. Figure 4 is an embodiment with a metal plate. Figure 5 shows another embodiment with a metal plate. Figure 6 shows various embodiments of a conductive metal plate with a tripod. FIG. 7 is a packaging flowchart of the embodiment shown in FIG. 2. 2. Drawing number description: lr circuit end
五、發明說明（3) 407446 12鍍通孔 2 0堆疊式晶片 21第一晶片 2 2 第二晶片 2 3 導電樹脂 3 0 錄球 40凸塊· 5 0填充物 60引線 7 0 封裝層 80金屬板 81支撐柱 82 四隻腳架 8 3 兩邊支樓壁 84三邊支撐壁 85 四邊支撐壁 詳細說明： 本發明主要特點係在同一封裝内堆疊晶片，因而使電 路輸出端之數目增加，同時亦不佔有太大之面積，提高裝 置之功能。底下藉由一具有兩晶片堆疊的實施例來說明本 發明之技術内容。 請參閱第1圖所示，一基板1 0，其上承載一堆疊之二 晶片20，第一晶片21與基板1 0相焊接，而第二晶片22堆疊 黏接於上述之第一晶片21上，並以打線方式（w i r e bonding)將引線60自第二晶片22上連接至基板10。 如第2圖所示，在此具有球狀閘排封裝之電子裝置中V. Description of the invention (3) 407446 12 Plated through hole 2 0 Stacked wafer 21 First wafer 2 2 Second wafer 2 3 Conductive resin 3 0 Recording ball 40 bumps · 5 0 Filler 60 lead 7 0 Encapsulation layer 80 metal Board 81 support column 82 Four legs 8 3 Support walls on both sides 84 Support walls on three sides 85 Support walls on four sides Detailed description: The main feature of the present invention is to stack the chips in the same package, thus increasing the number of circuit output terminals. Do not occupy too much area, improve the function of the device. The technical content of the present invention will be described below with an embodiment having a two-chip stack. Please refer to FIG. 1, a substrate 10 carries a stack of two wafers 20 thereon, a first wafer 21 is soldered to the substrate 10, and a second wafer 22 is stacked and bonded to the first wafer 21 described above. The wires 60 are connected to the substrate 10 from the second chip 22 by wire bonding. As shown in Figure 2, in this electronic device with a ball-gate package
G:\PAT\專利\ 南茂 06.PTD 第6頁 407446 五、發明說明（4) ’基板1 0係一封裝之底材’其為印刷電路板，此基板〖〇下 方設有數個錫球30，而其上方承載堆疊式晶片2〇，第.一晶 片21藉由可導電之凸塊4〇與基板1〇相焊接在一起，形成電 性相接，且於基板1〇與第一晶片21之間，使其充滿一填充 物（under-f 1 1 1 )5〇，藉此保護凸塊4〇。將第二晶片μ利用 一導電樹脂23堆疊黏接於第一晶片21上，再利用打線法將 引線6 0連接第二晶片2 2與基板1 〇，使其形成電連接。最外 層的封裝層70 ’係使用模塑化合物，常用者為環氧樹脂， 經過注模成形’而包覆整個堆疊式晶片2 〇及引線6 〇，提供 機械性的保護作用。 上述之裝置所使用之基板係一印刷電路板，但熟知此 技藝者當知’本發明亦可適用於金屬基板及腳框（lead frame)型態的封裝。 第3圖顯示堆疊式晶片20與基板1〇之間的電路連接， 第一晶片2 1藉著凸塊4〇直接耦合電路到基板丨〇上的對應電 路端ιι(即焊接區），電路端n經鍍通孔（託&丨？1&)12連 接至基板10背面之電路端1厂（即焊球墊），因而與錫球3〇 電連接，另於第二晶片22上之電路’利用打線法形成引線 60 ’使其電連接於基板1 〇上之另—電路端i丨，因而使晶片 内的電路電連接至基板10下方之錫球3 0。 在此堆疊晶片之間更可以包含一導電物，例如塗佈導 電樹脂’或如第4圖所示，第一晶片21與第二晶片22之間 可以夾設一金屬板80，金屬板80之上、下以導電樹脂23與 第一晶片2 1、第二晶片2 2相黏接。此金屬板8 0除了可作為G: \ PAT \ patent \ Nanmao 06.PTD Page 6 407446 V. Description of the invention (4) 'Substrate 10 is a packaged substrate' It is a printed circuit board. There are several solder balls under this substrate 30, and the stacked wafer 20 is carried thereon. The first wafer 21 is soldered to the substrate 10 by the conductive bump 40, forming an electrical connection, and the substrate 10 and the first wafer are electrically connected. Between 21, it is filled with a filler (under-f 1 1 1) 50, thereby protecting the bump 40. The second chip μ is stacked and adhered to the first chip 21 with a conductive resin 23, and then the lead 60 is connected to the second chip 22 and the substrate 10 by a wire bonding method to form an electrical connection. The outermost encapsulation layer 70 'uses a molding compound, usually epoxy resin, and is injection molded' to cover the entire stacked wafer 20 and leads 60 to provide mechanical protection. The substrate used in the above device is a printed circuit board, but those skilled in the art should know that the present invention can also be applied to metal substrate and lead frame type packages. FIG. 3 shows the circuit connection between the stacked wafer 20 and the substrate 10. The first wafer 21 is directly coupled to the corresponding circuit terminal (that is, the solder zone) on the substrate via the bump 40, and the circuit terminal n through plated through holes (support & 丨? 1 &) 12 connected to the circuit end 1 factory (ie solder ball pad) on the back of the substrate 10, so it is electrically connected to the solder ball 30, and the circuit on the second chip 22 'The lead 60 is formed by a wire bonding method' to electrically connect to the other circuit end i 丨 on the substrate 10, so that the circuit in the wafer is electrically connected to the solder ball 30 below the substrate 10. A conductive object may be included between the stacked wafers, for example, coated with a conductive resin, or as shown in FIG. 4, a metal plate 80 may be sandwiched between the first wafer 21 and the second wafer 22. The first and second wafers 21 and 22 are adhered to each other with conductive resin 23 on the upper and lower sides. In addition to this metal plate 8 0 can be used as
G:\PAT\專利\南茂06.PTD % Ί % ~ ---- 407446 五、發明說明（5) 月史熱用之外，方將此金屬板80連接至同電源端（p〇wer source)或接地端（ground)，不但可以隔絕電磁干擾，也 可以隔絕訊號之間的交錯干擾。導電金屬板8 〇，除了可以 是一平板狀’也可以是具有各種型態腳架之設計，如第5 圖所示之導電金屬板8 〇具有支撐柱8丨，此支撐柱8 i可頂抵 基板1 0 ’這種設計可以保護第一晶片21，也便於第二晶片 22在打線時，不會影響到第一晶片21 ;同時，當第二晶片 22面積大於第一晶片2 1時，則第二晶片22在周邊打線時， 由於底部有一具支撐柱81之金屬板8〇支樓著，所以可以保 護第一晶片2 1。如第6圖之A-D圖所示，其為兩晶片之間的 金屬板不同的實施例，分別為具有四隻腳架82之金屬板8〇 、.具有兩邊支推壁83之金屬板80、具有三邊支擇壁84之金 屬板80以及具有四邊支撐壁85之金屬板8〇等。 第7圖提供一封裝流程之實施例，包括下列步驟： (1) 準備·一基板10; . (2) .將第一晶片21藉著導電凸塊4〇直接耦合至基板1〇上， 且於基板1 0與第一晶片之間，使其充滿一填充物5 〇 ; (3 )利用一導電樹脂2 3 ’將第二晶片2 2堆疊黏接在第一晶 片21上； (4) 於第二晶片22上之電路，以打線法將引線6〇耦合至基 板1 0上； (5) 注模成形，使一封裝層7〇於基板1〇上，包覆整個堆疊 之晶片20及引線6〇 ; (6 )在基板1 〇之底部形成數個錫球3 〇。G: \ PAT \ Patents \ Nanmao 06.PTD% Ί% ~ ---- 407446 V. Description of the invention (5) Except for thermal history, only connect this metal plate 80 to the same power terminal (p〇wer source) or ground (ground), not only can isolate electromagnetic interference, but also can isolate interleaving interference between signals. The conductive metal plate 8 〇, besides being a flat plate, can also be designed with various types of tripods. The conductive metal plate 8 shown in FIG. 5 has a support post 8 丨, and this support post 8 i can be topped. This design can protect the first wafer 21 and also facilitate the second wafer 22 to affect the first wafer 21 when wiring. At the same time, when the area of the second wafer 22 is larger than the first wafer 21, Then, when the second wafer 22 is wired around, the first wafer 21 can be protected because there is a metal plate 80 supporting the pillar 81 at the bottom. As shown in the AD diagram of FIG. 6, it is an embodiment in which the metal plates between the two wafers are different, which are metal plates 80 with four tripods 82, metal plates 80 with push walls 83 on both sides, A metal plate 80 having three-sided support walls 84 and a metal plate 80 having four-sided support walls 85 are provided. FIG. 7 provides an embodiment of a packaging process, including the following steps: (1) preparing a substrate 10;. (2). Directly coupling the first chip 21 to the substrate 10 through the conductive bump 40, and Between the substrate 10 and the first wafer, it is filled with a filler 50; (3) the second wafer 22 is stacked and bonded on the first wafer 21 with a conductive resin 2 3 '; (4) in The circuit on the second chip 22 couples the lead 60 to the substrate 10 by wire bonding; (5) injection molding, so that a packaging layer 70 covers the entire stacked chip 20 and the lead on the substrate 10 6〇; (6) Several solder balls 30 are formed on the bottom of the substrate 10.
407440 五、發明說明C6) 經過上述之步驟，便完成一個具有多晶片堆疊封裝之 裝置。 以上所述係藉由較佳實施例說明本發明之技術思想及 特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之 内容並據以實施，當不能以之限定本發明之專利範圍，即 大凡依本發明所揭示之精神所作之均等變化或修飾，仍應 涵蓋在本發明之專利範圍内。407440 V. Description of the invention C6) After the above steps, a device with a multi-chip stacked package is completed. The above is a description of the technical ideas and characteristics of the present invention by means of preferred embodiments. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. That is, all equal changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.
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