TW473967B - Ball grid array package device having chip size substrate and the packaging method thereof - Google Patents

Abstract

The present invention provides a ball grid array package device having chip size substrate and the packaging method thereof, wherein plural bonding pads are disposed on the first surface of chip; at least a metal pad is disposed on the second surface; a substrate is located on the first surface of the chip and the bonding pad is exposed; several solder balls are installed on both sides of the substrate, and several wires are used to connect the substrate and the bonding pad of the chip; an encapsulant wraps the bonding pad, substrate, wires and part of the solder balls on the chip, and makes most of the solder balls protrude from the encapsulant for use as the external connection point, so that the present invention has the characteristics of chip-size, good heat dissipation effect and reduced processing steps and time, etc.

Description

473967 V. Description of the invention α) · Field of the invention: The present invention relates to a ball grid array package (B a 1 1 G rid Array 'BGA), in particular to a chip size package (Chip) with a metal pad and a wafer size substrate Seal e / Size Package (CSP) completed ball grid array packaging device and manufacturing method thereof. Background of the Invention: Reducing package size has always been a goal pursued by semiconductor industry. Advances in miniaturization processes have led to breakthrough developments in semiconductor wafer size. Not only has wafer size been significantly reduced, but it has also provided more functions and effectively reduced manufacturing costs. However, due to the limitation of the external size of the traditional lead frame package, not only cannot provide high-performance chips (limited number of 1/0 pins), but also cannot reduce the SMT (Surface Mount Technology) assembly area. . The ball-thumb array package provides a multi-pin solution. Under the same mounting area, the BGA package can provide more pin counts; and in order to respond to the South ’s rush package, the development of lighter, thinner, shorter, Small electronic system products, chip size packaging (CSP) technology came into being, and combined with ball grid array packaging technology, to make ball grid array packaging devices with the same size and multi-pin characteristics . As shown in the first figure, the ball grid array package is provided with a slot i 2 in the center of a substrate i 0, and a wafer J 4 is adhered to the lower surface of the substrate, so that the central pad of the wafer 12 is free from The slot 丨 2 is exposed, and the lead 丨 6 is used to connect the upper surface of the substrate 丨 〇 The central pad of the wafer 丨 4, and the lead 丨 6 is easy to be damaged, so

Page 4 473967 V. Description of the invention (2) Before the ball, cover the lead 16 with a sealant 18 to protect it. Install two solder balls 2 0 on the two sides of the sealant 18 and on the surface of the substrate 10 Then, the whole wafer 1 4 is covered with "sealing glue 2 2". Because the above-mentioned systems are wired and sealed before soldering, it is easy to make the sealing 18 higher than the solder 20, which affects the electrical properties of the solder to other devices; and because the solder 20 must be located at the sealing 18 Both sides must be protected, and the lead 16 must be protected, so the area occupied by the sealant 18 is large, which causes the solder ball 20 to move outward. Therefore, the area of the substrate 10 is large, and the package size is determined by the substrate 10. The substrate 10 size is larger than the wafer 14 size, which makes it difficult to shrink the package size to a minimum. In addition, as the above ball grid array packaging method has undergone a second sealing and baking step, not only the process steps are more cumbersome and costly More processing time does not meet the needs of simple and fast. Therefore, the present invention proposes a ball grid array packaging device and a packaging method using a metal pad with a light, thin and short design criterion to meet the electrical requirements for high heat dissipation, in order to effectively solve the above-mentioned shortcomings. OBJECTS AND SUMMARY OF THE INVENTION: The main object of the present invention is to provide a gate array packaging device and a packaging method thereof using a metal pad to determine a package size, so as to surely reduce the package size to the smallest wafer-like size and make it have good heat dissipation. Effects and electrical properties. Another object of the present invention is to provide a ball grid array packaging method, so as to reduce the manufacturing steps and effectively reduce the manufacturing time, thereby increasing the throughput of manufacturing a packaging device.

473967 V. Description of the invention (3) Another object of the present invention is to use the mature processes and equipment on the existing packaging factory line to achieve the same benefits of increasing functions and reducing size. In order to achieve the above purpose, a ball grid array package includes a wafer having a first surface and a second surface, a plurality of pads are provided on the first surface, at least one metal pad is located on the second surface of the wafer, and a substrate is located on The first surface of the chip is exposed with solder pads. Several solder balls are mounted on the substrate, and the substrate is connected to the wafer pads with a number of leads. Another encapsulant covers the wafer pads, substrate, leads, and some solder balls. Make most of the solder balls protrude out of the encapsulant.

The detailed descriptions are provided below with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features and functions of the present invention. 0 Drawing number description:

10 Substrate 12 Slot 14 Chip 16 Lead 18 Sealant 20 Solder ball 22 Sealant 30 Chip 32 Solder pad 34 Metal pad 36 Substrate 38 Hollow area 40 Solder ball 42 Lead 44 Encapsulant 46 Substrate

The width of the package is less than 1.2 times the width of the die, or 1.4 times of its surface. Therefore, when it is mounted on other devices, the present invention is a package device that is a chip-size package, such as As shown in the second figure, a wafer 30 has two surfaces, a plurality of pads 32 are provided on the first surface of the wafer 30, and a metal pad 34 is provided on the second surface of the wafer 30. The substrate 36, in the substrate 36, the fifth, the description of the invention (4) detailed description: When the wafer size is less than the crystal grain area, a smaller space is occupied. A ball grid array has a first surface and a first aligned soldering surface. The central surface of the wafer 30 corresponds to the size of the board 36. The size is smaller than shown, so that the substrate 36 is out of the pads 3 2; The number is the same as that of the substrate 36 on the wafer 30 (the outermost compound of the seal), often injection molding or printing 32, the substrate 36, the induction effect, to avoid wafers or moisture, etc. The positions of the wafer 30 and the pad 32 are set or dedicated to the wafer 30 when the size of the wafer 30 is a solder ball 40 and the leads 42 are respectively located at the leads 42 passing through the hollow pad 32, so that the crystal The lead 42 used for mounting the gel 4 4 is made of epoxy resin (after the molding step, the covered wire 42 and 30 of the solder ball 40 and the lead 4 2 are subjected to the following: and most of the welding external points In order to provide electric solder balls 40 to form an electrical phase, there is a hollow region 38, and the base. Please refer to the third figure to expose the two sides of the surface of the substrate 36 through the hollow region 38; and then to the region 38 to connect the substrate 3 6 pieces of circuits in 30 are electrically connected to those who are often gold wires. Molding epo xy resin), covering the bottom part of the pad on the chip 30 to provide protection (for example, collision, dust, ball 40, protruding from the encapsulation gel 44 to be connected to other devices, and the effect is to achieve transfer Electricity

Page 7 473967 473967 Five properties are all in bulk Description of invention (5) The purpose of the signal. Among them, the size of the above-mentioned pad 40 is slightly completely covered with the wafer 30; in addition to the thermal effect, the size can be set. In other words, if the chip size is larger than the embodiment, the package size is small and the package size is improved. The above method is shown in the present invention. The packaging method has a first surface and a plurality of pads 3 2. A series of hollow pads 3 2 are provided on the wafer 30, and then the solder balls 40 are arranged neatly in the row. The empty area 3 8 is used to connect the die pads 32 or the bases on the die or print the base. Part of the solder ball 40 is convex to complete a ball grid array. In addition, the metal on the second surface of the wafer 30 of the present invention is larger than the size of the wafer 30, and the encapsulation device has a metal pad 34 with the size of the metal pad 34. To define it, in addition to the structure of the right metal die and the size of the shrinkable contact points shown in the second figure, the package of this figure includes the following steps and a surface, and the first surface of the wafer 30 is mounted with 3 8 so that The hollow wafer 30 first uses a wire substrate 36 and a crystal method to lead a board 36 and leads out of the packaging and bonding device. Except in the wafer metal pad size is the same to the wafer size, with characteristics. The flow chart of the invented packaging method device is as follows: First, a wire bonding method is provided in which a crystal is mounted on the first and second surfaces of the wafer 30 and a gold substrate 36 is aligned with the area 38 aligned with the two sides of the soldering surface. Make the lead 30 solder pad 3 2; the most encapsulated gel 44 covers 42 and the bottom body 44 of the solder ball 40 as the counter pad 3 4. The gold body 4 4 can simultaneously increase the overall package pad compared to the chip. The scale is even smaller than both at the same time. As shown in the fourth picture, as shown in the picture 30, the central part of the surface is provided with a pad 34, and the substrate 36 is & the pad 32 is exposed with a plurality of 4 non-lines. 4 2 After passing through, use the chip 30 and the end part, & external point, the first surface of 3 0 is provided with a plurality of 473967 in the center of the invention 5. Description of the invention (6) Welding pad 3 2 to correspond to the tool In addition to the embodiment of the substrate 36 of the hollow area 38, the regular pads 32 can be formed on the two opposite sides of the first surface of the wafer 30, as shown in the fifth and sixth figures. As shown, a metal pad 34 is located on the second surface of the wafer 30, and a substrate 46 is smaller than the size of the wafer 30, so that it is mounted on the first of the wafer 30 After the center of the surface, two pads 32 are exposed, and a plurality of solder balls 40 are provided in the center of the substrate 46, and a plurality of leads 42 are used to connect the substrate 46 to the pads 32 of the wafer 30. Finally, there is a packaging gel 44. Cover the bottom portion of the wafer 30 and the pads 32, the substrate 46, the leads 42 and the solder balls 40 on the chip 30, and make most of the solder balls 40 protrude out of the encapsulant 44 as external contact points; The size of the metal pad 34 can be larger than, equal to, or smaller than the size of the wafer 30. In addition, the above-mentioned solder pads 32 can be arranged around the first surface of the wafer 30 as shown in the seventh figure. The first intention is that the wafers 30, 32; at the 30th and the next, the encapsulation glue 4 2 and the solder body 4 8 are shown in the figure, and the first surface of the wafer 30 is two wafers 30. The first method of the present invention for making this packaging method is to mount a substrate wafer 30 on the center of the surface. The first wire 4 2 is connected to the body 44 and covers the small part of the ball 40. Therefore, in the present invention, a whole piece of The metal pad includes the following side or surrounding surface bonded with a metal 塾 46, and exposed a plurality of solder pads 30 pads on the pads. The array of packages is packaged on the first surface of the centrally mounted substrate 46 and the wafer. 3 0 and its portion, and make the complete ball grid regardless of the above directly bonded to the π township: after each set 3 4 out of the surrounding ball 40; 32; most 32, base & part of the device. t-placement ~ surface-placement process First, a plurality of pads are provided first, and then the pads 32 of the chip; and a wire is used, and then a board 4 is used. 6. The leads protrude from the encapsulation structure, which is attached. In addition,

Page 9 473967 V. Description of the invention (7) The metal pad can also be divided into more than two pieces. At least two pieces of metal pads are glued to the second surface of the wafer, which can reduce the occurrence of delamination. . Therefore, the wafer-size gate array packaging device and the packaging method of the present invention can effectively reduce the process steps and shorten the processing time, thereby increasing the yield of manufacturing packaging devices. In addition, the present invention uses a metal pad to determine the package size. In addition to reducing the package size to a chip-like size, the metal pad has a good heat dissipation effect through the role of the metal pad, and can use mature processes on existing packaging factory lines. The device and the device are used to complete the packaging of the present invention, so as to achieve the dual effects of increasing functions and reducing size. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the scope of the patent of the present invention cannot be limited, Any equal changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

Page 10 473967 Brief Description of Drawings Description of Drawings · The first drawing is a sectional view of the structure of a conventional ball grid array package. The second figure is a sectional view of the structure of the present invention. The third figure is a top view of the present invention. The fourth figure is a packaging method of the packaging device shown in the second figure. The fifth figure is a structural cross-sectional view of another embodiment of the present invention. The sixth figure is a top view of the fifth figure, wherein solder pads are provided on two sides of the wafer. The seventh figure is a top view of another embodiment of the fifth figure, wherein a plurality of pads are provided around the wafer.

The eighth figure is a packaging method of the packaging device shown in the fifth figure.

Page 11

Claims (1)

473967 6. Application patent scope 1. A ball grid array packaging device with a wafer size substrate, comprising: at least one wafer having a first surface and a second surface / a plurality of pads are provided in the center of the first surface; at least A metal pad is located on the second surface of the wafer; a substrate is located on the first surface of the wafer, and a hollow area is provided in the center of the substrate to expose the pad; a number of solder balls are mounted on the two sides of the substrate; Several leads, which are solder pads connecting the substrate and the wafer through the hollow area; and a packaging gel covering the solder pads on the wafer, the substrate, the leads, and a portion of the solder balls, and most of them The solder ball protrudes out of the encapsulant as an external point. 2. The ball grid array packaging device according to item 1 of the scope of patent application, wherein the size of the metal pad is greater than, equal to, or smaller than the size of the wafer. 3. The ball grid array packaging device described in item 1 of the scope of patent application, wherein the formation method of the packaging colloid is selected from one of injection molding and printing molding. 4. The ball grid array packaging device described in item 1 of the patent application scope, wherein the packaging gel covers the wafer more completely. 5. —A method for packaging a ball grid array with a wafer-size substrate, comprising the following steps: providing a wafer having a first surface and a second surface, wherein a plurality of pads are provided in the center of the first surface of the wafer; A metal puppet is glued to the second surface, Page 12 473967 VI. Application scope: A substrate is mounted on the first surface of the wafer, and a hollow area is provided in the center of the substrate to expose the solder pads; β A plurality of solder balls are installed on both sides of the first surface of the wafer; Wire bonding method allows the leads to pass through the hollow area to connect the substrate and the wafer pads, and uses a packaging gel to cover the pads on the wafer, the substrate, the leads and a portion of the solder balls, and makes most of the The solder balls protrude out of the encapsulant as an external point to form a wafer-size ball grid array package. 6. The ball grid array packaging method according to item 5 of the scope of patent application, wherein the size of the metal pad is greater than, equal to, or smaller than the size of the wafer. 7. The ball grid array packaging method according to item 5 of the scope of the patent application, wherein the formation method of the packaging colloid is selected from one of injection molding and printing molding. 8. The ball grid array packaging method as described in item 5 of the patent application scope, wherein the packaging gel more completely covers the wafer. 9. A ball grid array sealing device with a wafer-size substrate, comprising: at least one wafer having a first surface and a second surface, and a plurality of pads are provided on at least two sides of the first surface; A metal pad is located on the second surface of the wafer; a substrate is located at the center of the first surface of the wafer and the pad is exposed; a solder ball is installed at the center of the substrate; a lead is connected between the substrate and the substrate Solder pads of the wafer; and a packaging gel covering the solder pads on the wafer, the substrate, the leads, and a portion of the solder balls, and making most of the solder balls protrude out of the packaging glue as Page 13 473967 6. Scope of patent application A pair of external points. 10 The ball grid array packaging device according to item 9 of the scope of the patent application, wherein the bonding pad is further disposed around the first surface of the wafer. 〃 1 1 · The ball grid array packaging device described in item 9 of the scope of patent application, wherein the size of the metal pad is greater than, equal to, or smaller than the size of the wafer. /, 12 "The ball grid array packaging device described in item 9 of the scope of patent application, the formation method of the A package colloid is selected from one of injection molding and printing molding ° N 1 3. The ball grid array packaging device according to the item, and the packaging gel more completely covers the wafer. 〃 1 4. A method for packaging a ball grid array with a wafer-size substrate, including the following: providing a wafer having a first surface and a second surface, at least two sides of the first surface of the wafer being provided with a plurality of solder pads; One of the younger brothers of Xuanri film is bonded with a metal cymbal; a substrate is mounted on the center of the first surface of the wafer and the pad is exposed; a plurality of solder balls are mounted on the center of the first surface of the wafer; Lead wires connecting the substrate and the wafer pad; and using a packaging gel to cover the pad, the substrate, the leads and a portion of the solder ball on the wafer, and make most of the solder balls protrude out of the packaging gel As the external contact point, a wafer-size ball grid array packaging device is formed. 15 · The ball grid array sealing method according to item 4 of the patent application scope, wherein the pads are further arranged around the wafer. 16. The ball grid array packaging method described in item 4 of the patent application scope, which 473967 VI. In the scope of patent application, the size of the metal pad is greater than, equal to or smaller than the size of the wafer. 1 7. The ball grid array packaging method according to item 14 of the scope of the patent application, wherein the formation method of the packaging colloid is selected from one of injection molding and printing molding. 1 8. The ball grid array packaging method according to item 14 of the scope of patent application, wherein the encapsulation gel covers the wafer more completely. Page 15