1324029 » a 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種嵌埋半導體晶片之電路板結 構，尤指一種在電路板中嵌埋有半導體晶片之結構。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 — (Semiconductor device)已開發出不同的封裝型態，其主要 - 係在一封裝基板（package substrate)先接置一半導體晶 _片，再將該半導體晶片電性連接該封裝基板’並以膠體進 行封裝；其中球柵陣列式（Ball grid array, BGA)係為一種先 進的半導體封裝技術，其特點在於採用一封裝基板來安置 半導體晶片，旅於該封裝基板背面植設複數陣列排列之凸 塊（bump)，使相同單位面積之半導體晶片承载件上可以容 納更多輸入/輸出連接端（I/O connection)以符合高度集積 化（Integration)之半導體晶片所需，以藉由此些錫球將整個 |封裝單元焊結姐電性連接至外部裝置。 ' 惟傳統半導體封裝結構是將半導體晶片黏貼於基板 頂面，接著進行打線接合（wire bonding)或覆晶接合（Flip chip)封裝，再於基板之背面植以錫球以進行電性連接，如 此，雖可達到高腳數的目的，但是在更高頻使用時或高速 操作時，其將因導線連接路徑過長導致阻抗增加，使電氣 特性之效能無法提昇，而有所限制。 有鑑於此，為了能有效地提昇電性品質以符合下世代 產品之應用，業界紛紛研究採用將半導體晶片埋入電路板 5 19675 丄j乙碑 内作直接的電性連接，藉以縮短電性傳導路徑，並減少訊 號損失、訊號失真及提昇高速操作之能力。 白知肷埋半導體晶片之電路板之製法流程圖如第1A 至1D圖所不，首先提供一承載板10，該承載板10具有第 表面10a及與該第一表面相對之第二表面i〇b，且於該 承載板10中形成至少一貫穿該第一表自_及第二表面/ Ob+之開口 1 〇〇 (如第} A圖所示）；接著將一半導體晶片 ·=容置於該承载板1〇之開〇 1〇〇巾而該半導體晶片U 具有一主動面1U及與其相對應之非主動面m，且該主 動面11a具複數電極塾112，於該主動面⑴具有一純化 層113亚露出該電極墊112，又於該電極墊ιι2表面具有 孟屬墊114 (如第1B圖所示）；之後於該承載板之第— 表面1〇a及半導體晶片11之主動Φ 11a形成一介電層12, 且该介電層12具有複數開孔120以露出該半導體晶片u 之土屬墊丨14(如第ic圖所示）；最後於該介電層12之表 鲁面形成-線路層13，且在該介電層開孔12〇中形成有導電 結構131以電性連接該半導體晶片11之金屬墊m(如第 1D圖所示）。 ^ 依上習知述製程所製成之嵌埋半導體晶片之電路板 雖可縮短電性傳導路徑，並減少訊號損失、訊號失直及提 升在南頻運作之能力以克服習知半導體晶片接置於電路板 表面之種種缺失。 惟由於該半導體晶片n與介電層12之間的熱膨脹係 (E)差異大，έ亥半導體晶片約為3 ，而該介 19675 6 4 . 電層約為50 ppnLrC，使得兩材 作溫度下即產生高應力，而造成電子產品之操 分層的情、、兄. f.、成兩材料界面之疲勞破壞與 曰^ Γ ί n) ’進而影響電路板嵌埋半導體 日日片之口口質，甚至使得該電路板 使用。 4半V體曰日片失效而不堪 因此，如何提出一種嵌埋半導 以避免習知嵌埋半導體曰K电峪板、、、σ構’ 片鱼介電声電路板中，導致該半導體晶 片J電層之間的接合面產生分 r改進的問題。 柯貝匕成為亟需 【發明内容】 上述之缺失，本發明之目的即在提供埋半 導體晶片之電路核社椹 θ 從U里千 劾φ 4 進習知嵌埋半導體晶片之電 路板=半導體晶片與介電層之間的分層問題。 晶片之電路:ΐ:他：括本::係提供，埋半導體 及第 二表面，且该承载板具有至少-貫穿該第一 半導體曰片且亡 千¥紅日日片，係容置於該開口中，該 動面具複數電極墊，於兮主動面且j之非主動面，且該主 極墊，又料" 具有一純化層並露出該電 該半導體曰=亟藝表面具有金屬塾；緩衝層，係形成於 露出該金“之=表並包覆在該金屬墊周圍，僅 板之第一表面、半導電層，係形成於該承載 線路層’係形成於該介電層表面，且，η，以及 且°亥泉路層猎由形成於 19675 71324029 » a ninth invention: TECHNICAL FIELD The present invention relates to a circuit board structure in which a semiconductor wafer is embedded, and more particularly to a structure in which a semiconductor wafer is embedded in a circuit board. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, which are mainly used to connect a semiconductor wafer to a package substrate. The semiconductor wafer is electrically connected to the package substrate ′ and encapsulated by a colloid; wherein a ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized in that a package substrate is used to mount the semiconductor wafer. A plurality of bumps arranged in the array are mounted on the back surface of the package substrate, so that more I/O connections can be accommodated on the semiconductor wafer carrier of the same unit area to meet the high integration (Integration) The semiconductor wafer is required to electrically connect the entire | package unit to the external device by means of the solder balls. The conventional semiconductor package structure is to adhere the semiconductor wafer to the top surface of the substrate, followed by wire bonding or Flip chip packaging, and then solder balls on the back side of the substrate for electrical connection. Although it can achieve the goal of high number of feet, when it is used at a higher frequency or at a high speed, it will increase the impedance due to the long connection path of the wire, so that the performance of the electrical characteristics cannot be improved, and there is a limit. In view of this, in order to effectively improve the electrical quality to meet the application of the next generation of products, the industry has studied the use of semiconductor wafers buried in the circuit board 5 19675 乙j E-mail for direct electrical connection, thereby shortening the electrical conduction Path and reduce signal loss, signal distortion and the ability to improve high speed operation. The method of manufacturing the circuit board of the semiconductor chip is as shown in FIGS. 1A to 1D. First, a carrier 10 is provided. The carrier 10 has a first surface 10a and a second surface opposite to the first surface. And forming at least one opening 1 through the first table and the second surface / Ob + in the carrier 10 (as shown in FIG. A); then placing a semiconductor wafer The semiconductor wafer U has an active surface 1U and an inactive surface m corresponding thereto, and the active surface 11a has a plurality of electrodes 112, and the active surface (1) has a The purification layer 113 exposes the electrode pad 112, and has a Meng mat 114 on the surface of the electrode pad ι (as shown in FIG. 1B); then the first surface of the carrier plate 1a and the active Φ of the semiconductor wafer 11 11a forms a dielectric layer 12, and the dielectric layer 12 has a plurality of openings 120 to expose the semiconductor wafer 14 of the semiconductor wafer u (as shown in Figure ic); and finally the surface of the dielectric layer 12 Forming a circuit layer 13 and forming a conductive structure 131 in the dielectric layer opening 12 以 to electrically connect the Conductor wafer of the metal pads 11 m (as shown on FIG. 1D). ^ The circuit board embedded with the semiconductor chip fabricated according to the conventional process can shorten the electrical conduction path, reduce the signal loss, signal loss and enhance the ability to operate in the south frequency to overcome the conventional semiconductor chip placement circuit. Various missing surfaces of the board. However, since the thermal expansion coefficient (E) between the semiconductor wafer n and the dielectric layer 12 is large, the semiconductor wafer is about 3, and the dielectric layer is about 19 ppn LrC, so that the two materials are at a temperature. That is, the high stress is generated, and the stratification of the electronic product is caused, the brother f., the fatigue damage of the interface between the two materials and the 曰^ Γ ί ί ) ' ' 进而 进而 进而 进而 进而 进而 进而 进而 进而 进而 进而 进而 进而 进而 电路 电路 电路 电路 电路 电路 电路Quality, even making the board use. 4 half-V body 曰 失效 失效 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 嵌 嵌 嵌 嵌 嵌 嵌The joint between the J electrical layers creates a problem of improved r.柯贝匕 becomes a need for the above-mentioned invention. The purpose of the present invention is to provide a circuit for a buried semiconductor wafer. Layering problems with the dielectric layer. The circuit of the chip: ΐ: he: includes:: providing, burying the semiconductor and the second surface, and the carrier has at least - through the first semiconductor cymbal and dies, and the system is placed In the opening, the movable mask has a plurality of electrode pads on the active surface of the cymbal and the non-active surface of the j, and the main pad has a purification layer and exposes the semiconductor 曰=the surface of the enamel has a metal ruthenium; The buffer layer is formed on the surface of the dielectric layer by exposing the gold "the surface and covering the metal pad, and only the first surface of the plate and the semiconductive layer are formed on the carrier layer". And, η, and ° Haiquan Road layer hunting was formed in 19775 7
» I 1324029 該介電層中之導電結構以電性連接該金屬塾。 相較於習知技術，本發明之嵌埋半導體晶片之電路板 結構，係於半導體晶片之主動面及介電層間加入1衝 層，藉由該緩衝層以包覆該半導體晶片之金屬墊，且露出 4金屬墊之上表面，而可藉由該緩衝層以降低該介電層與 半導體晶片之間接合面的應力，以避免產生分層的 【實施方式】 'Φ 以下係藉由特定的具體實施例說明本發明之實施方 式，热悉此技蟄之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 [第一實施例] «月參閱第2 A至2G圖，係為本發明之嵌埋半導體晶片 之電路板結構之製法剖視流程圖。 如第2A圖所示，提供一承載板21，該承載板21具有 一第一表面21a及與其相對之第二表面21b，且該承载板 _21具有至少一貫穿該第一表面2la及第二表面21b之開口 210，而该承載板21係為絕緣板、金屬板或具有線路之電 路板。 如第2B圖所示’於該承載板21之第二表面21b形成 有一綠型膜22，以封住該承載板21之開口 21 〇的一端。 如第2C圖所示’接著於該承載板21之開口 210中接 置一半導體晶片23，該半導體晶片23具有—主動面23a 及與其相對之非主動面23b，且該主動面23a具複數電極 替231 ’方；δ亥主動面23a具有一純化層232並露出該電極 8 19675 ^24029 墊231’又於該電極墊231表面具有金屬墊233;又於該半 導體晶片23之主動面23a以網印或注入方式形成一缓衝層 24’且該緩衝層24並包覆該金屬墊233之周圍而露出該金 屬墊233之外表面，該緩衝層24係為低熱膨脹係數（例如 約3〜20Ppm/t：)或低楊氏係數（例如約i〜1〇〇〇Mpa) 之有機聚合物；其中該緩衝層24之熱膨脹係數最佳係可 Μ於半導體晶片23及介電層25之間。 春 如第2D圖所示，然後於該承載板21之第一表面2U、 半導體晶片23之金屬塾233及緩衝層24表面形成一介電 層25 ’其中該介電層25可視製程需要而不填入該承載板 21與半導體晶片23之間隙。 、該介電層25係可例如為環氧樹脂（Ep〇xy ^η)、聚乙 广月女（Polyimide)、氰脂（cyanate ester)、玻璃纖維⑷lass 如〇、雙順丁烯二酸醯亞胺/三氮解（bt， lazine)、ABF或混合環氧樹脂與玻璃纖維等材質所構成。 _如第2E圖所示’之後於該介電層25表面形成一線路 ^ H▲路層26可藉由形成於該介電層25中之導電 ，構加以電性連接該半導體晶片23之金屬塾加。 士。苐2F圖所示，復可於該介電層25及線路層^上 it路增層結構27 ’其中該線路增層結構27係包括介 置於該介電層上之線路層奶，以及形成於該 接該273 ’且該導電結構273可供電性連 電二接:並於該線路增層結構27表面形成有複數 α連接墊274,又於該線路增層結構27上覆蓋有一防焊 19675 9 以 4U29 層28,且該防焊層以具有複數個開孔28〇，俾以顯露線路 ^層結構27之電性連接墊274 ’該電性連接墊274若為焊 塾（Pad)則可供植置凸塊（bump)或接腳（pin) 〇 如第2G圖所示，移除該離型膜22，並於該承截 ?'口2丨〇與半導體晶片23之間的間隙中形成一：板為;1 月曰材料之黏著材料29 ,俾以將該半導體晶片Μ固定於哕 開口 210 中。 ' μ _ 由於该半導體晶片23與介電層25之間於製程中所產 生的熱應力與熱膨脹係數差異（CTE difference)和揚氏係 數（Y〇ung’sModulus)之乘積為正比，因此可藉由該緩衝 層24之低熱如脹係數或低楊氏係數之物性，以釋放半導體 B曰片23與介電層25之間熱膨脹係數差異所產生之應力， 以避免產生分層的情況’俾可提升該半導體晶片23嵌埋於 承載板21中之可靠度。 [弟一貫施例] 瞻租芩閱第3 A至3D圖，係為本發明之嵌埋半導體晶片 之電路板結構之製法剖視流程圖。 如第3A圖所示，提供一係如前一實施例所述之承載 板21、離型膜22及半導體晶片23,該承載板2〗具有至少 一貫穿該第一表面21a及第二表面21b之開口 21〇:並於 δ玄承載板21之第二表面21b形成有一離型膜22，以封住 該承載板21之開口 210的一端；又於該承載板21之開口 210中接置有一半導體晶片23,該半導體晶片23具有一主 動面23a及與其相對之非主動面23b，且該主動面23a具 19675 10 1324029 複數電極墊231，於該主動面23a具有一鈍化層232並露 出該電極墊231，又於該電極墊231表面具有金屬墊233， 於該半導體晶片23之鈍化層232表面形成有一缓衝層 24,且該緩衝層24包覆該金屬墊233之周圍而露出該金屬 墊233之外表面。 如第3B圖所示，然後於該承载板21之第一表 半導體晶片23之金屬墊233及緩衝層24表面形成一介電 層25 ’且該介電層25係填入該承载板2丨之開口 2丨〇與半 V體晶片23之間的間隙中，俾以將該半導體晶片23固定 於該開口 21 〇中。 如第3C圖所示，之後於該介電層25表面形成一線路 層26’且該線路層26可藉由形成於該介電層中之導電 結構261而電性連接該半導體晶片23之金屬墊]^。 、如第3D圖所示，復可於該介電層25及線路層％上 :成=路增層結構27，其中該線路增層結構η係包括至 ^電層271、豐置於該介電層上之線路層272，以及形 啻；、·χ ”電層中之導電結構273，且該導電結構可供 古”接该線路層26 ’並於該線路增層結構27表面形成 一Γ二電性連接墊274 ’又於該線路增層結構27上覆蓋有 以Γ:! 28 ’且該防焊層28表面具有複數個開孔“Ο,俾 顯路線路增層結構27之電性連接墊274。 半導本發明之嵌埋半導體W之電路板結構，係於 該之主動面形成有一緩衝層，藉由該緩衝層包覆 $肢日日片之金屬塾，而 J猎由该緩衝層以降低嵌埋於 19675 11 1324029 承載板内之半導體晶片與介電層之間的接合面於製程中所 產生的熱應力，以避免該接合面產生分層的現象。 上述實施例僅為例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及料下，對上述實_進行修飾 與變化。因此，本發明之權利保護範圍，應如後述之申請 專利範圍所列。 【圖式簡單說明】 第1A至1D圖係為習知嵌埋半導體晶片之製法流程 體晶片之電路板 體晶片之電路板 第2A至2G圖係為本發明之嵌埋半導 結構之第一實施製法流程圖；以及 第3 A至3D圖係為本發明之嵌埋半導 結構之第二實施製法流程圖。 【主要元件符號說明】 10、21 承載板 100 、 210 開口 10a、21a 弟一表面 10b 、 21b 弟二表面 11 ' 23 半導體晶片 112 、 231 電極塾 113 、 232 鈍化層 114 ' 233 金屬塾 274 電性連接墊» I 1324029 The conductive structure in the dielectric layer electrically connects the metal crucible. Compared with the prior art, the circuit board structure of the embedded semiconductor wafer of the present invention is characterized in that a buffer layer is added between the active surface and the dielectric layer of the semiconductor wafer, and the buffer layer is used to cover the metal pad of the semiconductor wafer. And exposing the upper surface of the 4 metal pad, and the buffer layer can be used to reduce the stress on the bonding surface between the dielectric layer and the semiconductor wafer to avoid delamination. [Embodiment] Φ is determined by a specific DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Other embodiments of the present invention will be readily appreciated by those skilled in the art from this disclosure. [First Embodiment] «Monthly Referring to Figures 2A to 2G, there is shown a flow chart of a circuit board structure for embedding a semiconductor wafer of the present invention. As shown in FIG. 2A, a carrier board 21 is provided. The carrier board 21 has a first surface 21a and a second surface 21b opposite thereto, and the carrier board _21 has at least one through the first surface 21a and the second The opening 210 of the surface 21b, and the carrier plate 21 is an insulating plate, a metal plate or a circuit board having a line. As shown in Fig. 2B, a green film 22 is formed on the second surface 21b of the carrier plate 21 to seal one end of the opening 21 of the carrier plate 21. As shown in FIG. 2C, a semiconductor wafer 23 is attached to the opening 210 of the carrier board 21. The semiconductor wafer 23 has an active surface 23a and an inactive surface 23b opposite thereto, and the active surface 23a has a plurality of electrodes. For the 231 ' square; the δ hai active surface 23a has a purification layer 232 and exposes the electrode 8 19675 ^ 24029. The pad 231 ′ further has a metal pad 233 on the surface of the electrode pad 231; and the active surface 23 a of the semiconductor wafer 23 Printing or injecting a buffer layer 24 ′ and covering the periphery of the metal pad 233 to expose the outer surface of the metal pad 233 . The buffer layer 24 has a low coefficient of thermal expansion (for example, about 3 to 20 Ppm). /t:) or an organic polymer having a low Young's modulus (for example, about i~1 〇〇〇Mpa); wherein the buffer layer 24 preferably has a coefficient of thermal expansion between the semiconductor wafer 23 and the dielectric layer 25. As shown in FIG. 2D, a dielectric layer 25 ′ is formed on the surface of the first surface 2U of the carrier 21, the metal germanium 233 of the semiconductor wafer 23, and the buffer layer 24, wherein the dielectric layer 25 is required for the process. The gap between the carrier plate 21 and the semiconductor wafer 23 is filled. The dielectric layer 25 can be, for example, an epoxy resin (Ep〇xy^η), a polyimide, a cyanate ester, a glass fiber (4) lass such as lanthanum, a bismuthaleate. Imine/trinitrogen solution (bt, lazine), ABF or mixed epoxy resin and glass fiber. Forming a line on the surface of the dielectric layer 25 as shown in FIG. 2E, the layer 26 can be electrically connected to the metal of the semiconductor wafer 23 by conduction formed in the dielectric layer 25.塾加. Shi. As shown in FIG. 2F, the dielectric layer 25 and the circuit layer are provided with an additional layer structure 27', wherein the line build-up structure 27 includes a circuit layer milk disposed on the dielectric layer, and is formed. And connecting the 273 ′ and the conductive structure 273 can be connected to the power supply: a plurality of α connection pads 274 are formed on the surface of the line build-up structure 27, and the line build-up structure 27 is covered with a solder resist 19675. 9 is a 4U29 layer 28, and the solder resist layer has a plurality of openings 28〇, to expose the electrical connection pad 274 of the circuit structure 27, and the electrical connection pad 274 is a pad (Pad). For the implantation of a bump or a pin, as shown in FIG. 2G, the release film 22 is removed, and in the gap between the receiving port and the semiconductor wafer 23 Forming one: the plate is; the adhesive material 29 of the January material is fixed to fix the semiconductor wafer defect in the opening 210. ' μ _ Since the thermal stress generated in the process between the semiconductor wafer 23 and the dielectric layer 25 is proportional to the product of the difference in thermal expansion coefficient (CTE difference) and the Young's modulus (Y〇ung's Modulus), The low heat of the buffer layer 24, such as the expansion coefficient or the low Young's modulus, to release the stress generated by the difference in thermal expansion coefficient between the semiconductor B and the dielectric layer 25 to avoid delamination. The reliability of embedding the semiconductor wafer 23 in the carrier 21 is improved. [Brief of the Example] The drawings of Figures 3A to 3D are a cross-sectional view of the manufacturing process of the circuit board structure of the embedded semiconductor wafer of the present invention. As shown in FIG. 3A, a carrier board 21, a release film 22, and a semiconductor wafer 23 according to the previous embodiment are provided. The carrier board 2 has at least one through the first surface 21a and the second surface 21b. Opening 21〇: a release film 22 is formed on the second surface 21b of the δ-shaped carrier plate 21 to seal one end of the opening 210 of the carrier plate 21; and another opening 210 is formed in the opening 210 of the carrier plate 21 a semiconductor wafer 23 having an active surface 23a and an inactive surface 23b opposite thereto, and the active surface 23a has a 19695 10 1324029 plurality of electrode pads 231 having a passivation layer 232 on the active surface 23a and exposing the electrode The pad 231 further has a metal pad 233 on the surface of the electrode pad 231, a buffer layer 24 is formed on the surface of the passivation layer 232 of the semiconductor wafer 23, and the buffer layer 24 covers the periphery of the metal pad 233 to expose the metal pad. 233 outside the surface. As shown in FIG. 3B, a dielectric layer 25' is then formed on the surface of the metal pad 233 and the buffer layer 24 of the first semiconductor wafer 23 of the carrier 21, and the dielectric layer 25 is filled into the carrier board 2 In the gap between the opening 2 丨〇 and the half V body wafer 23, the semiconductor wafer 23 is fixed in the opening 21 。. As shown in FIG. 3C, a wiring layer 26' is formed on the surface of the dielectric layer 25, and the wiring layer 26 can be electrically connected to the metal of the semiconductor wafer 23 by the conductive structure 261 formed in the dielectric layer. Pad]^. As shown in FIG. 3D, the dielectric layer 25 and the circuit layer % are integrated into a channel build-up structure 27, wherein the line build-up structure η includes a gate layer 271 and a drain layer. a circuit layer 272 on the electrical layer, and a conductive structure 273 in the electrical layer, and the conductive structure can be used to connect the circuit layer 26' and form a surface on the surface of the circuit build-up structure 27. The second electrical connection pad 274 ′ is further covered on the line build-up structure 27 with Γ:! 28 ′ and the surface of the solder resist layer 28 has a plurality of openings “Ο, the electrical properties of the 俾 俾 线路 线路 增 增 27 27 The connection pad 274. The semi-conductive circuit board structure of the embedded semiconductor W of the present invention is formed on the active surface to form a buffer layer, and the buffer layer is coated with the metal crucible of the limb day, and the The buffer layer reduces the thermal stress generated in the manufacturing process of the bonding surface between the semiconductor wafer and the dielectric layer embedded in the carrier board of the 19675 11 1324029 to avoid delamination of the bonding surface. The principles and effects of the invention are illustrated and not intended to limit the invention. Those skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described later. 1A to 1D are circuit boards of circuit board wafers of conventional process semiconductor wafers, and 2A to 2G are diagrams of the first embodiment of the buried semiconductor structure of the present invention; And the 3A to 3D drawings are the flow chart of the second implementation method of the embedded semi-conductive structure of the present invention. [Main component symbol description] 10, 21 carrier plate 100, 210 opening 10a, 21a, a face 10b, 21b Two surfaces 11 ' 23 semiconductor wafer 112 , 231 electrodes 塾 113 , 232 passivation layer 114 ' 233 metal 塾 274 electrical connection pads
19675 12 1324029 11a' 23a 主動面 lib 、 23b 非主動面 12 、 25 、 271 介電層 120 、 280 開孔 13 、 26 、 272 線路層 131 、 261 、 273 導電結構 22 離型膜 24 緩衝層 29 黏著材料 27 線路增層結構 28 防焊層 13 1967519675 12 1324029 11a' 23a active surface lib, 23b inactive surface 12, 25, 271 dielectric layer 120, 280 opening 13, 26, 272 circuit layer 131, 261, 273 conductive structure 22 release film 24 buffer layer 29 adhesion Material 27 line buildup structure 28 solder mask 13 19675