TW201405673A - Method of forming chip scale package - Google Patents

Abstract

The invention relates to a method of forming a chip-scale package, comprising providing a carrier board and forming a conductive bump adjacent to a die-mounting area defined on the carrier board; disposing the chip on the chip-mounting area of the carrier board; forming an encapsulant on the carrier board, the conductive bump and the chip to encapsulate the chip therein; removing parts of the encapsulant so that one end of the conductive bump is exposed therefrom; removing the carrier board to expose the encapsulant, the conductive bump and an active surface of the chip; forming a dielectric layer on the encapsulant, the conductive bump and the chip; forming a circuit layer on the dielectric layer and forming a conductive blind via in the dielectric layer; and forming a first insulating layer on the dielectric layer and the circuit layer wherein the insulating layer has a first opening formed therein, thereby reducing manufacturing processes, throughput time and costs as a result.

Description

Wafer size package manufacturing method

The present invention relates to a method of fabricating a package, and more particularly to a method of fabricating a chip size package.

With the evolution of semiconductor technology, semiconductor products have developed various packaging technologies, and in order to make semiconductor packages thinner and lighter, a technology of chip scale package (CSP) has been developed, which is characterized by The wafer size package only has dimensions that are similar or slightly larger than the wafer size.

U.S. Patent Nos. 5,892,179, 6,103, 552, 6, 287, 893, 6,350, 668, and 6, 433, 427 disclose a conventional CSP structure which forms a line buildup directly on a wafer without the use of a wafer carrier such as a substrate or lead frame, and utilizes a line weight. The technology of the redistribution layer (RDL) redistributes the electrode pads on the wafer to the desired location.

However, the above-mentioned CSP structure has the disadvantage that the application of the technology of the circuit redistribution layer or the conductive traces disposed on the wafer are often limited by the size of the wafer or the area of the active surface thereof, especially when the wafer is accumulated and the wafer is increased. With ever-decreasing dimensions, the wafer does not even provide enough surface to provide a greater number of solder balls for electrical connection to the outside world.

In view of the above, U.S. Patent No. 6,271,469 and U.S. Patent Nos. 1A to 1C disclose a cross-sectional view of a wafer level wafer package (Wafer Level CSP, WLCSP), which is provided with a wiring layer formed on a wafer. A more adequate surface area to accommodate more input/output or solder balls.

As shown in FIG. 1A, a film 11 is prepared, and the plurality of wafers 12 are adhered to the film 11 by the active surface 121, which is, for example, a heat-sensitive adhesive film.

As shown in FIG. 1B, a packaging molding process is performed, that is, the non-active surface 122 and the side surface of the wafer 12 are covered with an encapsulant 13 such as an epoxy resin, and the adhesive film 11 is removed by heating, and exposed. The wafer action surface 121.

As shown in FIG. 1C, a dielectric layer 14 is then applied to the active surface 121 of the wafer 12 and the surface of the encapsulant 13 by a line redistribution layer (RDL) technique, and a plurality of openings through the dielectric layer 14 are opened to expose An electrode pad 120 on the wafer, a wiring layer 15 is formed on the dielectric layer 14, and the circuit layer 15 is electrically connected to the electrode pad 120. Then, an insulating protection layer 16 is disposed on the circuit layer 15, and is exposed. A portion of the wiring layer 15 is implanted with solder balls 17, and then a cutting operation is performed.

Through the above process, since the surface of the encapsulant 13 covering the wafer 12 can provide a surface area larger than the surface 121 of the wafer 12, a large number of solder balls 17 can be provided to effectively achieve electrical connection with the outside.

However, the disadvantage of the above-mentioned process is that the wafer 12 is adhered to the film 11 by the active surface 121, and the film 11 is often subjected to heat expansion during the process to cause expansion and contraction, thereby causing adhesion to the glue. The position of the wafer 12 on the film 11 is shifted, even when the package is molded, the wafer 12 is displaced due to thermal softening of the film 11, resulting in subsequent line re-layering. During the process, the circuit layer 15 cannot be effectively connected to the electrode pads 120 of the wafer 12, thereby causing poor electrical connection.

In addition, referring to FIG. 2, in the above-mentioned wafer-level wafer-size package, in the package molding, the film 11' may be softened by heat, so that the encapsulant 13 overflows to the active surface of the wafer 12. 121, or even contaminating the electrode pad 120, causing poor contact between the circuit layer of the subsequent circuit redistribution layer and the electrode pads of the wafer, resulting in waste problems.

In addition, referring to FIG. 3A, the wafer level wafer package package supports the wafer 12 only through the film 11 during the package molding process, so the film 11 and the package body 13 are prone to severe warpage 110. The problem, especially when the thickness of the encapsulant 13 is very thin, the warpage problem will be more serious, which leads to the subsequent application of the circuit re-layering process, the dielectric layer 14 coated on the wafer 12 will be The thickness is not uniform; thus, a hard carrier 18 (as shown in FIG. 3B) is additionally provided to fix the encapsulant 13 to the rigid carrier 18 through a glue 19 for leveling. However, when the process of the circuit redistribution layer is completed and the carrier 18 is removed, the adhesive 190 is easily left on the encapsulant 13 (as shown in FIG. 3C). Other related prior art disclosures are shown in U.S. Patent Nos. 6,498,387, 6,586,822, 7, 019, 406, and 7, 238, 602.

Furthermore, as shown in FIG. 3D, if the package is to be stacked, the package body 13 is first penetrated, and a through-hole process (Through Mold Via, TMV) is performed to form a plurality of through-passes. a hole, which is then filled with a conductive material 100 in the via hole by an electroplating or plating process, and a plurality of conductive vias 10 are formed, and then formed on the conductive vias 10 The solder ball 17' is for attaching the electronic device 1 such as another package. However, the process of penetrating the encapsulant 13 is difficult, and the conductive material 100 needs to be filled when the conductive via 10 is formed, so that the process time is increased and the cost is increased.

Therefore, how to provide a method for manufacturing a chip size package can avoid the lack of the prior art, thereby ensuring the electrical connection quality between the circuit layer and the electrode pad, improving the reliability of the product, and reducing the process cost, which is an important Question.

The invention provides a method for manufacturing a wafer size package, comprising: providing a carrier board, and providing adjacent conductive bumps and a crystallizing area on the carrier board; and disposing the wafer on the crystallizing area of the carrier board; The wafer has a plurality of active and non-active surfaces, and the active surface has a plurality of electrode pads, and is disposed on the carrier plate with the active surface; forming an encapsulant on the carrier, the conductive bumps and the wafer, Coating the wafer, and the encapsulant has a first surface bonded to the carrier plate and a second surface opposite to the first surface; a portion of the encapsulant is removed from the second surface of the encapsulant to make the conductive One end of the bump is exposed on the second surface of the encapsulant; the carrier is removed to expose the first surface of the encapsulant, the conductive bump and the active surface of the wafer; and a dielectric layer is formed on the encapsulant a first surface, the conductive bump and the active surface of the wafer; forming a wiring layer on the dielectric layer, and forming a conductive blind via in the dielectric layer to allow the wiring layer to pass through the conductive blind via Connecting the electrode pad The conductive bumps; and forming a first insulating protective layer on the dielectric layer and the circuit layer, and the insulating protective layer having a first opening, in order to make portions of the first wiring layer exposed from the opening.

As can be seen from the above, the method for manufacturing the wafer-sized package of the present invention is to directly connect the stacked electronic devices by using the conductive bumps, without the filling step of the through-hole and the conductive material of the encapsulant to form the conductive via, which is simplified. Process to reduce process time and reduce costs. Furthermore, the present invention uses a carrier plate instead of the conventional film, thereby effectively avoiding problems such as encapsulation gel overflow and wafer contamination caused by thermal deformation of the film.

Moreover, in the present invention, since the wafer is disposed on the carrier board, the carrier board does not have the problem of expansion or softening of the film according to the prior art due to heat, and the support of the overall structure is increased by the conductive bumps on the carrier board. The force is prevented from warping, so that the wafer does not shift or displace, so that the electrode layer of the circuit layer and the wafer can be effectively aligned during the process of performing the circuit redistribution layer, thereby ensuring the quality of the electrical connection and effectively The problem of waste is avoided; and the present invention does not need to be fixed to a carrier by a glue as it is, so that no glue remains on the encapsulant.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. Technology disclosed by the invention The content can be covered. In the meantime, the terms "upper", "outermost", "smooth" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

4A to 4H are cross-sectional views showing the method of fabricating the wafer-sized package of the present invention.

As shown in FIG. 4A, a carrier 20 is provided, and the adjacent plurality of conductive bumps 200 and a crystallized area A are disposed on the carrier 20, and the carrier 20 is formed of a copper material. The carrier plate 20 and the conductive bumps 200 can be integrally formed or separately formed.

Alternatively, as shown in FIG. 4A', one end of the conductive bump 200 has a metal layer 20a, and the material forming the metal layer 20a is one of a group of nickel, palladium, and gold or a laminated structure. . However, the following description will be made by way of example only in FIG. 4A.

As shown in FIG. 4B, a wafer 22 is disposed on the crystallized area A of the carrier 20, the wafer 22 has an opposite active surface 22a and an inactive surface 22b, and the active surface 22a has a plurality of electrode pads 220 thereon. And the action surface 22a is attached to the carrier plate 20. In this embodiment, the adhesive layer 21 is applied to the active surface 22a for the purpose of bonding and fixing the wafer 22 to the carrier 20, but is not limited thereto.

As shown in FIG. 4C, an encapsulant 23 is formed on the carrier 20, the conductive bump 200, and the wafer 22 to cover the wafer 22. The encapsulant 23 has a bond to the carrier 20 a surface 23a and phase The second surface 23b of the first surface 23a. In this embodiment, the encapsulant 23 covers the non-active surface 22b of the wafer 22, and the distance h between one end of the conductive bump 200 and the second surface 23b of the encapsulant 23 is 10 to 50 μm, but Not limited to this range.

As shown in FIG. 4D, a portion of the encapsulant 23 is removed from the second surface 23b of the encapsulant 23 so that one end of the conductive bump 200 is exposed on the second surface 23b of the encapsulant 23, in detail The encapsulant 23 is partially removed by grinding to make one end of the conductive bump 200 flush with the second surface 23b of the encapsulant 23.

Alternatively, as shown in FIG. 4D', a package colloid opening 230 corresponding to the exposed conductive bump 200 is formed by laser burning on the second surface 23b of the encapsulant 23. However, only the 4D figure will be exemplified below.

As shown in FIG. 4E, the carrier 20 is removed by etching to expose the first surface 23a of the encapsulant 23 and the conductive bump 200, and the adhesive layer 21 is removed by a chemical solution to expose the wafer 22. The action surface 22a.

When the carrier 20 is removed, the present invention does not leave a metal material or adhesive on the first surface 23a of the encapsulant 23.

As shown in FIG. 4F, the process of performing a circuit redistribution layer (RDL) is performed by forming at least one dielectric layer 24 on the first surface 23a of the encapsulant 23, the conductive bump 200, and the active surface of the wafer 22. 22a; then, forming a plurality of blind vias 240 in the dielectric layer 24, exposing the conductive bumps 200 and the electrode pads 220, and then performing a patterning step to form the conductive vias 250 in the blind vias 240, and Forming a circuit layer 25 on the conductive via 250 and the dielectric layer 24 to allow the circuit layer 25 to pass through the conductive via 250 The electrode pad 220 and the conductive bump 200 are electrically connected.

As shown in FIG. 4G, a first insulating protective layer 26a is formed on the dielectric layer 24 and the wiring layer 25, and the first insulating protective layer 26a has a plurality of first openings 260a to expose a portion of the wiring layer 25. The first opening 260a is provided in a subsequent process to form a first conductive element 27 such as a solder ball on the circuit layer 25 in the first opening 260a, and is connected to other electronic devices, such as a circuit board. a semiconductor wafer or package; further, a second insulating protective layer 26b is formed on the second surface 23b of the encapsulant 23 and the conductive bump 200, and the second insulating protective layer 26b has a plurality of second openings 260b to A portion of the conductive bump 200 is exposed to the second opening 260b.

Alternatively, as shown in FIG. 4G', the build-up structure 25' may be formed on the dielectric layer 24 and the circuit layer 25, and the first insulating protective layer 26a may be disposed at the most of the build-up structure 25'. The outer layer is exposed to the first opening 260a, and the first conductive member 27 is formed on the line in the first opening 260a. Further, the build-up structure 25' has at least one dielectric layer, a line disposed on the dielectric layer, and a conductive via hole disposed in the dielectric layer and electrically connecting the circuit layer 25 and the line. In other embodiments, another build-up structure (not shown) may be formed on the second surface 23b of the encapsulant 23. However, the following description will be made only by the 4G diagram.

As shown in FIG. 4H, a second conductive element 28, such as a solder ball, is formed on the conductive bump 200 in the second opening 260b for external connection with other electronic devices 29, such as a circuit board or another package.

The processes shown in Figures 5A through 5C provide a process for forming the carrier 20 and the conductive bumps 200 as shown in Figure 4A.

As shown in FIG. 5A, a substrate 30 is provided, and a resist layer 31 is formed on the substrate 30. The resist layer 31 has a plurality of openings 310, and a portion of the surface of the substrate 30 is exposed.

As shown in FIG. 5B, a portion of the substrate 30 in the opening 310 is etched away to form the conductive bump 200 under the resist layer 31.

As shown in FIG. 5C, the resist layer 31 is removed, and the remaining substrate 30 material is used as the carrier board 20.

The processes shown in Figs. 5A' to 5C' provide a process for forming the carrier 20, the conductive bumps 200, and the metal layer 20a as shown in Fig. 4A'.

As shown in FIG. 5A', a substrate 30 is provided, and a resist layer 31 is formed on the substrate 30, and the resist layer 31 has a plurality of openings 310 exposing a portion of the surface of the substrate 30.

As shown in Fig. 5B', the metal layer 20a is formed on the substrate 30 in the opening 310.

As shown in FIG. 5C', the resist layer 31 and a portion of the substrate 30 under it are removed to form the conductive bump 200 under the metal layer 20a, and the remaining substrate 30 is used as the carrier 20.

In summary, the method for manufacturing the wafer-sized package of the present invention is to directly connect the stacked electronic devices by using the conductive bumps, without the filling step of the through-hole and the conductive material of the encapsulant to form the conductive vias. Simplify the process to reduce process time and reduce costs. Furthermore, the present invention uses a carrier plate instead of the conventional film, thereby effectively avoiding problems such as encapsulation gel overflow and wafer contamination caused by thermal deformation of the film.

Moreover, the present invention does not rely on the placement of a wafer on the carrier board. If the film of the prior art is stretched or softened due to heat, and the supporting force of the overall structure is increased by the conductive bumps on the carrier plate to avoid warping of the structure, the wafer does not shift or Displacement, so that the circuit layer and the electrode pad of the wafer can be effectively aligned when the process of the circuit redistribution layer is performed, the electrical connection quality is ensured, and the waste problem is effectively avoided; and the present invention does not need to be fixed to the adhesive as is conventionally A carrier, so there is no glue left on the encapsulant.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1, 29‧‧‧ electronic devices

10‧‧‧ Conductive through hole

100‧‧‧Electrical materials

11, 11'‧‧ ‧ film

110‧‧‧ warpage

12, 22‧‧‧ wafer

120, 220‧‧‧electrode pads

121, 22a‧‧‧ action surface

122, 22b‧‧‧ non-active surface

13‧‧‧Package colloid

130‧‧‧Overflow

14, 24‧‧‧ dielectric layer

15, 25‧‧‧ circuit layer

16‧‧‧Insulation protection layer

17, 17'‧‧‧ solder balls

18‧‧‧ Vehicles

19‧‧‧Viscos

190‧‧‧Residual adhesive

20‧‧‧Loading board

20a‧‧‧metal layer

200, 200'‧‧‧ conductive bumps

21‧‧‧Adhesive layer

23, 23'‧‧‧Package colloid

23a‧‧‧ first surface

23b, 23b’‧‧‧ second surface

230‧‧‧Package colloid opening

240‧‧‧Blind hole

25’‧‧‧Additional structure

250‧‧‧conductive blind holes

26a‧‧‧First insulation protection layer

26b‧‧‧Second insulation protection layer

260a‧‧‧first opening

260b‧‧‧Second opening

27‧‧‧First conductive element

28‧‧‧Second conductive element

30‧‧‧Substrate

31‧‧‧Resist layer

310‧‧‧ openings

A‧‧‧ crystal zone

H‧‧‧distance

1A to 1C are cross-sectional views of a method of fabricating a wafer level wafer size package as disclosed in U.S. Patent No. 6,271,469, the disclosure of which is incorporated herein by reference. A cross-sectional view of the problem; FIGS. 3A to 3D are cross-sectional views of the wafer-level wafer-size package disclosed in U.S. Patent No. 6,271,469, which has the problems of encapsulation warpage, additional carriers, residual adhesive on the surface of the encapsulant, and difficulty in stacking; 4A to 4H are diagrams showing a wafer size package of the present invention and a method for fabricating the same, wherein the 4A', 4D' and 4G' diagrams are another embodiment of the 4A, 4D and 4G diagrams, respectively. The figures shown in Figures 5A to 5C are the carrier plates and guides shown in Figure 4A. A cross-sectional view of the process of the electric bumps; and a cross-sectional view of the process of the carrier plate, the conductive bumps, and the metal layer shown in Fig. 4A' shown in Figs. 5A' to 5C'.

200‧‧‧conductive bumps

22‧‧‧ wafer

22a‧‧‧Action surface

22b‧‧‧Non-active surface

220‧‧‧electrode pad

23‧‧‧Package colloid

23a‧‧‧ first surface

23b‧‧‧ second surface

24‧‧‧ dielectric layer

240‧‧‧Blind hole

25‧‧‧Line layer

250‧‧‧conductive blind holes

26a‧‧‧First insulation protection layer

26b‧‧‧Second insulation protection layer

260a‧‧‧first opening

260b‧‧‧Second opening

27‧‧‧First conductive element

Claims (15)

A method for manufacturing a wafer-sized package includes: providing a carrier plate, and providing adjacent conductive bumps and a crystallizing region on the carrier plate; and disposing a wafer on the crystallographic region of the carrier plate, the wafer having The active surface and the non-active surface, and the active surface has a plurality of electrode pads, and the active surface is attached to the carrier plate; forming an encapsulant on the carrier plate, the conductive bumps and the wafer to cover the surface a chip, and the encapsulant has a first surface bonded to the carrier plate and a second surface opposite to the first surface; a portion of the encapsulant is removed from the second surface of the encapsulant to cause the conductive bump One end is exposed on the second surface of the encapsulant; the carrier is removed to expose the first surface of the encapsulant, the conductive bump and the active surface of the wafer; and a dielectric layer is formed on the first surface of the encapsulant a conductive bump and a working surface of the wafer; forming a wiring layer on the dielectric layer, and forming a conductive blind via in the dielectric layer, so that the wiring layer is electrically connected to the electrode through the conductive blind via Pad and the conductive bump ; And forming a first insulating protective layer on the dielectric layer and the circuit layer, and the insulating protective layer having a first opening, in order to make portions of the first wiring layer exposed from the opening. The manufacture of the wafer size package as described in claim 1 The method includes forming a first conductive element on the circuit layer in the first opening. The method for fabricating a chip-size package according to claim 1, further comprising forming a build-up structure on the dielectric layer and the circuit layer, and the first insulating protective layer is disposed at the most of the build-up structure On the outer layer. The method of fabricating a wafer-size package according to claim 1, wherein removing the portion of the encapsulant system comprises removing a portion of the thickness of the encapsulant such that one end of the conductive bump and the second portion of the encapsulant The surface is flush. The method of fabricating a wafer-size package according to claim 4, wherein the part of the thickness of the encapsulant is removed by grinding. The method of fabricating a wafer-size package according to claim 1, wherein the removing part of the encapsulant system comprises forming an encapsulation opening corresponding to the exposed conductive bump on the second surface of the encapsulant. The method of fabricating a wafer-size package according to claim 6, wherein the method of forming the encapsulation opening is laser cauterization. The method of fabricating a wafer-size package according to claim 1, further comprising exposing the conductive bump to one end of the second surface to form a second conductive element. The method for manufacturing a wafer-size package according to claim 1, further comprising forming a second insulating protective layer on the second surface of the encapsulant and the conductive bump, and the second insulating protective layer has a second opening a hole for exposing a portion of the conductive bump to the second opening. The method of claim 1 , wherein one end of the conductive bump has a metal layer, and the metal layer is exposed on the second surface of the encapsulant. The method for manufacturing a wafer-size package according to claim 1, wherein the step of forming the carrier plate and the conductive bump comprises: providing a substrate; forming a resist layer on the substrate, and the resist layer has a plurality of layers Opening, exposing a portion of the surface of the substrate; removing a portion of the substrate material in the opening; and removing the resist layer. The method of manufacturing a wafer-size package according to claim 10, wherein the process of forming the carrier, the conductive bump and the metal layer comprises: providing a substrate; forming a resist layer on the substrate, and the resistor The layer has a plurality of openings exposing a portion of the surface of the substrate; forming the metal layer on the substrate in the opening; and removing the resist layer and a portion of the substrate material therebelow. The method of fabricating a wafer-sized package according to claim 1, wherein the method of removing the carrier is etched. The method for manufacturing a wafer-size package according to claim 1, further comprising applying an adhesive layer on the active surface of the wafer, so that the wafer is placed on the crystallographic region of the carrier, and is moved. Except the carrier board After that, the adhesive layer is removed. The method of fabricating a wafer-size package according to claim 1, wherein the material of the carrier plate is made of copper.