CN104851868B - Packaging system and preparation method thereof - Google Patents
Packaging system and preparation method thereof Download PDFInfo
- Publication number
- CN104851868B CN104851868B CN201410051473.4A CN201410051473A CN104851868B CN 104851868 B CN104851868 B CN 104851868B CN 201410051473 A CN201410051473 A CN 201410051473A CN 104851868 B CN104851868 B CN 104851868B
- Authority
- CN
- China
- Prior art keywords
- layer
- conductor layer
- conductor
- guide pillar
- covering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
A kind of packaging system, it includes a conductor layer No.1, a metal level, one first dielectric layer, one second conductor layer, guide pillar layer, a passive device, one first adhesive layer, privates layer and a welding resisting layer.Conductor layer No.1 has a relative first surface and a second surface.Metal level is arranged on the first surface of conductor layer No.1.First dielectric layer be arranged on conductor layer No.1 with the subregion of conductor layer No.1.Second conductor layer is arranged on conductor layer No.1 and the first dielectric layer.Guide pillar layer is arranged on the second conductor layer, and forms a concave structure with the second conductor layer.Passive device is set and electrical ties are on the second conductor layer in concave structure.First adhesive layer is arranged in the subregion of the second conductor layer and guide pillar layer, and coats passive device, wherein the first adhesive layer is not exposed to one end of guide pillar layer.Privates layer is arranged on one end of the first adhesive layer and guide pillar layer.Welding resisting layer is arranged on the first adhesive layer and privates layer.
Description
Technical field
The invention relates to a kind of packaging system and preparation method thereof, in particular to a kind of semiconductor encapsulation device
And preparation method thereof.
Background technology
In the electronic product of a new generation, constantly pursue more compact, more require that product has multi-functional and high-performance,
Therefore, integrated circuit (Integrated Circuit, IC) must accommodate more electronic components to reach in limited region
High density and the requirement of miniaturization, are that this electronic industry develops new structure dress technology, electronic component are embedded in substrate, significantly contracted
Small packaging housing product, also shortens the access path of electronic component and substrate, in addition also using increasing layer technology (Build-Up) increase
Layout area, to meet compact and multi-functional trend trend.
Fig. 1 is traditional glass fibre basal plate encapsulating structure.Glass fibre basal plate encapsulating structure 10 includes glass fibre
Substrate 100, for example, can be glass epoxy resin copper clad laminate FR-4 models or FR-5 models, and wherein glass fibre basal plate 100 is passed through
Groove 110 and multiple via holes 120 are formed by laser beam drilling (Laser Via), electronic component 130 is fixed in groove 110,
Metallic conduction post 140 is arranged in the via hole 120 of part, and the first metal conducting layer 142,144 is separately positioned on glass fibre
Conducted on substrate 100 and with metallic conduction post 140, the covering of insulating barrier 150 groove 110, electronic component 130 and multiple via holes
120, the second metal conducting layer 146,148 be arranged on the upper of insulating barrier 150 and with the metal conducting layer of electronic component 130 and first
142nd, 144 conduct.
However, above-mentioned traditional glass fibre basal plate encapsulating structure, its be use glass fibre material as substrate into
This is prohibitively expensive, and recycles laser beam drilling technology again to form the laminated construction of four layers of blind buried via hole of metal level laser, its
In, multiple laser beam drilling process time is longer and complex manufacturing process, and the cost of four layers of metal level is also higher, can all cause tradition
Glass fibre basal plate encapsulating structure do not have industrial advantage.
The content of the invention
The present invention proposes a kind of packaging system, and adhesive layer (Mold Compound Layer) can be used to be coreless base for it
The material of main part of plate (Coreless Substrate), and form via hole and pre- package interconnection system using guide pillar layer is electroplated
(Mold Interconnect System, MIS) packaged type is taken advantage of a situation in substrate manufacture and passive device is embedded in substrate,
Form the laminated construction that passive device is buried in simple three-layer metal layer.
The present invention proposes a kind of preparation method of packaging system, and the sealing (Mold of lower cost can be used in it
Compound expensive glass fibre basal plate) is replaced, and three-layer metal layer plating guide pillar laminar flow journey substitution at lower cost is high
The expensive blind buried via hole flow of four layers of metal level laser, so process time is shorter and flow is simple.
In the first embodiment, the present invention proposes a kind of packaging system, and it includes a conductor layer No.1, a metal level, one
First dielectric layer, one second conductor layer, guide pillar layer, a passive device, one first adhesive layer, privates layer and one are anti-
Layer.Conductor layer No.1 has a relative first surface and a second surface.Metal level is arranged at the first of conductor layer No.1
On surface.First dielectric layer be arranged on conductor layer No.1 with the subregion of conductor layer No.1, wherein the first dielectric layer is not
It is exposed to the first surface of conductor layer No.1.Second conductor layer is arranged on conductor layer No.1 and the first dielectric layer.Guide pillar layer is set
It is placed on the second conductor layer, and a concave structure is formed with the second conductor layer.Passive device is set and electrical ties are in matrix knot
On the second conductor layer in structure.First adhesive layer is arranged in the subregion of the second conductor layer and guide pillar layer, and coats quilt
Dynamic element, wherein the first adhesive layer is not exposed to one end of guide pillar layer.Privates layer is arranged at the first adhesive layer and guide pillar layer
One end on.Welding resisting layer is arranged on the first adhesive layer and privates layer.
In the first embodiment, the present invention proposes a kind of preparation method of packaging system, and its step includes：One metal is provided
Support plate, it has a relative first side and a second side；A conductor layer No.1 is formed in the second side of metal support plate
On；One first dielectric layer is formed in the second side and conductor layer No.1 of metal support plate；One second conductor layer is formed in first
On conductor layer and the first dielectric layer；Guide pillar layer is formed on the second conductor layer, wherein guide pillar layer forms one with the second conductor layer
Concave structure；The setting of one passive device is provided and electrical ties are on the second conductor layer in concave structure；Form one first sealing
The first dielectric layer of layer cladding, the second conductor layer, passive device, the second side of guide pillar layer and metal support plate；Expose guide pillar layer
One end；Privates layer is formed on one end of the first adhesive layer and the guide pillar exposed layer；A welding resisting layer is formed in the first envelope
On glue-line and privates layer；The subregion of metal support plate is removed to form a window, wherein conductor layer No.1 and first is situated between
Electric layer is exposed from window.
In a second embodiment, the present invention proposes a kind of packaging system, and it includes a conductor layer No.1, a metal level, one
First dielectric layer, one second dielectric layer, one second conductor layer, guide pillar layer, a passive device, one first adhesive layer, one the 3rd
Conductor layer and a welding resisting layer.Conductor layer No.1 has a relative first surface and a second surface.Metal level is arranged at
On the first surface of one conductor layer.First dielectric layer is arranged in the subregion of conductor layer No.1, wherein the first dielectric layer is not
The first surface of conductor layer No.1 is exposed to, the first dielectric layer is not less than the second surface of conductor layer No.1.Second dielectric layer is set
It is placed on conductor layer No.1 and the first dielectric layer.Second conductor layer is arranged on conductor layer No.1 and the second dielectric layer.Guide pillar layer
It is arranged on the second conductor layer, and a concave structure is formed with the second conductor layer.Passive device is set and electrical ties are in matrix
On conductor layer No.1 in structure.First adhesive layer is arranged at the first dielectric layer, the second dielectric layer, the second conductor layer and guide pillar layer
Subregion in, and passive device is coated, wherein the first adhesive layer is not exposed to one end of guide pillar layer.Privates layer is set
On the one end for being placed in the first adhesive layer and guide pillar layer.Welding resisting layer is arranged on the first adhesive layer and privates layer.
In a second embodiment, the present invention proposes a kind of preparation method of packaging system, and its step includes：One metal is provided
Support plate, it has a relative first side and a second side；One first dielectric layer is formed in the second side of metal support plate
On；A conductor layer No.1 is formed in the second side of metal support plate, wherein the first dielectric layer is arranged at the portion of conductor layer No.1
In subregion, the first dielectric layer is not less than conductor layer No.1；One second dielectric layer is formed in conductor layer No.1 and the first dielectric layer
On；One second conductor layer is formed on conductor layer No.1 and the second dielectric layer；Guide pillar layer is formed on the second conductor layer, wherein
Guide pillar layer and the second conductor layer one concave structure of formation；The setting of one passive device is provided and electrical ties are in first in concave structure
On conductor layer；Form one first adhesive layer and coat the first dielectric layer, conductor layer No.1, the second dielectric layer, the second conductor layer, guide pillar
The second side of layer, passive device and metal support plate；Expose one end of guide pillar layer；Privates layer is formed in the first adhesive layer
With expose guide pillar layer one end on；A welding resisting layer is formed on the first adhesive layer and privates layer；Remove metal support plate
Subregion is to form a window, and wherein conductor layer No.1 exposes with the first dielectric layer from window.
The beneficial effects of the invention are as follows：It is coreless substrate that adhesive layer (Mold Compound Layer), which can be used,
The material of main part of (Coreless Substrate), and form via hole and pre- package interconnection system using guide pillar layer is electroplated
(Mold Interconnect System, MIS) packaged type is taken advantage of a situation in substrate manufacture and passive device is embedded in substrate,
Form the laminated construction that passive device is buried in simple three-layer metal layer；In addition sealing (the Mold of lower cost can be used
Compound expensive glass fibre basal plate) is replaced, and three-layer metal layer plating guide pillar laminar flow journey substitution at lower cost is high
The expensive blind buried via hole flow of four layers of metal level laser, so process time is shorter and flow is simple.
Brief description of the drawings
Fig. 1 is traditional glass fibre basal plate encapsulating structure；
Fig. 2 is the packaging system schematic diagram of first embodiment of the invention；
Fig. 3 is the packaging system preparation method flow chart of first embodiment of the invention；
Fig. 4 A to Fig. 4 R make schematic diagram for the packaging system of first embodiment of the invention；
Fig. 5 is the packaging system schematic diagram of second embodiment of the invention；
Fig. 6 is the packaging system preparation method flow chart of second embodiment of the invention；
Fig. 7 A to Fig. 7 T make schematic diagram for the packaging system of second embodiment of the invention.
Description of reference numerals：10- glass fibre basal plate encapsulating structures；100- glass fibre basal plates；110- grooves；120- is led
Through hole；130- electronic components；140- metallic conduction posts；142nd, the metal conducting layers of 144- first；146th, the metallic conductions of 148- second
Layer；150- insulating barriers；20th, 40- packaging systems；200- conductor layer No.1s；202- first surfaces；204- second surfaces；210- gold
Belong to layer；The dielectric layers of 220- first；The dielectric layers of 222- second；The conductor layers of 230- second；240- guide pillars layer；242- concave structures；
244- subregions；One end of 246- guide pillars layer；250- passive devices；The adhesive layers of 260- first；270- privates layer；280-
Welding resisting layer；290- outward elements；The adhesive layers of 292- second；294- metal balls；30th, 50- preparation methods；Step S302- steps
S336；Step S502- steps S540；300- metal support plates；302- first sides；304- second sides；306- windows；310-
One photoresist layer；The photoresist layers of 320- second；The photoresist layers of 330- the 3rd；The photoresist layers of 340- the 4th；The photoresist layers of 350- the 5th；C- cutting systems
Make process.
Embodiment
Fig. 2 is the packaging system schematic diagram of first embodiment of the invention.Packaging system 20, it includes a conductor layer No.1
200th, a metal level 210, one first dielectric layer 220, one second conductor layer 230, a guide pillar 240, one passive device 250, one of layer
First adhesive layer 260, privates layer 270 and a welding resisting layer 280.Conductor layer No.1 200 has one first relative table
The second surface 204 of face 202 and one.Metal level 210 is arranged on the first surface 202 of conductor layer No.1 200.First dielectric layer
220 be arranged on conductor layer No.1 200 with the subregion of conductor layer No.1 200, wherein the first dielectric layer 220 is not exposed to
The first surface 202 of conductor layer No.1 200.Second conductor layer 230 is arranged on the dielectric layer 220 of conductor layer No.1 200 and first.
Guide pillar layer 240 is arranged on the second conductor layer 230, and forms a concave structure 242 with the second conductor layer 230.Passive device
250 set and electrical ties on the second conductor layer 230 in concave structure 242.First adhesive layer 260 is arranged at the second conductor layer
230 with the subregion 244 of guide pillar layer 240, and coating passive device 250, wherein the first adhesive layer 260 is not exposed to and led
One end 246 of post layer 240.In the present embodiment, the first adhesive layer 260 is arranged at the complete of the second conductor layer 230 and guide pillar layer 240
In portion region, but it is not limited thereto.In addition, the first adhesive layer 260 has phenolic group resin (Novolac-Based
Resin), epoxy (Epoxy-Based Resin), silicone (Silicone-Based Resin) or other are appropriate
Covering, but be not limited thereto.Privates layer 270 is arranged at one end 246 of the first adhesive layer 260 and guide pillar layer 240
On.Welding resisting layer 280 is arranged on the first adhesive layer 260 and privates layer 270.
Wherein, packaging system 20 more may include an outward element 290, one second adhesive layer 292 and multiple metal balls 294.
Outward element 290 is set and electrical ties are on the first surface 202 of conductor layer No.1 200.Second adhesive layer 292 is arranged at external
On the first surface 202 of element 290 and conductor layer No.1 200.Multiple metal balls 294 are arranged on privates layer 270.One
In embodiment, outward element 290 is not an active member, a passive device, semiconductor wafer or a flexible circuit board, but not
As limit.
Fig. 3 is the packaging system preparation method flow chart of first embodiment of the invention, and Fig. 4 A to Fig. 4 R are the present invention first
The packaging system of embodiment makes schematic diagram.The preparation method 30 of packaging system 20, its step includes：
Step S302, as shown in Figure 4 A there is provided a metal support plate 300, it has a relative first side 302 and one
Two side faces 304.
Step S304, as shown in Figure 4 B, forms a conductor layer No.1 200 in the second side 304 of metal support plate 300.
In the present embodiment, conductor layer No.1 200 can apply electroless plating (Electroless Plating) technology, sputter
(Sputtering Coating) technology or evaporation (Thermal Coating) technology, then by lithographic manufacturing process
(Photolithography) formed, but be not limited thereto with etching manufacturing process (Etch Process).Wherein first
Conductor layer 200 can be patterning conductor layer, and it includes an at least cabling and at least chip seat, the material of conductor layer No.1 200
Matter can be metal, e.g. copper.
Step S306, as shown in Figure 4 C, forms one first dielectric layer 220 in the second side 304 of metal support plate 300 and the
On one conductor layer 200, and one first photoresist layer 310 is formed in the first side 302 of metal support plate 300.In the present embodiment
In, the first dielectric layer 220 is to apply coating manufacturing process, then by lithographic manufacturing process (Photolithography) and etching
Manufacturing process (Etch Process) is formed, and the first photoresist layer 310 is formed using pressing dry film photoresistance manufacturing process, but
It is not limited thereto.
Step S308, as shown in Figure 4 D, forms one second conductor layer 230 in the dielectric layer 220 of conductor layer No.1 200 and first
On.In the present embodiment, the second conductor layer 230 can apply electroless plating (Electroless Plating) technology, sputter
(Sputtering Coating) technology or evaporation (Thermal Coating) technology, then by lithographic manufacturing process
(Photolithography) formed, but be not limited thereto with etching manufacturing process (Etch Process).Wherein second
Conductor layer 230 can be patterning conductor layer, and it includes an at least cabling, and forms the conductor layer No.1 200 for corresponding to and exposing
On.
Step S310, as shown in Figure 4 E, forms one second photoresist layer 320 in the first dielectric layer 220 and the second conductor layer 230
On.In the present embodiment, the second photoresist layer 320 is formed using pressing dry film photoresistance manufacturing process, but is not limited thereto.
Step S312, as illustrated in figure 4f, removes the subregion of the second photoresist layer 320 to expose the second conductor layer 230.
In the present embodiment, the subregion for removing the second photoresist layer 320 is to apply lithographic manufacturing process (Photolithography) skill
Art is reached, but is not limited thereto.
Step S314, as shown in Figure 4 G, forms guide pillar layer 240 on the second conductor layer 230.In the present embodiment, lead
Post layer 240 is that technology is formed using plating (Electrolytic Plating), but is not limited thereto.Wherein, guide pillar layer
240 include an at least conductive pole, and it is formed on the cabling corresponding to the second conductor layer 230, and the material of guide pillar layer 240 can be gold
Category, e.g. copper.
Step S316, as shown at figure 4h, remove the first photoresist layer 310, the second photoresist layer 320 and form conductor layer No.1
200 in the second side 304 of metal support plate 300, formed the first dielectric layer 220 in metal support plate 300 second side 304 with
On conductor layer No.1 200, the second conductor layer 230 is formed on the dielectric layer 220 of conductor layer No.1 200 and first, and formation is led
Post layer 240 is on the second conductor layer 230, and wherein guide pillar layer 240 and the second conductor layer 230 form a concave structure 242.
Step S318, sets there is provided a passive device 250 and electrical ties is in the in concave structure 242 as shown in fig. 41
On two conductor layers 230.
Step S320, as shown in fig. 4j, forms one first adhesive layer 260 and coats the first dielectric layer 220, the second conductor layer
230th, guide pillar layer 240, the second side 304 of passive device 250 and metal support plate 300.In the present embodiment, the first adhesive layer
260 be that the encapsulation technology for being molded (Transfer Molding) using metaideophone is formed, and the material of the first adhesive layer 260 may include
Phenolic group resin (Novolac-Based Resin), epoxy (Epoxy-Based Resin), silicone
(Silicone-Based Resin) or other appropriate coverings, at high temperature and pressure, are situated between with liquid condition cladding first
Electric layer 220, the second conductor layer 230, guide pillar layer 240 and passive device 250, it forms the first adhesive layer 260 after solidifying.First envelope
Glue-line 260 also may include the silica of appropriate filler, e.g. powdery.
In another embodiment, injection moulding (Injection Molding) or compression forming can also be applied
Encapsulation technology first adhesive layer 260 of formation of (Compression Molding).
Wherein, the step of forming the first adhesive layer 260 may include：One covering is provided, wherein covering have resin and
The silica of powdery.Covering is heated to liquid condition.The covering being in a liquid state is injected in the second side of metal support plate 300
On 304, covering coats the first dielectric layer 220, the second conductor layer 230, guide pillar layer 240 and passive device at high temperature and pressure
250.Solidify covering, make covering formation the first adhesive layer 260, but formed the first adhesive layer 260 the step of not as
Limit.
Step S322, as shown in Figure 4 K, exposes one end 246 of guide pillar layer 240.In the present embodiment, guide pillar layer 240 is exposed
It is the part that the first adhesive layer 260 is removed using grinding (Grinding) mode, to expose one end 246 of guide pillar layer 240.Compared with
Good but non-exclusively, the substantial alignment of 246 and first adhesive layer of one end 260 of guide pillar layer 240 is e.g. coplanar.In another reality
Apply in example, one end 246 of guide pillar layer 240 while the first adhesive layer 260 are formed, can be exposed, without removing the first sealing
Any part of layer 260.
Step S324, as illustrated in fig. 4l, forms privates layer 270 in the first adhesive layer 260 and the guide pillar layer exposed
On 240 one end 246.In one embodiment, privates layer 270 can apply electroless plating (Electroless Plating) skill
Art, sputter (Sputtering Coating) technology or evaporation (Thermal Coating) technology formed, but not as
Limit.Wherein privates layer 270 can be patterning conductor layer, and it includes an at least cabling, and is formed corresponding to leading for exposing
On one end 246 of post layer 240, the material of privates layer 270 can be metal, e.g. copper.
Step S326, as shown in fig. 4m, formed a welding resisting layer 280 in the first adhesive layer 260 with privates layer 270,
And the privates layer 270 of exposed portion.Wherein, welding resisting layer 280 has the work(of each cabling electricity of insulation privates layer 270
Effect.
Step S328, as shown in Fig. 4 N, removes the subregion of metal support plate 300 to form a window 306, wherein first
Conductor layer 200 exposes with the first dielectric layer 220 from window 306.In the present embodiment, the subregion of metal support plate 300 is removed
It is to be reached using lithographic manufacturing process (Photolithography) with etching manufacturing process (Etch Process), first leads
The cabling of line layer 200 can also expose with chip seat from window 306, in addition, the subregion left by metal support plate 300 is to be formed
One metal level 210.
Step S330, sets there is provided an outward element 290 as shown in Fig. 4 O and electrical ties is in the of conductor layer No.1 200
On one surface 202.In one embodiment, outward element 290 is an active member, a passive device, semiconductor wafer or one
Flexible circuit board, but be not limited thereto.
Step S332, as shown in Fig. 4 P, forms one second adhesive layer 292 and is coated on outward element 290 and conductor layer No.1
On 200 first surface 202.In the present embodiment, the second adhesive layer 292 is using metaideophone shaping (Transfer Molding)
Encapsulation technology formed, the material of the second adhesive layer 292 may include phenolic group resin (Novolac-Based Resin), ring
Epoxide resin (Epoxy-Based Resin), silicone (Silicone-Based Resin) or other appropriate coverings,
At high temperature and pressure, outward element 292 is coated with liquid condition and on the first surface 202 of conductor layer No.1 200, it solidifies
After form the second adhesive layer 292.Second adhesive layer 292 also may include the silica of appropriate filler, e.g. powdery.
In another embodiment, injection moulding (Injection Molding) or compression forming can also be applied
Encapsulation technology second adhesive layer 292 of formation of (Compression Molding).
Step S334, as shown in Fig. 4 Q, forms multiple metal balls 294 on privates layer 270.Each metal ball 294
Material can be metal, e.g. copper.
Step S336, as shown in Fig. 4 R, finally again carry out cutting manufacturing process C in conductor layer No.1 200, metal level 210,
First dielectric layer 220, the second conductor layer 230, the first adhesive layer 260, privates layer 270 or welding resisting layer 280 etc. are at least within
One layer and form packaging system 20 as shown in Figure 2.
To illustrate herein, the packaging system 20 of first embodiment of the invention, it is to utilize the first adhesive layer to be seedless
The material of main part of heart substrate come replace costliness traditional glass fibre basal plate, and at lower cost three-layer metal layer plating lead
Post laminar flow journey come replace costliness the blind buried via hole flow of traditional four layer metal level laser, so process time is shorter and flow is simple
It is single, therefore cost of manufacture can be greatly reduced.
Fig. 5 is the packaging system schematic diagram of second embodiment of the invention.Packaging system 40 is substantially similar to the present invention the
The structure of the packaging system 20 of one embodiment, it include a conductor layer No.1 200, a metal level 210, one first dielectric layer 220,
One second dielectric layer 222, one second conductor layer 230,240, one passive device 250 of guide pillar layer, one first adhesive layer 260, one
Privates layer 270 and a welding resisting layer 280.Conductor layer No.1 200 has relative a first surface 202 and a second surface
204.Metal level 210 is arranged on the first surface 202 of conductor layer No.1 200.First dielectric layer 220 is arranged at conductor layer No.1
In 200 subregion, wherein the first dielectric layer 220 is not exposed to the first surface 202 of conductor layer No.1 200, the first dielectric
Layer 220 is not less than the second surface 204 of conductor layer No.1 200.Second dielectric layer 222 is arranged at conductor layer No.1 200 and first
On dielectric layer 220.Second conductor layer 230 is arranged on the dielectric layer 222 of conductor layer No.1 200 and second.Guide pillar layer 240 is arranged at
On second conductor layer 230, and a concave structure 242 is formed with the second conductor layer 230.Passive device 250 is set and electrical ties
In on the conductor layer No.1 200 in concave structure 242.First adhesive layer 260 is arranged at the first dielectric layer 220, the second dielectric layer
222nd, in the subregion 244 of the second conductor layer 230 and guide pillar layer 240, and passive device 250 is coated, wherein the first sealing
Layer 260 is not exposed to one end 246 of guide pillar layer 240.In the present embodiment, the first adhesive layer 260 is arranged at the first dielectric layer
220th, in the Zone Full of the second dielectric layer 222, the second conductor layer 230 and guide pillar layer 240, but it is not limited thereto.In addition, the
One adhesive layer 260 have phenolic group resin (Novolac-Based Resin), epoxy (Epoxy-Based Resin),
Silicone (Silicone-Based Resin) or other appropriate coverings, but be not limited thereto.Privates layer 270
On the one end 246 for being arranged at the first adhesive layer 260 and guide pillar layer 240.Welding resisting layer 280 is arranged at the first adhesive layer 260 and the 3rd
On conductor layer 270.
Wherein, packaging system 40 more may include an outward element 290, one second adhesive layer 292 and multiple metal balls 294.
Outward element 290 is set and electrical ties are on the first surface 202 of conductor layer No.1 200.Second adhesive layer 292 is arranged at external
On the first surface 202 of element 290 and conductor layer No.1 200.Multiple metal balls 294 are arranged on privates layer 270.One
In embodiment, outward element 290 is not an active member, a passive device, semiconductor wafer or a flexible circuit board, but not
As limit.
Fig. 6 is the packaging system preparation method flow chart of second embodiment of the invention, and Fig. 7 A to Fig. 7 T are the present invention second
The packaging system of embodiment makes schematic diagram.The preparation method 50 of packaging system 40, its step includes：
Step S502, as shown in Figure 7 A there is provided a metal support plate 300, it has a relative first side 302 and one
Two side faces 304.
Step S504, as shown in Figure 7 B, formed one first dielectric layer 220 in the second side 304 of metal support plate 300 with
One the 3rd photoresist layer 330 is in the first side 302 of metal support plate.In the present embodiment, the first dielectric layer 220 is using coating
Manufacturing process is formed, and the 3rd photoresist layer 330 is formed using pressing dry film photoresistance manufacturing process, but is not limited thereto.
Step S506, as seen in figure 7 c, forms a conductor layer No.1 200 in the second side 304 of metal support plate 300,
Wherein the first dielectric layer 220 is arranged in the subregion of conductor layer No.1 200, and the first dielectric layer 220 is not less than the first wire
Layer 200.In the present embodiment, conductor layer No.1 200 is formed using plating (Electrolytic Plating) technology, but
It is not limited thereto.Wherein conductor layer No.1 200 can be patterning conductor layer, and it includes an at least cabling and an at least chip
Seat, the material of conductor layer No.1 200 can be metal, e.g. copper.
Step S508, as illustrated in fig. 7d, forms one second dielectric layer 222 in the dielectric layer 220 of conductor layer No.1 200 and first
On.In the present embodiment, the second dielectric layer 222 is formed using coating manufacturing process, but is not limited thereto.
Step S510, as seen in figure 7e, forms one the 4th photoresist layer 340 in conductor layer No.1 200, the first dielectric layer 220
With on the second dielectric layer 222.In the present embodiment, the 4th photoresist layer 340 is to apply pressing dry film photoresistance manufacturing process, then is passed through
Lithographic manufacturing process (Photolithography) is formed, but is not limited thereto.
Step S512, as shown in Figure 7 F, forms one second conductor layer 230 in the dielectric layer 222 of conductor layer No.1 200 and second
On.In the present embodiment, the second conductor layer 230 is formed using plating (Electrolytic Plating) technology, but simultaneously
It is not limited.Wherein, the second conductor layer 230 includes an at least cabling, and it forms the cabling corresponding to conductor layer No.1 200
On, the material of the second conductor layer 230 can be metal, e.g. copper.
Step S514, as shown in Figure 7 G, forms one the 5th photoresist layer 350 in the 4th photoresist layer 340 and the second conductor layer 230
On.In the present embodiment, the 5th photoresist layer 350 is formed using pressing dry film photoresistance manufacturing process, but is not limited thereto.
Step S516, as shown in fig. 7h, removes the subregion of the 5th photoresist layer 350 to expose the second conductor layer 230.
In the present embodiment, the subregion for removing the 5th photoresist layer 350 is to apply lithographic manufacturing process (Photolithography) skill
Art is reached, but is not limited thereto.
Step S518, as shown in Figure 7 I, forms guide pillar layer 240 on the second conductor layer 230.In the present embodiment, lead
Post layer 240 is that technology is formed using plating (Electrolytic Plating), but is not limited thereto.Wherein, guide pillar layer
240 include an at least conductive pole, and it is formed on the cabling corresponding to the second conductor layer 230, and the material of the second conductor layer 230 can be with
For metal, e.g. copper.
Step S520, as shown in figure 7j, removes the 4th photoresist layer 340 and the 5th photoresist layer 350 and forms the first dielectric layer
220 in the second side 304 of metal support plate 300, and formation conductor layer No.1 200 is in the second side 302 of metal support plate 300
On, wherein the first dielectric layer 220 is arranged in the subregion of conductor layer No.1 200, the first dielectric layer 220, which is not less than first, leads
Line layer 200, forms the second dielectric layer 222 on the dielectric layer 220 of conductor layer No.1 200 and first, the second conductor layer 230 of formation in
On the dielectric layer 222 of conductor layer No.1 220 and second, and guide pillar layer 240 is formed on conductor layer No.1 200, wherein guide pillar layer
240 and second conductor layer 230 formation one concave structure 242.
Step S522, sets there is provided a passive device 250 and electrical ties is in the in concave structure 222 as shown in fig. 7k
On one conductor layer 200.
Step S524, as shown in fig. 7l, forms one first adhesive layer 260 and coats the first dielectric layer 220, conductor layer No.1
200th, the second dielectric layer 222, the second conductor layer 230, guide pillar layer 240, the second side of passive device 250 and metal support plate 300
304.In the present embodiment, the first adhesive layer 260 is the encapsulation technology institute shape that (Transfer Molding) is molded using metaideophone
Into the material of the first adhesive layer 260 may include phenolic group resin (Novolac-Based Resin), epoxy (Epoxy-
Based Resin), silicone (Silicone-Based Resin) or other appropriate coverings, at high temperature and pressure,
First dielectric layer 220, conductor layer No.1 200, the second dielectric layer 222, the second conductor layer 230, guide pillar layer are coated with liquid condition
240 with passive device 250, its solidify after form the first adhesive layer 260.First adhesive layer 260 also may include appropriate filler,
The e.g. silica of powdery.
In another embodiment, injection moulding (Injection Molding) or compression forming can also be applied
Encapsulation technology first adhesive layer 260 of formation of (Compression Molding).
Wherein, the step of forming the first adhesive layer 260 may include：One covering is provided, wherein covering have resin and
The silica of powdery.Covering is heated to liquid condition.The covering being in a liquid state is injected in the second side of metal support plate 300
On 304, covering coats the first dielectric layer 220, conductor layer No.1 200, the second dielectric layer 222, second at high temperature and pressure
Conductor layer 230, guide pillar layer 240 and passive device 250.Solidify covering, make covering the first adhesive layer 260 of formation, but formed
The step of first adhesive layer 260, is not limited thereto.
Step S526, as shown in Fig. 7 M, exposes one end 246 of guide pillar layer 240.In the present embodiment, guide pillar layer 240 is exposed
It is the part that the first adhesive layer 260 is removed using grinding (Grinding) mode, to expose one end 246 of guide pillar layer 240.Compared with
Good but non-exclusively, the substantial alignment of 246 and first adhesive layer of one end 260 of guide pillar layer 240 is e.g. coplanar.In another reality
Apply in example, one end 246 of guide pillar layer 240 while the first adhesive layer 260 are formed, can be exposed, without removing the first sealing
Any part of layer 260.
Step S528, as shown in figure 7n, forms privates layer 270 in the first adhesive layer 260 and the guide pillar layer exposed
On 240 one end 246.In one embodiment, privates layer 270 can apply electroless plating (Electroless Plating) skill
Art, sputter (Sputtering Coating) technology or evaporation (Thermal Coating) technology formed, but not as
Limit.Wherein privates layer 270 can be patterning conductor layer, and it includes an at least cabling, and is formed corresponding to leading for exposing
On one end 246 of post layer 240, the material of privates layer 270 can be metal, e.g. copper.
Step S530, as shown in figure 7o, formed a welding resisting layer 280 in the first adhesive layer 260 with privates layer 270,
And the privates layer 270 of exposed portion.Wherein, welding resisting layer 280 has the work(of each cabling electricity of insulation privates layer 270
Effect.
Step S532, as shown in figure 7p, removes the subregion of metal support plate 300 to form a window 306, wherein first
Conductor layer 200 exposes with the first dielectric layer 220 from window 306.In the present embodiment, the subregion of metal support plate 300 is removed
It is to be reached using lithographic manufacturing process (Photolithography) with etching manufacturing process (Etch Process), first leads
The cabling of line layer 200 can also expose with chip seat from window 306, in addition, the subregion left by metal support plate 300 is to be formed
One metal level 210.
Step S534, sets there is provided an outward element 290 and electrical ties is in the of conductor layer No.1 200 as shown in figure 7q
On one surface 202.In one embodiment, outward element 290 is an active member, a passive device, semiconductor wafer or one
Flexible circuit board, but be not limited thereto.
Step S536, as shown in figure 7r, forms one second adhesive layer 292 and is coated on outward element 290 and conductor layer No.1
On 200 first surface 202.In the present embodiment, the second adhesive layer 292 is using metaideophone shaping (Transfer Molding)
Encapsulation technology formed, the material of the second adhesive layer 292 may include phenolic group resin (Novolac-Based Resin), ring
Epoxide resin (Epoxy-Based Resin), silicone (Silicone-Based Resin) or other appropriate coverings,
At high temperature and pressure, outward element 290 is coated with liquid condition and on the first surface 202 of conductor layer No.1 200, it solidifies
After form the second adhesive layer 292.Second adhesive layer 292 also may include the silica of appropriate filler, e.g. powdery.
In another embodiment, injection moulding (Injection Molding) or compression forming can also be applied
Encapsulation technology second adhesive layer 292 of formation of (Compression Molding).
Step S538, as shown in Fig. 7 S, forms multiple metal balls 294 on privates layer 270.Each metal ball 294
Material can be metal, e.g. copper.
Step S540, as shown in figure 7t, finally again carry out cutting manufacturing process C in conductor layer No.1 200, metal level 210,
First dielectric layer 220, the second conductor layer 230, the first adhesive layer 260, privates layer 270 or welding resisting layer 280 etc. are at least within
One layer and form packaging system 40 as shown in Figure 5.
To illustrate herein, envelope of the packaging system 40 compared to first embodiment of the invention of second embodiment of the invention
Assembling device 20, it is that passive device is arranged on into position compared with the conductor layer No.1 less than the second conductor layer, therefore can reduce plating
The height and manufacturing process difficulty of guide pillar layer.In addition, forming the thickness of the thickness and the first adhesive layer of grinding of the first adhesive layer
It can therefore reduce, make making simpler and save cost.
In summary, the packaging system of first embodiment of the invention, it is coreless substrate using the first adhesive layer
Material of main part come replace costliness traditional glass fibre basal plate, and at lower cost three-layer metal layer plating guide pillar laminar flow journey
To replace the blind buried via hole flow of traditional four layer metal level laser of costliness, so process time is shorter and flow is simple, can be significantly
Reduce cost of manufacture.
In addition, the packaging system of second embodiment of the invention, it is that passive device is arranged on into position relatively to lead less than second
On the conductor layer No.1 of line layer, therefore the height and manufacturing process difficulty of plating guide pillar layer can be reduced.In addition, forming the first adhesive layer
Thickness and grind the first adhesive layer thickness also can therefore reduce, allow making it is simpler and save cost.
But particular embodiments described above, it is only for example and releases the features of the present invention and effect, not for restriction
The present invention's implements category, under the scope of the spirit and technology taken off on without departing from the present invention, any with disclosed
Content and the equivalent change and modification completed, still should be following claims and are covered.
Claims (10)
1. a kind of preparation method of packaging system, it is characterised in that step includes：
A metal support plate is provided, it has a relative first side and a second side；
A conductor layer No.1 is formed in the second side of the metal support plate；
One first dielectric layer is formed in second side and the conductor layer No.1 of the metal support plate；
One second conductor layer is formed on the conductor layer No.1 and first dielectric layer；
Guide pillar layer is formed on second conductor layer, wherein guide pillar layer forms a concave structure with second conductor layer；
The setting of one passive device is provided and electrical ties are on second conductor layer in the concave structure；
Form one first adhesive layer and coat first dielectric layer, second conductor layer, the passive device, guide pillar layer and the metal
The second side of support plate；
Expose one end of guide pillar layer；
Privates layer is formed on one end of first adhesive layer and the guide pillar exposed layer；
A welding resisting layer is formed on first adhesive layer and privates layer；And
The subregion of the metal support plate is removed to form a window, the wherein conductor layer No.1 and first dielectric layer is from the window
Mouth exposes.
2. preparation method as claimed in claim 1, it is characterised in that further include：
The setting of one outward element is provided and electrical ties are on a first surface of the conductor layer No.1；
One second adhesive layer is formed to be coated on the first surface of the outward element and the conductor layer No.1；And
Multiple metal balls are formed on privates layer.
3. preparation method as claimed in claim 1, it is characterised in that the step of forming first adhesive layer includes：
A covering is provided, the wherein covering has the silica of resin and powdery；
The covering is heated to liquid condition；
The covering being in a liquid state is injected in the second side of the metal support plate, and the covering is coated at high temperature and pressure
First dielectric layer, second conductor layer, the passive device and guide pillar layer；And
Solidify the covering, the covering is formed first adhesive layer.
4. preparation method as claimed in claim 2, it is characterised in that the outward element be an active member, a passive device,
Semiconductor wafer or a flexible circuit board.
5. preparation method as claimed in claim 1, it is characterised in that first adhesive layer has phenolic group resin, epoxy
Base resin or silicone.
6. a kind of preparation method of packaging system, it is characterised in that step includes：
A metal support plate is provided, it has a relative first side and a second side；
One first dielectric layer is formed in the second side of the metal support plate；
A conductor layer No.1 is formed in the second side of the metal support plate, wherein first dielectric layer is arranged at this and first led
In the subregion of line layer, first dielectric layer is not less than the conductor layer No.1；
One second dielectric layer is formed on the conductor layer No.1 and first dielectric layer；
One second conductor layer is formed on the conductor layer No.1 and second dielectric layer；
Guide pillar layer is formed on second conductor layer, wherein guide pillar layer forms a concave structure with second conductor layer；
The setting of one passive device is provided and electrical ties are on the conductor layer No.1 in the concave structure；
Formed one first adhesive layer coat first dielectric layer, the conductor layer No.1, second dielectric layer, second conductor layer,
The second side of guide pillar layer, the passive device and the metal support plate；
Expose one end of guide pillar layer；
Privates layer is formed on one end of first adhesive layer and the guide pillar exposed layer；
A welding resisting layer is formed on first adhesive layer and privates layer；And
The subregion of the metal support plate is removed to form a window, the wherein conductor layer No.1 and first dielectric layer is from the window
Mouth exposes.
7. preparation method as claimed in claim 6, it is characterised in that further include：
The setting of one outward element is provided and electrical ties are on a first surface of the conductor layer No.1；
One second adhesive layer is formed to be coated on the first surface of the outward element and the conductor layer No.1；And
Multiple metal balls are formed on privates layer.
8. preparation method as claimed in claim 6, it is characterised in that the step of forming first adhesive layer includes：
A covering is provided, the wherein covering has the silica of resin and powdery；
The covering is heated to liquid condition；
The covering being in a liquid state is injected in the second side of the metal support plate, and the covering is coated at high temperature and pressure
First dielectric layer, the conductor layer No.1, second dielectric layer, second conductor layer, guide pillar layer and the passive device；And
Solidify the covering, the covering is formed first adhesive layer.
9. preparation method as claimed in claim 7, it is characterised in that the outward element be an active member, a passive device,
Semiconductor wafer or a flexible circuit board.
10. preparation method as claimed in claim 6, it is characterised in that first adhesive layer has phenolic group resin, epoxy
Base resin or silicone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410051473.4A CN104851868B (en) | 2014-02-14 | 2014-02-14 | Packaging system and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410051473.4A CN104851868B (en) | 2014-02-14 | 2014-02-14 | Packaging system and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104851868A CN104851868A (en) | 2015-08-19 |
| CN104851868B true CN104851868B (en) | 2017-08-11 |
Family
ID=53851391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410051473.4A Active CN104851868B (en) | 2014-02-14 | 2014-02-14 | Packaging system and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104851868B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200807661A (en) * | 2006-07-28 | 2008-02-01 | Phoenix Prec Technology Corp | Circuit board structure having passive component and stack structure thereof |
| CN202839599U (en) * | 2012-08-23 | 2013-03-27 | 江阴长电先进封装有限公司 | Chip-embedded-type three-dimensional wafer-level packaging structure |
| CN103515252A (en) * | 2012-06-21 | 2014-01-15 | 新科金朋有限公司 | Semiconductor device and method of forming an embedded SOP fan-out package |
| TW201405673A (en) * | 2012-07-18 | 2014-02-01 | 矽品精密工業股份有限公司 | Method of forming chip scale package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130186676A1 (en) * | 2012-01-20 | 2013-07-25 | Futurewei Technologies, Inc. | Methods and Apparatus for a Substrate Core Layer |
-
2014
- 2014-02-14 CN CN201410051473.4A patent/CN104851868B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200807661A (en) * | 2006-07-28 | 2008-02-01 | Phoenix Prec Technology Corp | Circuit board structure having passive component and stack structure thereof |
| CN103515252A (en) * | 2012-06-21 | 2014-01-15 | 新科金朋有限公司 | Semiconductor device and method of forming an embedded SOP fan-out package |
| TW201405673A (en) * | 2012-07-18 | 2014-02-01 | 矽品精密工業股份有限公司 | Method of forming chip scale package |
| CN202839599U (en) * | 2012-08-23 | 2013-03-27 | 江阴长电先进封装有限公司 | Chip-embedded-type three-dimensional wafer-level packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104851868A (en) | 2015-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107636813B (en) | Semiconductor package with high density die-to-die connections and method of manufacturing the same | |
| CN102403283B (en) | Ball grid array packaging structure with basic islands and manufacturing method thereof | |
| CN105321926A (en) | Packaging device and manufacturing method thereof | |
| JP6393878B2 (en) | Electronic chip package and method for manufacturing electronic chip package | |
| CN104952828A (en) | Flip chip package on package structure and method for fabricating the same | |
| CN104916645A (en) | Semiconductor device and manufacture method of the same | |
| CN102376672A (en) | Foundation island-free ball grid array packaging structure and manufacturing method thereof | |
| CN107251664B (en) | Stereo circuit tectosome | |
| CN105304584B (en) | Interposer substrate and method of manufacturing the same | |
| CN108962840A (en) | Electronic package and manufacturing method thereof | |
| CN105489565B (en) | Package structure of embedded device and method for fabricating the same | |
| CN102376656A (en) | Foundation island-free packaging structure without pins on four surfaces and manufacturing method thereof | |
| CN102256450A (en) | Embedded circuit board of passive device and manufacturing method thereof | |
| CN105323948B (en) | Interposer substrate and method of manufacturing the same | |
| TW200828472A (en) | Method for fabricating a circuit | |
| CN104396008A (en) | Semiconductor package substrate, package system using the same and method for manufacturing thereof | |
| CN104412380B (en) | Semiconductor package substrate, the package system using semiconductor package substrate and the method for manufacturing package system | |
| CN107845610B (en) | Board structure and preparation method thereof | |
| CN106356351B (en) | Board structure and preparation method thereof | |
| CN104851869B (en) | Packaging system and preparation method thereof | |
| CN104851868B (en) | Packaging system and preparation method thereof | |
| CN103824829A (en) | Non-solder mask defined copper pad and embedded copper pad | |
| CN104851847B (en) | Packaging system and preparation method thereof | |
| CN104769712A (en) | Semiconductor device including embedded controller die and method of making same | |
| CN102403282A (en) | Packaging structure with basic islands and without pins at four sides and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180322 Address after: The Cayman Islands KY1-1205 Grand Cayman West Bay Road No. 802 Furong Road Hongge mailbox No. 31119 Patentee after: Phoenix pioneer Limited by Share Ltd Address before: Hsinchu County, Taiwan, China Patentee before: Persistent strength or power Science and Technology Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200708 Address after: Hsinchu County, Taiwan, China Patentee after: PHOENIX PIONEER TECHNOLOGY Co.,Ltd. Address before: The Cayman Islands KY1-1205 Grand Cayman West Bay Road No. 802 Furong Road Hongge mailbox No. 31119 Patentee before: PHOENIX & Corp. |