CN102403283B - Ball grid array packaging structure with basic islands and manufacturing method thereof - Google Patents

Ball grid array packaging structure with basic islands and manufacturing method thereof Download PDF

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Publication number
CN102403283B
CN102403283B CN2011103787975A CN201110378797A CN102403283B CN 102403283 B CN102403283 B CN 102403283B CN 2011103787975 A CN2011103787975 A CN 2011103787975A CN 201110378797 A CN201110378797 A CN 201110378797A CN 102403283 B CN102403283 B CN 102403283B
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Prior art keywords
metal substrate
pin
back side
basic island
grid array
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CN2011103787975A
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CN102403283A (en
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王新潮
梁志忠
谢洁人
吴昊
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN2011103787975A priority Critical patent/CN102403283B/en
Priority to PCT/CN2012/000023 priority patent/WO2013075384A1/en
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention relates to a ball grid array packaging structure with basic islands and a manufacturing method thereof. The structure comprises an outer base island (1) and an outer pin (2); a chip (5) is arranged on the front surface of the outer base island (1); an inner pin (4) is arranged on the front surface of the outer pin (2) by multi-layer electroplating way; the front surface of the inner pin (4) is extended to the side of the chip (5) and is connected with the front surface of the chip (5) through a metal wire (6); plastic packaging materials (7) are encapsulated out of the inner pin (4), the chip (5) and the metal wire (6); and solder balls (9) are arranged on the back surfaces of the outer base island (1) and the outer pin (2). The ball grid array packaging structure with basic islands and the manufacturing method thereof provided by the invention have the advantages that: the process of etching double surfaces of a metal base plate is removed, the process cost is reduced and high density capability of the inner pin is realized as the inner pin is formed in a multi-layer electroplating way.

Description

Basic island ball grid array package structure and manufacture method thereof are arranged
Technical field
The present invention relates to a kind of have basic island ball grid array package structure and manufacture method thereof, belong to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in figure 49) that to carry out encapsulation process;
Second kind: adopt metal substrate at first to carry out chemistry at the back side of metal substrate and etch partially, again plastic packaging material being carried out in the aforementioned zone that has etched partially through chemistry seals, the chemistry of pin etches partially in afterwards the front of metal substrate being carried out, carry out the plating work on pin surface in the lead frame after finishing again, namely finish the making (shown in Figure 51) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1) but, the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2) but, also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or non-conductive bonding material, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation;
3) but, again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the metal wire bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is soft materials, so caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4) but, again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in figure 50) on the contrary with the former metal leg that should belong to.
Second kind:
1), because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2), the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus under the operational environment of high temperature and low temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3) thereby, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and the smooth and easy influence production yield of lead frame transport process;
4) thereby, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and the smooth and easy influence production yield of lead frame transport process;
5), because the interior pin in lead frame front is to adopt etched technology, must be greater than 100 μ m so the pin of pin is wide in the etching, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
In order to address the above problem, the applicant in first to file name be called the patent of invention of " base island lead frame structure and production method thereof are arranged ", its application number is 20101027029.9, it has following beneficial effect:
1) but, the back side of this kind lead frame need not stick the glued membrane of the high temperature resistance of one deck costliness, so directly reduced high cost;
2) but, because the back side of this kind lead frame does not need to stick the glued membrane of one deck high temperature resistance yet, so the technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable kind is wider;
3) but, again because the back side of the lead frame of this kind does not need to stick the glued membrane of one deck high temperature resistance, guaranteed the stability of ball bonding bonding parameter, guaranteed the stability of the reliability of the quality of ball bonding and product;
4) but, again because the back side of the lead frame of this kind does not need to stick the glued membrane of one deck high temperature resistance, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material;
5), plastic packaging material is set in the zone between described metal leg (pin) and metal leg (pin), this plastic packaging material plastic packaging material in the plastic packaging process envelopes the height of whole metal leg, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again;
6), owing to used plating mode and the back etched technology of positive interior pin, so the pin in lead frame front can be extended to as much as possible the next door of Ji Dao, impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter);
7), also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip, because the length of metal wire has shortened, so also significantly reduce in the interference to signal of the existing dead resistance of metal wire, parasitic capacitance and stray inductance;
8), because having used the plating elongation technology of interior pin, so can be easy to produce the distance between high pin number and highdensity pin and the pin, make volume and the area of encapsulation significantly to dwindle;
9), because volume after being encapsulated is significantly dwindled, the more direct material cost that embodies significantly descends, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
But, still have following deficiency: after at first metal substrate carries out two-sided etching operation, follow-uply also to carry out the etching operation second time, therefore increase the cost of operation operation, also more serious to the pollution of environment; What the interior pin in lead frame front adopted in addition is etching technique, must be greater than 100 μ m so the pin of pin is wide in the etching, and the gap between interior pin and the interior pin is also greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, a kind of have basic island ball grid array package structure and manufacture method thereof are provided, it has saved the two-sided etched flow chart of metal substrate, reduced the cost of operation operation, and because interior pin adopts the multilayer plating mode to form, therefore realized the high density ability of interior pin.
The object of the present invention is achieved like this: a kind of have a basic island ball grid array package structure, be characterized in: it comprises outer Ji Dao and outer pin, described outer front, basic island is provided with chip, described outer pin front forms interior pin by the multilayer plating mode, the pin front extends to the chip next door in described, be connected with metal wire between described chip front side and the interior pin front, pin in described, chip and metal wire are encapsulated with plastic packaging material outward, the zone of described outer Ji Dao and outer pin periphery, zone between outer Ji Dao and the outer pin and the zone between outer pin and the outer pin are equipped with gap filler, and expose outside the gap filler at the back side of outer Ji Dao and outer pin, the outer Ji Dao outside exposing gap filler with outside the back side of pin be provided with the tin ball.
The present invention has the manufacture method of basic island ball grid array package structure, and described method comprises following processing step:
Step 1, get metal substrate
Step 2, pad pasting operation
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at front and the back side of metal substrate,
Step 3, the positive photoresist film of removing the part figure of metal substrate
The metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation carry out figure exposure, develop and the photoresist film of removing the part figure, exposing the regional graphics that the follow-up needs in metal substrate front are electroplated,
Step 4, plating the first metal layer
Form the first metal layer by the multilayer plating mode in the zone to the photoresist film of metal substrate front removal part figure in the step 3,
Step 5, metal substrate front and back side striping operation
The photoresist film of metal substrate front and back side remainder is removed, pin in the positive formation relatively of metal substrate,
Step 6, load routing
The implantation of chip is carried out by conduction or non-conductive bonding material in metal substrate front between the interior pin that step 5 forms, and carries out the operation of bonding metal wire between chip front side and interior pin front,
Step 7, seal
Utilize the plastic packaging material injection device, chip is implanted and the metal substrate of bonding metal wire operation is sealed the plastic packaging material operation with finishing, and carries out the curing operation after plastic packaging material is sealed,
Step 8, pad pasting operation
Utilize film sticking equipment finish seal and the metal substrate of curing operation in the front and the back side stick the photoresist film that can carry out exposure imaging respectively,
The photoresist film of part figure is removed at step 9, the metal substrate back side
The exposure of figure, the photoresist film with removal part figure of developing are carried out in the metal substrate back side that utilizes exposure imaging equipment that step 8 is finished the pad pasting operation, carry out etched regional graphics to expose the follow-up needs in the metal substrate back side,
Step 10, the metal substrate back side are carried out total eclipse and are carved or etch partially
Total eclipse is carried out in the zone of metal substrate back side removal part photoresist film in the step 9 simultaneously carve or etch partially, form the etching area of depression at the metal substrate back side, relative outer Ji Dao and the outer pin of forming of while,
Step 11, metal substrate front and back side striping operation
The photoresist film of metal substrate front and back side remainder is removed,
Gap filler is filled in step 12, metal substrate back etched zone
In the etching area at the described metal substrate back side, fill gap filler, and carry out the curing operation after gap filler is sealed,
The microetch operation is carried out at step 13, outer Ji Dao and the outer pin back side
Externally microetch is carried out in Ji Dao and zone, the outer pin back side, forms the microetch zone of depression at the metal substrate back side,
Step 14, formation tin ball
Carry out Reflow Soldering again insert tin glue in microetch zone, the metal substrate back side after, Ji Dao and the outer pin back side form the tin ball outside,
Step 15, cutting finished product
Completing steps 14 is finished the semi-finished product that form the tin ball carry out cutting operation, make to integrate in array aggregate mode originally and to contain more than cuttings of plastic-sealed body module of chip independent, made basic island ball grid array package structure finished product.
Compared with prior art, the invention has the beneficial effects as follows:
1, it has saved the two-sided and etching flow chart of secondary respectively of metal substrate, has reduced cost, time, personnel, power, the material of operation operation, has also reduced in the etching work procedure issuable harmful substance simultaneously to the pollution of environment;
2, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully.
3, has only a kind of material of lead frame during the load routing, in using the processing procedure process of superhigh temperature 380 and 420 degrees centigrade, because the expansion that the difference that does not have the multiple material coefficient of expansion is brought is impacted with contraction, guarantee superhigh temperature resistant (generally being below the 200 ℃) performance of lead frame, can should not be out of shape the warpage issues that produces lead frame because of elevated temperature heat.
4, when the plastic-sealed body paster is to the pcb board, because implanting or be coated with the tin ball in the position at plastic-sealed body pin and Ji Dao, it is big that spacing between the plastic-sealed body back side and the pcb board becomes, and especially the problem that causes tin fusion difficulty can not blown because of hot blast in the inner ring pin of plastic-sealed body or zone, basic island.
When if 5 plastic-sealed body pasters are not fine to the pcb board, need do over again again and heavily paste, because there are enough height at the tin cream place, cleaning agent cleans easily, maintenance easily behind the tin ball of burn-oning does not weld to take away as the tin ball and welds a ball again again behind the tin ball and get final product.
Description of drawings
Each operation schematic diagram of Fig. 1 ~ Figure 16 basic island ball grid array package structure embodiment 1 manufacture method for the present invention has.
The structural representation of Figure 17 (A) basic island ball grid array package structure embodiment 1 for the present invention has.
Figure 17 (B) is the vertical view of Figure 17 (A).
The structural representation of Figure 18 (A) basic island ball grid array package structure embodiment 2 for the present invention has.
Figure 18 (B) is the vertical view of Figure 18 (A).
The structural representation of Figure 19 (A) basic island ball grid array package structure embodiment 3 for the present invention has.
Figure 19 (B) is the vertical view of Figure 19 (A).
The structural representation of Figure 20 (A) basic island ball grid array package structure embodiment 4 for the present invention has.
Figure 20 (B) is the vertical view of Figure 21 (A).
The structural representation of Figure 21 (A) basic island ball grid array package structure embodiment 5 for the present invention has.
Figure 21 (B) is the vertical view of Figure 21 (A).
The structural representation of Figure 22 (A) basic island ball grid array package structure embodiment 6 for the present invention has.
Figure 22 (B) is the vertical view of Figure 22 (A).
The structural representation of Figure 23 (A) basic island ball grid array package structure embodiment 7 for the present invention has.
Figure 23 (B) is the vertical view of Figure 23 (A).
The structural representation of Figure 24 (A) basic island ball grid array package structure embodiment 8 for the present invention has.
Figure 24 (B) is the vertical view of Figure 24 (A).
The structural representation of Figure 25 (A) basic island ball grid array package structure embodiment 9 for the present invention has.
Figure 25 (B) is the vertical view of Figure 25 (A).
The structural representation of Figure 26 (A) basic island ball grid array package structure embodiment 10 for the present invention has.
Figure 26 (B) is the vertical view of Figure 26 (A).
The structural representation of Figure 27 (A) basic island ball grid array package structure embodiment 11 for the present invention has.
Figure 27 (B) is the vertical view of Figure 27 (A).
The structural representation of Figure 28 (A) basic island ball grid array package structure embodiment 12 for the present invention has.
Figure 28 (B) is the vertical view of Figure 28 (A).
The structural representation of Figure 29 (A) basic island ball grid array package structure embodiment 13 for the present invention has.
Figure 29 (B) is the vertical view of Figure 29 (A).
The structural representation of Figure 30 (A) basic island ball grid array package structure embodiment 14 for the present invention has.
Figure 30 (B) is the vertical view of Figure 30 (A).
The structural representation of Figure 31 (A) basic island ball grid array package structure embodiment 15 for the present invention has.
Figure 31 (B) is the vertical view of Figure 31 (A).
The structural representation of Figure 32 (A) basic island ball grid array package structure embodiment 16 for the present invention has.
Figure 32 (B) is the vertical view of Figure 32 (A).
The structural representation of Figure 33 (A) basic island ball grid array package structure embodiment 17 for the present invention has.
Figure 33 (B) is the vertical view of Figure 33 (A).
The structural representation of Figure 34 (A) basic island ball grid array package structure embodiment 18 for the present invention has.
Figure 34 (B) is the vertical view of Figure 34 (A).
The structural representation of Figure 35 (A) basic island ball grid array package structure embodiment 19 for the present invention has.
Figure 35 (B) is the vertical view of Figure 35 (A).
The structural representation of Figure 36 (A) basic island ball grid array package structure embodiment 20 for the present invention has.
Figure 36 (B) is the vertical view of Figure 36 (A).
The structural representation of Figure 37 (A) basic island ball grid array package structure embodiment 21 for the present invention has.
Figure 37 (B) is the vertical view of Figure 37 (A).
The structural representation of Figure 38 (A) basic island ball grid array package structure embodiment 22 for the present invention has.
Figure 38 (B) is the vertical view of Figure 38 (A).
The structural representation of Figure 39 (A) basic island ball grid array package structure embodiment 23 for the present invention has.
Figure 39 (B) is the vertical view of Figure 39 (A).
The structural representation of Figure 40 (A) basic island ball grid array package structure embodiment 24 for the present invention has.
Figure 40 (B) is the vertical view of Figure 40 (A).
The structural representation of Figure 41 (A) basic island ball grid array package structure embodiment 25 for the present invention has.
Figure 41 (B) is the vertical view of Figure 41 (A).
The structural representation of Figure 42 (A) basic island ball grid array package structure embodiment 26 for the present invention has.
Figure 42 (B) is the vertical view of Figure 42 (A).
The structural representation of Figure 43 (A) basic island ball grid array package structure embodiment 27 for the present invention has.
Figure 43 (B) is the vertical view of Figure 43 (A).
The structural representation of Figure 44 (A) basic island ball grid array package structure embodiment 28 for the present invention has.
Figure 44 (B) is the vertical view of Figure 44 (A).
The structural representation of Figure 45 (A) basic island ball grid array package structure embodiment 29 for the present invention has.
Figure 45 (B) is the vertical view of Figure 45 (A).
The structural representation of Figure 46 (A) basic island ball grid array package structure embodiment 30 for the present invention has.
Figure 46 (B) is the vertical view of Figure 46 (A).
The structural representation of Figure 47 (A) basic island ball grid array package structure embodiment 31 for the present invention has.
Figure 47 (B) is the vertical view of Figure 47 (A).
The structural representation of Figure 48 (A) basic island ball grid array package structure embodiment 32 for the present invention has.
Figure 48 (B) is the vertical view of Figure 48 (A).
Figure 49 was not for there was the schematic diagram that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The schematic diagram of flash when the four sides that Figure 50 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Figure 51 was for sealed the structural representation of two-sided etched lead frame in advance in the past.
Wherein:
Outer basic island 1, outer pin 2, interior basic island 3, interior pin 4, chip 5, metal wire 6, plastic packaging material 7, conduction or non-conductive bonding material 8, tin ball 9, gap filler 10, metal substrate 11, photoresist film 12 or 13, the first metal layer 14, passive device 15, outer static release ring 16, interior static release ring 17.
Embodiment
The present invention has basic island ball grid array package structure and manufacture method thereof as follows:
Embodiment 1: single basic island individual pen pin (Ji Dao in not having)
Referring to Figure 17 (A) and 17(B), Figure 17 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 1.Figure 17 (B) is the vertical view of Figure 17 (A).By Figure 17 (A) and Figure 17 (B) as can be seen, the present invention has basic island ball grid array package structure, it comprises outer basic island 1 and outer pin 2, described outer 1 front, basic island is provided with chip 5 by conduction or non-conductive bonding material 8, pin 4 in described outer pin 2 fronts form by the multilayer plating mode, pin 4 is referred to as the first metal layer 14 in described, pin 4 fronts extend to chip 5 next doors in described, described chip 5 positive with interior pin 4 fronts between be connected with metal wire 6, pin 4 in described, chip 5 and the metal wire 6 outer plastic packaging materials 7 that are encapsulated with, the zone of described outer basic island 1 and outer pin 2 peripheries, zone between outer basic island 1 and the outer pin 2 and the zone between outer pin 2 and the outer pin 2 are equipped with gap filler 10, and expose outside the gap filler 10 at the back side of outer basic island 1 and outer pin 2, the outer basic island 1 outside exposing gap filler 10 with outside the back side of pin 2 be provided with tin ball 9.
Its manufacture method is as follows
Step 1, get metal substrate
Referring to Fig. 1, get the suitable metal substrate of a slice thickness 11, the material of metal substrate 11 can be carried out conversion according to function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy, stainless steel or dilval etc.
Step 2, pad pasting operation
Referring to Fig. 2; utilize film sticking equipment to stick the photoresist film 12 and 13 that can carry out exposure imaging respectively at front and the back side of metal substrate 11; protecting follow-up electroplated metal layer process operation, so photoresist film can be that the dry lithography glued membrane also can be the wet type photoresist film.
Step 3, the positive part photoresist film of removing of metal substrate
Referring to Fig. 3, part figure photoresist film is carried out graph exposure, develops and removes in metal substrate 11 fronts that utilize exposure imaging equipment that step 2 is finished the pad pasting operation, to expose the figure that metal substrate 11 positive follow-up needs carry out the plating area.
Step 4, plating the first metal layer
Referring to Fig. 4, in step 3, form the first metal layer 14 by the multilayer plating mode in the zone of the photoresist film of metal substrate 11 positive removal part figures, described the first metal layer 14 can adopt and be followed successively by nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures from bottom to top.Be example with nickel, copper, Nie, Palladium, five layers of metal level of gold, wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer, and middle copper layer, nickel dam He Palladium layer mainly play a part in conjunction with increasing, and outermost gold layer mainly plays the effect with the metal wire bonding.
Step 5, metal substrate front and back side striping operation
Referring to Fig. 5, the photoresist film of metal substrate 11 fronts and back side remainder is removed pin 4 in metal substrate 11 positive formation relatively.
Step 6, load routing
Referring to Fig. 6 ~ Fig. 7, the implantation of chip 5 is carried out by conduction or non-conductive bonding material 8 in metal substrate 11 fronts between the interior pin 4 that step 5 forms, and carries out 6 operations of bonding metal wire between chip 5 fronts and interior pin 4 fronts.
Step 7, seal
Referring to Fig. 8, utilize the plastic packaging material injection device, chip is implanted and the metal substrate 11 of bonding metal wire operation is sealed the plastic packaging material operation with finishing, and carries out plastic packaging material and seal the back curing operation.
Step 8, pad pasting operation
Referring to Fig. 9; utilize film sticking equipment finish seal and curing operation after metal substrate 11 in the front and the back side stick the photoresist film 12 and 13 that can carry out exposure imaging respectively; protecting follow-up etch process operation, so photoresist film can be that the dry lithography glued membrane also can be the wet type photoresist film.
The photoresist film of part figure is removed at step 9, the metal substrate back side
Referring to Figure 10, the exposure of figure, the photoresist film with removal part figure of developing are carried out in metal substrate 11 back sides that utilize exposure imaging equipment that step 8 is finished the pad pasting operation, carry out etched zone to expose the follow-up needs in metal substrate 11 back sides.
Step 10, the metal substrate back side are carried out total eclipse and are carved or etch partially operation
The zone of removing the photoresist film of part figure referring to Figure 11, to the metal substrate back side in the step 9 is carried out total eclipse simultaneously and is carved or etch partially, and forms the etching area of depression at the metal substrate back side, forms outer basic island 1 and outer pin 2 simultaneously relatively.
Step 11, metal substrate front and back side striping operation
Referring to Figure 12, the photoresist film of metal substrate front and back side remainder is removed.
Gap filler is filled in step 12, metal substrate back etched zone
Referring to Figure 13, in the etching area at the described metal substrate back side, utilize pad device to carry out filling gap filler 10, and carry out gap filler 10 fillings or seal after curing operation, described gap filler can be that filler or packless gap filler are arranged.
Microetch is carried out at step 13, outer Ji Dao and the outer pin back side
Referring to Figure 14, externally microetch is carried out in Ji Dao and zone, the outer pin back side, forms the microetch zone of depression at the metal substrate back side.
Step 14, formation tin ball
Referring to Figure 15, carry out Reflow Soldering again after in microetch zone, the metal substrate back side, inserting tin glue, the tin of Ji Dao and outer pin back side formation outside ball 9.
Step 15, cutting finished product
Referring to Figure 16, step 14 is finished the semi-finished product that form the tin ball carry out cutting operation, make to integrate in array aggregate mode originally and to contain more than cuttings of plastic-sealed body module of chip independent, made basic island ball grid array package structure finished product.
Embodiment 2: single basic island individual pen pin (interior Ji Dao is arranged)
Referring to Figure 18 (A) and Figure 18 (B), Figure 18 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 2.Figure 18 (B) is the vertical view of Figure 18 (A).By Figure 18 (A) and Figure 18 (B) as can be seen, embodiment 2 only is with the difference of embodiment 1: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 3: single basic island individual pen pin passive device (Ji Dao in not having)
Referring to Figure 19 (A) and Figure 19 (B), Figure 19 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 3.Figure 19 (B) is the vertical view of Figure 19 (A).By Figure 19 (A) and Figure 19 (B) as can be seen, the difference of embodiment 3 and embodiment 1 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 4: single basic island individual pen pin passive device (interior Ji Dao is arranged)
Referring to Figure 20 (A) and Figure 20 (B), Figure 20 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 4.Figure 20 (B) is the vertical view of Figure 20 (A).By Figure 20 (A) and Figure 20 (B) as can be seen, embodiment 4 only is with the difference of embodiment 3: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 5: single basic island individual pen pin static release ring (Ji Dao in not having)
Referring to Figure 21 (A) and Figure 21 (B), Figure 21 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 5.Figure 21 (B) is the vertical view of Figure 21 (A).By Figure 21 (A) and Figure 21 (B) as can be seen, the difference of embodiment 5 and embodiment 1 only is: be provided with outer static release ring 16 between described outer basic island 1 and the outer pin 2, static release ring 17 in described outer static release ring 16 fronts form by the multilayer plating mode, described in static release ring 17 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 6: single basic island individual pen pin static release ring (interior Ji Dao is arranged)
Referring to Figure 22 (A) and Figure 22 (B), Figure 22 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 6.Figure 22 (B) is the vertical view of Figure 22 (A).By Figure 22 (A) and Figure 22 (B) as can be seen, embodiment 6 only is with the difference of embodiment 5: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 7: single basic island individual pen pin static release ring passive device (Ji Dao in not having)
Referring to Figure 23 (A) and Figure 23 (B), Figure 23 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 7.Figure 23 (B) is the vertical view of Figure 23 (A).By Figure 23 (A) and Figure 23 (B) as can be seen, the difference of embodiment 7 and embodiment 5 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 8: single basic island individual pen pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 24 (A) and Figure 24 (B), Figure 24 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 8.Figure 24 (B) is the vertical view of Figure 24 (A).By Figure 24 (A) and Figure 24 (B) as can be seen, embodiment 8 only is with the difference of embodiment 7: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 9: single basic island multi-turn pin (Ji Dao in not having)
Referring to Figure 25 (A) and Figure 25 (B), Figure 25 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 9.Figure 25 (B) is the vertical view of Figure 25 (A).By Figure 25 (A) and Figure 25 (B) as can be seen, embodiment 9 only is with the difference of embodiment 1: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 10: single basic island multi-turn pin (interior Ji Dao is arranged)
Referring to Figure 26 (A) and Figure 26 (B), Figure 26 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 10.Figure 26 (B) is the vertical view of Figure 26 (A).By Figure 26 (A) and Figure 26 (B) as can be seen, embodiment 10 only is with the difference of embodiment 9: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 11: single basic island multi-turn pin passive device (Ji Dao in not having)
Referring to Figure 27 (A) and Figure 27 (B), Figure 27 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 11.Figure 27 (B) is the vertical view of Figure 27 (A).By Figure 27 (A) and Figure 27 (B) as can be seen, the difference of embodiment 11 and embodiment 9 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 12: single basic island multi-turn pin passive device (interior Ji Dao is arranged)
Referring to Figure 28 (A) and Figure 28 (B), Figure 28 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 12.Figure 28 (B) is the vertical view of Figure 28 (A).By Figure 28 (A) and Figure 28 (B) as can be seen, embodiment 12 only is with the difference of embodiment 11: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 13: single basic island multi-turn pin static release ring (Ji Dao in not having)
Referring to Figure 29 (A) and Figure 29 (B), Figure 29 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 13.Figure 29 (B) is the vertical view of Figure 29 (A).By Figure 29 (A) and Figure 29 (B) as can be seen, the difference of embodiment 13 and embodiment 9 only is: be provided with outer static release ring 16 between described outer basic island 1 and the outer pin 2, static release ring 17 in described outer static release ring 16 fronts form by the multilayer plating mode, described in static release ring 17 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 14: single basic island multi-turn pin static release ring (interior Ji Dao is arranged)
Referring to Figure 30 (A) and Figure 30 (B), Figure 30 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 14.Figure 30 (B) is the vertical view of Figure 30 (A).By Figure 30 (A) and Figure 30 (B) as can be seen, embodiment 14 only is with the difference of embodiment 13: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 15: single basic island multi-turn pin static release ring passive device (Ji Dao in not having)
Referring to Figure 31 (A) and Figure 31 (B), Figure 31 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 15.Figure 31 (B) is the vertical view of Figure 31 (A).By Figure 31 (A) and Figure 31 (B) as can be seen, the difference of embodiment 15 and embodiment 13 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 16: single basic island multi-turn pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 32 (A) and Figure 32 (B), Figure 32 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 16.Figure 32 (B) is the vertical view of Figure 32 (A).By Figure 32 (A) and Figure 32 (B) as can be seen, embodiment 16 only is with the difference of embodiment 15: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 17: how basic island individual pen pin (Ji Dao in not having)
Referring to Figure 33 (A) and Figure 33 (B), Figure 33 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 17.Figure 33 (B) is the vertical view of Figure 33 (A).By Figure 33 (A) and Figure 33 (B) as can be seen, embodiment 17 only is with the difference of embodiment 1: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 18: how basic island individual pen pin (interior Ji Dao is arranged)
Referring to Figure 34 (A) and Figure 34 (B), Figure 34 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 18.Figure 34 (B) is the vertical view of Figure 34 (A).By Figure 34 (A) and Figure 34 (B) as can be seen, embodiment 18 only is with the difference of embodiment 17: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 19: how basic island individual pen pin passive device (Ji Dao in not having)
Referring to Figure 35 (A) and Figure 35 (B), Figure 35 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 19.Figure 35 (B) is the vertical view of Figure 35 (A).By Figure 35 (A) and Figure 35 (B) as can be seen, embodiment 19 only is with the difference of embodiment 3: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 20: how basic island individual pen pin passive device (interior Ji Dao is arranged)
Referring to Figure 36 (A) and Figure 36 (B), Figure 36 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 20.Figure 36 (B) is the vertical view of Figure 36 (A).By Figure 36 (A) and Figure 36 (B) as can be seen, embodiment 20 only is with the difference of embodiment 19: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 21: how basic island individual pen pin static release ring (Ji Dao in not having)
Referring to Figure 37 (A) and Figure 37 (B), Figure 37 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 21.Figure 37 (B) is the vertical view of Figure 37 (A).By Figure 37 (A) and Figure 37 (B) as can be seen, embodiment 21 only is with the difference of embodiment 5: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 22: how basic island individual pen pin static release ring (interior Ji Dao is arranged)
Referring to Figure 38 (A) and Figure 38 (B), Figure 38 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 22.Figure 38 (B) is the vertical view of Figure 38 (A).By Figure 38 (A) and Figure 38 (B) as can be seen, embodiment 22 is with the difference of embodiment 21: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 23: how basic island individual pen pin static release ring passive device (Ji Dao in not having)
Referring to Figure 39 (A) and Figure 39 (B), Figure 39 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 23.Figure 39 (B) is the vertical view of Figure 39 (A).By Figure 39 (A) and Figure 39 (B) as can be seen, embodiment 23 only is with the difference of embodiment 7: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 24: how basic island individual pen pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 40 (A) and Figure 40 (B), Figure 40 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 24.Figure 40 (B) is the vertical view of Figure 40 (A).By Figure 40 (A) and Figure 40 (B) as can be seen, embodiment 24 only is with the difference of embodiment 23: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 25: how basic island multi-turn pin (Ji Dao in not having)
Referring to Figure 41 (A) and Figure 41 (B), Figure 41 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 25.Figure 41 (B) is the vertical view of Figure 41 (A).By Figure 41 (A) and Figure 41 (B) as can be seen, embodiment 25 only is with the difference of embodiment 17: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 26: how basic island multi-turn pin (interior Ji Dao is arranged)
Referring to Figure 42 (A) and Figure 42 (B), Figure 42 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 26.Figure 42 (B) is the vertical view of Figure 42 (A).By Figure 42 (A) and Figure 42 (B) as can be seen, embodiment 26 only is with the difference of embodiment 25: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 27: how basic island multi-turn pin passive device (Ji Dao in not having)
Referring to Figure 43 (A) and Figure 43 (B), Figure 43 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 27.Figure 43 (B) is the vertical view of Figure 43 (A).By Figure 43 (A) and Figure 43 (B) as can be seen, embodiment 27 only is with the difference of embodiment 19: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 28: how basic island multi-turn pin passive device (interior Ji Dao is arranged)
Referring to Figure 44 (A) and Figure 44 (B), Figure 44 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 28.Figure 44 (B) is the vertical view of Figure 44 (A).By Figure 44 (A) and Figure 44 (B) as can be seen, embodiment 28 only is with the difference of embodiment 27: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 29: how basic island multi-turn pin static release ring (Ji Dao in not having)
Referring to Figure 45 (A) and Figure 45 (B), Figure 45 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 29.Figure 45 (B) is the vertical view of Figure 45 (A).By Figure 45 (A) and Figure 45 (B) as can be seen, embodiment 29 is with the difference of embodiment 21: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 30: how basic island multi-turn pin static release ring (interior Ji Dao is arranged)
Referring to Figure 46 (A) and Figure 46 (B), Figure 46 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 30.Figure 46 (B) is the vertical view of Figure 46 (A).By Figure 46 (A) and Figure 46 (B) as can be seen, embodiment 30 is with the difference of embodiment 29: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 31: how basic island multi-turn pin static release ring passive device (Ji Dao in not having)
Referring to Figure 47 (A) and Figure 47 (B), Figure 47 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 31.Figure 47 (B) is the vertical view of Figure 47 (A).By Figure 47 (A) and Figure 47 (B) as can be seen, embodiment 31 is with the difference of embodiment 23: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 32: how basic island multi-turn pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 48 (A) and Figure 48 (B), Figure 48 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 32.Figure 48 (B) is the vertical view of Figure 48 (A).By Figure 48 (A) and Figure 48 (B) as can be seen, embodiment 32 is with the difference of embodiment 31: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.

Claims (7)

1. manufacture method that basic island ball grid array package structure is arranged is characterized in that described method comprises following processing step:
Step 1, get metal substrate
Step 2, pad pasting operation
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at front and the back side of metal substrate,
Step 3, the positive photoresist film of removing the part figure of metal substrate
The metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation carry out figure exposure, develop and the photoresist film of removing the part figure, exposing the zone that the follow-up needs in metal substrate front are electroplated,
Step 4, plating the first metal layer
The positive zone of removing the photoresist film of part figure of metal substrate in the step 3 is formed the first metal layer by the multilayer plating mode,
Step 5, metal substrate front and back side striping operation
The photoresist film of metal substrate front and back side remainder is removed, pin in the positive formation relatively of metal substrate,
Step 6, load routing
The implantation of chip is carried out by conduction or non-conductive bonding material in metal substrate front between the interior pin that step 5 forms, and carries out the operation of bonding metal wire between chip front side and interior pin front,
Step 7, seal
Utilize the plastic packaging material injection device, chip is implanted and the metal substrate of bonding metal wire operation is sealed the plastic packaging material operation with finishing, and carries out the curing operation after plastic packaging material is sealed,
Step 8, pad pasting operation
Utilize film sticking equipment to seal and the photoresist film that can carry out exposure imaging is sticked at front and the back side of the metal substrate of curing operation respectively finishing,
The photoresist film of part figure is removed at step 9, the metal substrate back side
The exposure of figure, the photoresist film with removal part figure of developing are carried out in the metal substrate back side that utilizes exposure imaging equipment that step 8 is finished the pad pasting operation, carry out etched zone to expose the follow-up needs in the metal substrate back side,
Step 10, the metal substrate back side are carried out total eclipse and are carved or etch partially operation
The graphics field of metal substrate back side removal part photoresist film in the step 9 is carried out total eclipse simultaneously carve or etch partially, form the etching area of depression at the metal substrate back side, relative outer Ji Dao and the outer pin of forming of while,
Step 11, metal substrate front and back side striping operation
The photoresist film of metal substrate front and back side remainder is removed,
Gap filler is filled in step 12, metal substrate back etched zone
The equipment of utilize filling in the etching area at the described metal substrate back side carries out the filling gap filler, and carry out the gap filler filling or seal after curing operation,
Microetch is carried out at step 13, outer Ji Dao and the outer pin back side
Externally microetch is carried out in Ji Dao and zone, the outer pin back side, forms the microetch zone of depression at the metal substrate back side,
Step 14, formation tin ball
Carry out Reflow Soldering again insert tin glue in microetch zone, the metal substrate back side after, Ji Dao and the outer pin back side form the tin ball outside,
Step 15, cutting finished product
Completing steps 14 is finished the semi-finished product that form the tin ball carry out cutting operation, make to integrate in array aggregate mode originally and to contain more than cuttings of plastic-sealed body module of chip independent, made basic island ball grid array package structure finished product.
2. the manufacture method that basic island ball grid array package structure is arranged according to claim 1, it is characterized in that: the front of described outer Ji Dao (1) forms one or more interior Ji Dao (3) by the multilayer plating mode, and described chip (5) is arranged at interior Ji Dao (3) front by conduction or non-conductive bonding material (8).
3. the manufacture method that basic island ball grid array package structure is arranged according to claim 1 is characterized in that: by conduction or non-conductive bonding material (8) cross-over connection passive device (15) is arranged between pin (4) and the interior pin (4) in described.
4. the manufacture method that basic island ball grid array package structure is arranged according to claim 1, it is characterized in that: be provided with outer static release ring (16) between described outer Ji Dao (1) and the outer pin (2), described outer static release ring (16) is positive to form interior static release ring (17) by the multilayer plating mode, described in static release ring (17) positive with chip (5) front between be connected by metal wire (6).
5. according to one of them described manufacture method that basic island ball grid array package structure is arranged of claim 1 ~ 4, it is characterized in that: described outer Ji Dao (1) has single, and described outer pin (2) has multi-turn.
6. according to one of them described manufacture method that basic island ball grid array package structure is arranged of claim 1 ~ 4, it is characterized in that: described outer Ji Dao (1) has a plurality of, and described outer pin (2) has individual pen.
7. according to one of them described manufacture method that basic island ball grid array package structure is arranged of claim 1 ~ 4, it is characterized in that: described outer Ji Dao (1) has a plurality of, and described outer pin (2) has multi-turn.
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