CN102867789B - Single-chip positively-arranged first-encapsulated second-etched base island-exposed encapsulating structure and manufacturing method thereof - Google Patents
Single-chip positively-arranged first-encapsulated second-etched base island-exposed encapsulating structure and manufacturing method thereof Download PDFInfo
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- CN102867789B CN102867789B CN201210140783.4A CN201210140783A CN102867789B CN 102867789 B CN102867789 B CN 102867789B CN 201210140783 A CN201210140783 A CN 201210140783A CN 102867789 B CN102867789 B CN 102867789B
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/181—Encapsulation
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Abstract
The invention relates to a single-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure and a manufacturing method thereof. The structure comprises a base island (1) and a pin (2), wherein a chip (4) is arranged on the front face of the base island (1); the front face of the chip (4) is connected with the front face of the pin (2) through a metal wire (5); plastic sealing materials (6) are enveloped in regions around the base island (1) and the pin (2) as well as outside the chip (4) and the metal wire (5); the surfaces of the plastic sealing materials (6) on the lower parts of the base island (1) and the pin (2) are provided with small holes (7); the small holes (7) are communicated with the back face of the base island (1) or the pin (2); and metal balls (9) are arranged in the small holes (7), and are contacted with the back face of the base island (1) or the pin (2). The single-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure has the beneficial effects that the manufacturing cost is lowered, the safety and the reliability of an encapsulating body are enhanced, environmental pollution is lowered, and design and manufacturing of a high-density circuit are realized truly.
Description
Technical field
The present invention relates to a kind of single-chip formal dress and first encapsulate the base island exposed encapsulating structure of after etching and manufacture method thereof.Belong to technical field of semiconductor encapsulation.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step one, see Figure 38, get the substrate that a glass fiber material is made,
Step 2, see Figure 39, perforate on desired position on glass fibre basal plate,
Step 3, see Figure 40, at back side coating one deck Copper Foil of glass fibre basal plate,
Step 4, see Figure 41, glass fibre basal plate punching position insert conductive materials,
Step 5, see Figure 42, at front coating one deck Copper Foil of glass fibre basal plate,
Step 6, see Figure 43, in glass fibre basal plate covering surface photoresistance film,
Step 7, see Figure 44, the position that photoresistance film is needing is carried out exposure imaging and is windowed,
Step 8, see Figure 45, to etch completing the part of windowing,
Step 9, see Figure 46, the photoresistance film of substrate surface to be divested,
Step 10, see Figure 47, carry out the coating of solder mask (being commonly called as green paint) on the surface of copper foil circuit layer,
Step 11, see Figure 48, after solder mask needs to carry out, window in the load of operation and the region of routing bonding,
Step 12, see Figure 49, the region of carrying out windowing in step 11 is electroplated, and relatively forms Ji Dao and pin,
Step 13, complete the concerned process steps such as follow-up load, routing, encapsulating, cutting.
Above-mentioned conventional high-density substrate encapsulation structure has the following disadvantages and defect:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must glass fibre be used, so just many thickness space of layer of glass thickness about 100 ~ 150 μm;
3, glass fibre inherently a kind of foaming substance, so easily because the time of placing and environment suck moisture and moisture, directly have influence on the security capabilities of reliability or the grade of reliability;
4, fiberglass surfacing has been coated to the Copper Foil metal layer thickness of one deck about 50 ~ 100 μm, and the etching distance of metal level circuit and circuit is also because the characteristic of etching factor can only accomplish that the etched gap of 50 ~ 100 μm is (see Figure 50, best making ability is that etched gap is about equal to by the thickness of etching object), so the design and manufaction accomplishing high-density line that cannot be real;
5, because must use Copper Foil metal level, and Copper Foil metal level is the mode of employing high pressure stickup, so the thickness of Copper Foil is difficult to the thickness lower than 50 μm, otherwise is just difficult to operation as out-of-flatness or Copper Foil breakage or Copper Foil extension displacement etc.;
6, also because whole baseplate material be adopt glass fiber material, so significantly increase the thickness 100 ~ 150 μm of glass layer, cannot be real accomplish ultra-thin encapsulation;
7, conventional fiber glass sticks on the technology of Copper Foil because material property difference very large (coefficient of expansion), in the operation of adverse circumstances, easily cause stress deformation, directly has influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of single-chip formal dress is provided first to encapsulate the base island exposed encapsulating structure of after etching and manufacture method thereof, its technique is simple, do not need to use glass layer, decrease manufacturing cost, improve the safety and reliability of packaging body, decrease the environmental pollution that glass fiber material brings, and the employing of metal substrate line layer is electro-plating method, really can accomplish the Design and manufacture of high-density line.
The object of the present invention is achieved like this: a kind of single-chip formal dress first encapsulates the base island exposed encapsulating structure of after etching, it comprises Ji Dao and pin, described Ji Dao front is provided with chip by conduction or non-conductive bonding material, be connected with metal wire between described chip front side with pin front, the region of periphery, described base island, region between Ji Dao and pin, region between pin and pin, the region on Ji Dao and pin top, the region of Ji Dao and pin bottom and chip and metal wire are all encapsulated with plastic packaging material outward, the plastic packaging material of described Ji Dao and pin bottom offers aperture on the surface, described aperture is connected with Ji Dao or the pin back side, Metal Ball is provided with in described aperture, described Metal Ball and Ji Dao or pin back face touch.
Single-chip formal dress first encapsulates a manufacture method for the base island exposed encapsulating structure of after etching, and it comprises following processing step:
Step one, get metal substrate
Step 2, metallic substrate surfaces preplating copper material
One deck copper material film is electroplated in metallic substrate surfaces,
Step 3, the operation of subsides photoresistance film
Subsides photoresistance film equipment is utilized to carry out the coating of photoresistance film in the metal substrate front and the back side that complete preplating copper material film,
Step 4, metal substrate front removal unit divide photoresistance film
Carry out graph exposure, develop and window in the metal substrate front utilizing exposure imaging equipment to complete pad pasting operation in step 3, to expose the graphics field that the follow-up needs in metal substrate front carry out electroplating,
Step 5, plating inert metal line layer
The metal substrate back side is completed the upper inert metal line layer of graphics field plating of windowing,
Step 6, plated metal line layer
Metallic circuit layer on inert metal line layer plated surface in step 5, namely described metallic circuit layer forms Ji Dao top and pin top at metal substrate vis-a-vis after having electroplated,
Step 7, removal metallic substrate surfaces photoresistance film
The photoresistance film of metallic substrate surfaces is removed,
Step 8, coating bonding material
At the base island top front face coated with conductive that step 6 is formed relatively or nonconducting bonding material,
Step 9, load
The conduction or non-conductive bonding material of the coating of step 8 Ji Dao top are carried out the implantation of chip,
Step 10, wire bond
The operation of bond wire line is carried out between chip front side and pin front,
Step 11, encapsulating
The operation of encapsulating plastic packaging material is carried out by completing the metal substrate front after load routing,
Step 12, the operation of subsides photoresistance film
The metal substrate front and the back side that subsides photoresistance film equipment completes encapsulating plastic packaging material is utilized to carry out the coating of photoresistance film,
Step 13, metal substrate back side removal unit divide photoresistance film
Carry out graph exposure, develop and window in the metal substrate back side utilizing exposure imaging equipment to complete pad pasting operation in step 12, to expose the follow-up graphics field needing to carry out chemical etching, the metal substrate back side,
Step 14, chemical etching
The metal substrate back side in step 13 is completed the graphics field of windowing and carries out chemical etching,
Step 15, plated metal line layer
The plating of metallic circuit layer is carried out on the inert metal line layer surface of exposing after step 14 completes chemical etching, and namely metallic circuit layer forms Ji Dao bottom and pin bottom at the metal substrate back side after having electroplated relatively,
Step 10 six, removal metallic substrate surfaces photoresistance film
The photoresistance film of metallic substrate surfaces is removed,
Step 10 seven, encapsulating
Step 10 six is removed the encapsulating operation that plastic packaging material is carried out at the metal substrate back side after photoresistance film,
The surface perforate of step 10 eight, plastic packaging material
Carry out on the surface of step 10 seven metal substrate back side encapsulating plastic packaging material follow-up to plant Metal Ball region open operation,
Step 10 nine, cleaning
Step 10 eight metal substrate back side plastic packaging material tapping is cleaned,
Step 2 ten, plant ball
Metal Ball is implanted into through the aperture of cleaning in step 10 nine,
Step 2 11, cutting finished product
Step 2 ten is completed the semi-finished product of planting ball and carry out cutting operation, make originally to integrate in array aggregate mode and contain plastic-sealed body module more than cutting of chip independent, obtain single-chip formal dress and first encapsulate the base island exposed encapsulating structure finished product of after etching.
Described step 10 nine pairs of metal substrate back side plastic packaging material tappings clean carry out simultaneously coat of metal be coated to.
Be provided with static release ring between described Ji Dao and pin, described static release ring front is connected by metal wire with between chip front side.
Cross-over connection passive device between described pin and pin, described passive device is connected across between pin front and pin front or is connected across between the pin back side and the pin back side.
Described pin has multi-turn.
Described Ji Dao comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and described Ji Dao top and Ji Dao bottom form by single or multiple lift metal plating, and described intermediate barrier layers is nickel dam, titanium layer or layers of copper.
Described pin comprises pin top, pin bottom and intermediate barrier layers, and described pin top and pin bottom form by single or multiple lift metal plating, and described intermediate barrier layers is nickel dam, titanium layer or layers of copper.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention does not need to use glass layer, so can reduce the cost that glass layer brings;
2, the present invention does not use the foaming substance of glass layer, so the grade of reliability can improve again, relatively will improve the fail safe of packaging body;
3, the present invention does not need to use glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4, two-dimensional metallic substrate circuit layer of the present invention adopted is electro-plating method, and the gross thickness of electrodeposited coating is about 10 ~ 15 μm, and the gap between circuit and circuit can reach the gap of less than 25 μm easily, so the technical capability of pin connection tiling in high density can be accomplished veritably;
5, two-dimensional metallic substrate of the present invention is metal level galvanoplastic because of what adopt, so come simple than the technique of glass fibre high pressure Copper Foil metal level, and do not have metal level because high pressure produces the damaged and metal level of metal level out-of-flatness, metal level and to extend the bad of displacement or puzzled;
6, two-dimensional metallic substrate circuit layer of the present invention carries out metal plating on the surface of metal base, so material characteristic is substantially identical, so coating circuit is substantially identical with the internal stress of metal base, the rear engineering (the surface mount work as high temperature eutectic load, high temperature tin material solder load and high temperature passive device) of adverse circumstances can be carried out easily and be not easy to produce stress deformation.
Accompanying drawing explanation
Fig. 1 ~ Figure 21 is each operation schematic diagram that single-chip formal dress of the present invention first encapsulates after etching base island exposed encapsulating structure embodiment 1 manufacture method.
Figure 22 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 1 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 22 (B) is Figure 22 (A).
Figure 23 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 2 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 23 (B) is Figure 23 (A).
Figure 24 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 3 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 24 (B) is Figure 24 (A).
Figure 25 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 4 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 25 (B) is Figure 25 (A).
Figure 26 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 5 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 26 (B) is Figure 26 (A).
Figure 27 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 6 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 27 (B) is Figure 27 (A).
Figure 28 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 7 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 28 (B) is Figure 28 (A).
Figure 29 (A) first encapsulates the structural representation of the base island exposed encapsulating structure embodiment 8 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 29 (B) is Figure 29 (A).
Figure 30 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 9 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 30 (B) is Figure 30 (A).
Figure 31 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 10 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 31 (B) is Figure 31 (A).
Figure 32 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 11 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 32 (B) is Figure 32 (A).
Figure 33 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 12 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 33 (B) is Figure 33 (A).
Figure 34 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 13 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 34 (B) is Figure 34 (A).
Figure 35 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 14 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 35 (B) is Figure 35 (A).
Figure 36 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 15 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 36 (B) is Figure 36 (A).
Figure 37 (A) first etches the structural representation of the base island exposed encapsulating structure embodiment 16 of rear encapsulation for single-chip formal dress of the present invention.
The vertical view that Figure 37 (B) is Figure 37 (A).
Figure 38 ~ Figure 49 is each operation schematic diagram of the manufacturing process flow of traditional high-density base board encapsulating structure.
Figure 50 is the etching situation schematic diagram of fiberglass surfacing Copper Foil metal level.
Wherein:
Base island 1
Pin 2
Conduction or non-conductive bonding material 3
Chip 4
Metal wire 5
Plastic packaging material 6
Aperture 7
Coat of metal 8
Metal Ball 9
Static release ring 10
Passive device 11
Metal substrate 12
Copper material film 13
Photoresistance film 14
Inert metal line layer 15
Metallic circuit layer 16.
Embodiment
A kind of single-chip of the present invention formal dress first encapsulate the base island exposed encapsulating structure of after etching and manufacture method as follows:
Embodiment 1: Dan Ji island individual pen pin
The structural representation of the base island exposed encapsulating structure embodiment 1 of after etching is first encapsulated see Figure 22 (A) and Figure 22 (B), Figure 22 (A) single-chip of the present invention formal dress.The vertical view that Figure 22 (B) is Figure 22 (A).As can be seen from Figure 22 (A) and Figure 22 (B), single-chip formal dress of the present invention first encapsulates the base island exposed encapsulating structure of after etching, it comprises base island 1 and pin 2, front, described base island 1 is provided with chip 4 by conduction or non-conductive bonding material 3, described chip 4 front is connected with metal wire 5 with between pin 2 front, the region of periphery, described base island 1, region between base island 1 and pin 2, region between pin 2 and pin 2, the region on base island 1 and pin 2 top, the region of base island 1 and pin 2 bottom and chip 4 and metal wire 5 is outer is all encapsulated with plastic packaging material 6, the plastic packaging material 6 of described base island 1 and pin 2 bottom offers aperture 7 on the surface, described aperture 7 is connected with base island 1 or pin 2 back side, Metal Ball 9 is provided with in described aperture 7, described Metal Ball 9 is touched with base island 1 or pin 2 back face.
Be provided with coat of metal 8 between described Metal Ball 9 and base island 1 or pin 2 back side, described coat of metal 8 is antioxidant.
Described Metal Ball 9 material adopts tin or ashbury metal.
Described base island 1 comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and described Ji Dao top and Ji Dao bottom form by single or multiple lift metal plating, and described intermediate barrier layers is nickel dam, titanium layer or layers of copper.
Described pin 2 comprises pin top, pin bottom and intermediate barrier layers, and described pin top and pin bottom form by single or multiple lift metal plating, and described intermediate barrier layers is nickel dam, titanium layer or layers of copper.
Its manufacture method is as follows:
Step one, get metal substrate
See Fig. 1, get the metal substrate that a slice thickness is suitable, the material of metal substrate can convert according to the function of chip and characteristic, such as: copper material, iron material, ferronickel material, zinc-iron material etc.
Step 2, metallic substrate surfaces preplating copper material
See Fig. 2, electroplate one deck copper material film in metallic substrate surfaces, object is that the mode of described plating can adopt chemical plating or metallide for basis is done in follow-up plating.
Step 3, the operation of subsides photoresistance film
See Fig. 3, utilize subsides photoresistance film equipment to carry out the coating of photoresistance film in the metal substrate front and the back side that complete preplating copper material film, described photoresistance film can adopt wet type photoresistance film or dry type photoresistance film.
Step 4, metal substrate front removal unit divide photoresistance film
See Fig. 4, carry out graph exposure, develop and window in the metal substrate front utilizing exposure imaging equipment to complete pad pasting operation in step 3, to expose the graphics field that the follow-up needs in metal substrate front carry out electroplating.
Step 5, plating inert metal line layer
See Fig. 5, the metal substrate back side is completed the upper inert metal line layer of graphics field plating of windowing, as the barrier layer of subsequent etch operation, described inert metal wiring material layer adopts nickel, titanium or copper etc., and described plating mode adopts chemical plating or metallide mode.
Step 6, plated metal line layer
See Fig. 6, metallic circuit layer on inert metal line layer plated surface in step 5, namely described metallic circuit layer forms Ji Dao top and pin top at metal substrate vis-a-vis after having electroplated, described metallic circuit layer can be single or multiple lift, described metallic circuit layer material adopts the golden or NiPdAu of silver, aluminium, copper, nickel etc., the mode of described plating mode can be electroless plating also can be metallide.
Step 7, removal metallic substrate surfaces photoresistance film
See Fig. 7, the photoresistance film of metallic substrate surfaces removed, minimizing technology adopts chemical medicinal liquid to soften and the mode adopting high pressure water jets to remove.
Step 8, coating bonding material
See Fig. 8, at the base island top front face coated with conductive that step 6 is formed relatively or nonconducting bonding material, object is the joint for follow-up implanted chip Hou Yuji island.
Step 9, load
See Fig. 9, the conduction or non-conductive bonding material of the coating of step 8 Ji Dao top are carried out the implantation of chip.
Step 10, wire bond
See Figure 10, carry out the operation of bond wire line between chip front side and pin front, the material of described metal wire adopts gold, silver, copper, aluminium or alloy material, and the shape of metal wire can be thread also can be banded.
Step 11, encapsulating
See Figure 11, the operation of encapsulating plastic packaging material is carried out by completing the metal substrate front after load routing, the encapsulating mode of plastic packaging material can adopt mould encapsulating mode, spraying equipment spraying method or brush coating mode, and described plastic packaging material can adopt the epoxy resin of packing material or no-arbitrary pricing material.
Step 12, the operation of subsides photoresistance film
See Figure 12, utilize the metal substrate front and the back side that film sticking equipment completes encapsulating plastic packaging material to carry out the coating of photoresistance film, described photoresistance film can adopt wet type photoresistance film or dry type photoresistance film.
Step 13, metal substrate back side removal unit divide photoresistance film
See Figure 13, utilize exposure imaging equipment to complete the metal substrate back side of pasting photoresistance film operation in step 12 and carry out graph exposure, develop and window, to expose the follow-up graphics field needing to carry out chemical etching, the metal substrate back side.
Step 14, chemical etching
See Figure 14, the metal substrate back side in step 13 is completed the graphics field of windowing and carries out chemical etching, chemical etching until inert metal line layer and encapsulating plastic packaging material position till, etching solution can adopt copper chloride or iron chloride.
Step 15, plated metal line layer
See Figure 15, the plating of metallic circuit layer is carried out on the inert metal line layer surface of exposing after step 14 completes chemical etching, namely metallic circuit layer forms Ji Dao bottom and pin bottom at the metal substrate back side after having electroplated relatively, described metallic circuit layer can be single or multiple lift, described metallic circuit layer material adopts copper nickel gold, copper nickeline, porpezite, gold or copper etc., and described electro-plating method can be electroless plating or metallide.
Step 10 six, removal metallic substrate surfaces photoresistance film
See Figure 16, the photoresistance film of metallic substrate surfaces removed, minimizing technology adopts chemical medicinal liquid soften and adopt high pressure water jets to remove.
Step 10 seven, encapsulating
See Figure 17, step 10 six is removed the encapsulating operation that plastic packaging material is carried out at the metal substrate back side after photoresistance film, encapsulating mode can adopt mould encapsulating mode, spraying equipment spraying method or pad pasting mode, and described plastic packaging material can adopt the epoxy resin of packing material or no-arbitrary pricing material.
The surface perforate of step 10 eight, plastic packaging material
See Figure 18, carry out the follow-up perforate operation will planting Metal Ball region on the surface of step 10 seven metal substrate back side encapsulating plastic packaging material, described perforate mode can adopt dry laser to sinter or the method for wet chemistry corrosion.
Step 10 nine, cleaning
See Figure 19, clean to remove oxidation material or lipid phase etc. to step 10 eight metal substrate back side plastic packaging material tapping, can carry out the coating of coat of metal, coat of metal adopts antioxidant simultaneously.
Step 2 ten, plant ball
See Figure 20, Metal Ball is implanted into through the aperture of cleaning in step 10 nine, the back face of Metal Ball and Ji Dao or pin touches, described ball mode of planting can adopt conventional ball attachment machine or adopt metal paste printing can form orbicule again after high-temperature digestion, and the material of Metal Ball can be pure tin or ashbury metal.
Step 2 11, cutting finished product
See Figure 21, step 2 ten is completed the semi-finished product of planting ball and carry out cutting operation, make originally to integrate in array aggregate mode and contain plastic-sealed body module more than cutting of chip independent, obtain single-chip formal dress and first encapsulate the base island exposed encapsulating structure finished product of after etching.
Embodiment 2: Dan Ji island individual pen pin static release ring
The structural representation of the base island exposed encapsulating structure embodiment 2 of after etching is first encapsulated see Figure 23 (A) and Figure 23 (B), Figure 23 (A) single-chip of the present invention formal dress.The vertical view that Figure 23 (B) is Figure 23 (A).As can be seen from Figure 23 (A) and Figure 23 (B), the difference of embodiment 2 and embodiment 1 is only: be provided with static release ring 10 between described base island 1 and pin 2, and described static release ring 10 front is connected by metal wire 5 with between chip 4 front.
Embodiment 3: Dan Ji island individual pen pin passive device
The structural representation of the base island exposed encapsulating structure embodiment 3 of after etching is first encapsulated see Figure 24 (A) and Figure 24 (B), Figure 24 (A) single-chip of the present invention formal dress.The vertical view that Figure 24 (B) is Figure 24 (A).As can be seen from Figure 24 (A) and Figure 24 (B), the difference of embodiment 3 and embodiment 1 is only: by conductive bond material cross-over connection passive device 11 between described pin 2 and pin 2, described passive device 11 can be connected across between pin 2 front and pin 2 front, also can be connected across between pin 2 back side and pin 2 back side.
Embodiment 4: Dan Ji island individual pen pin static release ring passive device
The structural representation of the base island exposed encapsulating structure embodiment 4 of after etching is first encapsulated see Figure 25 (A) and Figure 25 (B), Figure 25 (A) single-chip of the present invention formal dress.The vertical view that Figure 25 (B) is Figure 25 (A).As can be seen from Figure 25 (A) and Figure 25 (B), the difference of embodiment 4 and embodiment 2 is only: by conductive bond material cross-over connection passive device 11 between described pin 2 and pin 2, described passive device 11 can be connected across between pin 2 front and pin 2 front, also can be connected across between pin 2 back side and pin 2 back side.
Embodiment 5: Dan Ji island multi-circle pin
The structural representation of the base island exposed encapsulating structure embodiment 5 of after etching is first encapsulated see Figure 26 (A) and Figure 26 (B), Figure 26 (A) single-chip of the present invention formal dress.The vertical view that Figure 26 (B) is Figure 26 (A).As can be seen from Figure 26 (A) and Figure 26 (B), embodiment 5 is only with the difference of embodiment 1: described pin 2 has multi-turn.
Embodiment 6: Dan Ji island multi-circle pin static release ring
The structural representation of the base island exposed encapsulating structure embodiment 6 of after etching is first encapsulated see Figure 27 (A) and Figure 27 (B), Figure 27 (A) single-chip of the present invention formal dress.The vertical view that Figure 27 (B) is Figure 27 (A).As can be seen from Figure 27 (A) and Figure 27 (B), embodiment 6 is only with the difference of embodiment 2: described pin 2 has multi-turn.
Embodiment 7: Dan Ji island multi-circle pin passive device
The structural representation of the base island exposed encapsulating structure embodiment 7 of after etching is first encapsulated see Figure 28 (A) and Figure 28 (B), Figure 28 (A) single-chip of the present invention formal dress.The vertical view that Figure 28 (B) is Figure 28 (A).As can be seen from Figure 28 (A) and Figure 28 (B), embodiment 7 is only with the difference of embodiment 3: described pin 2 has multi-turn.
Embodiment 8: Dan Ji island multi-circle pin static release ring passive device
The structural representation of the base island exposed encapsulating structure embodiment 8 of after etching is first encapsulated see Figure 29 (A) and Figure 29 (B), Figure 29 (A) single-chip of the present invention formal dress.The vertical view that Figure 29 (B) is Figure 29 (A).As can be seen from Figure 29 (A) and Figure 29 (B), embodiment 8 is only with the difference of embodiment 4: described pin 2 has multi-turn.
Embodiment 9: Duo Ji island individual pen pin
The structural representation of the base island exposed encapsulating structure embodiment 9 of rear encapsulation is first etched see Figure 30 (A) and Figure 30 (B), Figure 30 (A) single-chip of the present invention formal dress.The vertical view that Figure 30 (B) is Figure 30 (A).As can be seen from Figure 30 (A) and Figure 30 (B), embodiment 9 is only with the difference of embodiment 1: described base island 1 has multiple.
Embodiment 10: Duo Ji island individual pen pin static release ring
The structural representation of the base island exposed encapsulating structure embodiment 10 of rear encapsulation is first etched see Figure 31 (A) and Figure 31 (B), Figure 31 (A) single-chip of the present invention formal dress.The vertical view that Figure 31 (B) is Figure 31 (A).As can be seen from Figure 31 (A) and Figure 31 (B), embodiment 10 is only with the difference of embodiment 2: described base island 1 has multiple.
Embodiment 11: Duo Ji island individual pen pin passive device
The structural representation of the base island exposed encapsulating structure embodiment 11 of rear encapsulation is first etched see Figure 32 (A) and Figure 32 (B), Figure 32 (A) single-chip of the present invention formal dress.The vertical view that Figure 32 (B) is Figure 32 (A).As can be seen from Figure 32 (A) and Figure 32 (B), embodiment 11 is only with the difference of embodiment 3: described base island 1 has multiple.
Embodiment 12: Duo Ji island individual pen pin static release ring passive device
The structural representation of the base island exposed encapsulating structure embodiment 12 of rear encapsulation is first etched see Figure 33 (A) and Figure 33 (B), Figure 33 (A) single-chip of the present invention formal dress.The vertical view that Figure 33 (B) is Figure 33 (A).As can be seen from Figure 33 (A) and Figure 33 (B), embodiment 12 is only with the difference of embodiment 4: described base island 1 has multiple.
Embodiment 13: Duo Ji island multi-circle pin
The structural representation of the base island exposed encapsulating structure embodiment 13 of rear encapsulation is first etched see Figure 34 (A) and Figure 34 (B), Figure 34 (A) single-chip of the present invention formal dress.The vertical view that Figure 34 (B) is Figure 34 (A).As can be seen from Figure 34 (A) and Figure 34 (B), embodiment 13 is only with the difference of embodiment 5: described base island 1 has multiple.
Embodiment 14: Duo Ji island multi-circle pin static release ring
The structural representation of the base island exposed encapsulating structure embodiment 14 of rear encapsulation is first etched see Figure 35 (A) and Figure 35 (B), Figure 35 (A) single-chip of the present invention formal dress.The vertical view that Figure 35 (B) is Figure 35 (A).As can be seen from Figure 35 (A) and Figure 35 (B), embodiment 14 is only with the difference of embodiment 6: described base island 1 has multiple.
Embodiment 15: Duo Ji island multi-circle pin passive device
The structural representation of the base island exposed encapsulating structure embodiment 15 of rear encapsulation is first etched see Figure 36 (A) and Figure 36 (B), Figure 36 (A) single-chip of the present invention formal dress.The vertical view that Figure 36 (B) is Figure 36 (A).As can be seen from Figure 36 (A) and Figure 36 (B), embodiment 15 is only with the difference of embodiment 7: described base island 1 has multiple.
Embodiment 16: Duo Ji island multi-circle pin static release ring passive device
The structural representation of the base island exposed encapsulating structure embodiment 16 of rear encapsulation is first etched see Figure 37 (A) and Figure 37 (B), Figure 37 (A) single-chip of the present invention formal dress.The vertical view that Figure 37 (B) is Figure 37 (A).As can be seen from Figure 37 (A) and Figure 37 (B), embodiment 16 is only with the difference of embodiment 8: described base island 1 has multiple.
Claims (6)
1. single-chip formal dress first encapsulates a manufacture method for the base island exposed encapsulating structure of after etching, it is characterized in that described method comprises following processing step:
Step one, get metal substrate
Step 2, metallic substrate surfaces preplating copper material
One deck copper material film is electroplated in metallic substrate surfaces,
Step 3, the operation of subsides photoresistance film
Subsides photoresistance film equipment is utilized to carry out the coating of photoresistance film in the metal substrate front and the back side that complete preplating copper material film,
Step 4, metal substrate front removal unit divide photoresistance film
Utilize exposure imaging equipment to complete the metal substrate front of pasting photoresistance film operation in step 3 to carry out graph exposure, develop and window, to expose the graphics field that the follow-up needs in metal substrate front carry out electroplating,
Step 5, plating inert metal line layer
The metal substrate back side is completed the upper inert metal line layer of graphics field plating of windowing,
Step 6, plated metal line layer
Metallic circuit layer on inert metal line layer plated surface in step 5, namely described metallic circuit layer forms Ji Dao top and pin top at metal substrate vis-a-vis after having electroplated,
Step 7, removal metallic substrate surfaces photoresistance film
The photoresistance film of metallic substrate surfaces is removed,
Step 8, coating bonding material
At the base island top front face coated with conductive that step 6 is formed relatively or nonconducting bonding material,
Step 9, load
The conduction or non-conductive bonding material of the coating of step 8 Ji Dao top are carried out the implantation of chip,
Step 10, wire bond
The operation of bond wire line is carried out between chip front side and pin front,
Step 11, encapsulating
The operation of encapsulating plastic packaging material is carried out by completing the metal substrate front after load routing,
Step 12, the operation of subsides photoresistance film
The metal substrate front and the back side that subsides photoresistance film equipment completes encapsulating plastic packaging material is utilized to carry out the coating of photoresistance film,
Step 13, metal substrate back side removal unit divide photoresistance film
Carry out graph exposure, develop and window in the metal substrate back side utilizing exposure imaging equipment to complete pad pasting operation in step 12, to expose the follow-up graphics field needing to carry out chemical etching, the metal substrate back side,
Step 14, chemical etching
The metal substrate back side in step 13 is completed the graphics field of windowing and carries out chemical etching,
Step 15, plated metal line layer
The plating of metallic circuit layer is carried out on the inert metal line layer surface of exposing after step 14 completes chemical etching, and namely metallic circuit layer forms Ji Dao bottom and pin bottom at the metal substrate back side after having electroplated relatively,
Step 10 six, removal metallic substrate surfaces photoresistance film
The photoresistance film of metallic substrate surfaces is removed,
Step 10 seven, encapsulating
Step 10 six is removed the encapsulating operation that plastic packaging material is carried out at the metal substrate back side after photoresistance film,
The surface perforate of step 10 eight, plastic packaging material
The follow-up perforate operation will planting Metal Ball region is carried out on the surface of step 10 seven metal substrate back side encapsulating plastic packaging material,
Step 10 nine, cleaning
Step 10 eight metal substrate back side plastic packaging material tapping is cleaned,
Step 2 ten, plant ball
Metal Ball is implanted into through the aperture of cleaning in step 10 nine,
Step 2 11, cutting finished product
Step 2 ten is completed the semi-finished product of planting ball and carry out cutting operation, make originally to integrate in array aggregate mode and contain plastic-sealed body module more than cutting of chip independent, obtain single-chip formal dress and first encapsulate the base island exposed encapsulating structure finished product of after etching.
2. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island exposed encapsulating structure of after etching, it is characterized in that: between described Ji Dao (1) and pin (2), be provided with static release ring (10), be connected by metal wire (5) between described static release ring (10) front with chip (4) front.
3. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island exposed encapsulating structure of after etching, it is characterized in that: cross-over connection passive device (11) between described pin (2) and pin (2), described passive device (11) is connected across between pin (2) front and pin (2) front or is connected across between pin (2) back side and pin (2) back side.
4. first encapsulate the manufacture method of the base island exposed encapsulating structure of after etching according to a kind of single-chip formal dress of claim 1 ~ 3 described in one of them, it is characterized in that: described pin (2) has multi-turn.
5. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island exposed encapsulating structure of after etching, it is characterized in that: described step 10 nine pairs of metal substrate back side plastic packaging material tappings clean carry out simultaneously coat of metal be coated to.
6. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island exposed encapsulating structure of after etching, it is characterized in that: described Ji Dao (1) has multiple.
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| TW200845246A (en) * | 2007-05-09 | 2008-11-16 | Kinsus Interconnect Tech Corp | High-density fine line package structure and method for fabricating the same |
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| CN102403283A (en) * | 2011-11-25 | 2012-04-04 | 江苏长电科技股份有限公司 | Ball grid array packaging structure with basic islands and manufacturing method thereof |
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| TW200845246A (en) * | 2007-05-09 | 2008-11-16 | Kinsus Interconnect Tech Corp | High-density fine line package structure and method for fabricating the same |
| CN101958300A (en) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | Double-sided graphic chip inversion module packaging structure and packaging method thereof |
| CN102403283A (en) * | 2011-11-25 | 2012-04-04 | 江苏长电科技股份有限公司 | Ball grid array packaging structure with basic islands and manufacturing method thereof |
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