CN102856283B - First packaged and then etched packaging structure with single chip normally installed and base islands buried and preparation method of structure - Google Patents
First packaged and then etched packaging structure with single chip normally installed and base islands buried and preparation method of structure Download PDFInfo
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- CN102856283B CN102856283B CN201210140777.9A CN201210140777A CN102856283B CN 102856283 B CN102856283 B CN 102856283B CN 201210140777 A CN201210140777 A CN 201210140777A CN 102856283 B CN102856283 B CN 102856283B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention relates to a first packaged and then etched packaging structure with a single chip normally installed and base islands buried and a preparation method of the structure. The structure comprises base islands (1) and pins (2), wherein a chip (4) is arranged on the fronts of the base islands (1); the front face of the chip (4) and the front faces of the pins (2) are connected by metal wires (5); plastic package materials (6) are arranged in the surrounding regions of the base islands (1) and the pins (2) and outside the chip (4) and the metal wires (5); small holes (7) are formed on the surfaces of the plastic package materials (6) on the lower parts of the pins (2); the small holes (7) are communicated with the backs of the pins (2); metal balls (9) are arranged in the small holes (7); and the metal balls (9) are contacted with the backs of the pins (2). The packaging structure and the preparation method have the following beneficial effects that the preparation cost is reduced; the safety and reliability of the packaging body are improved; environmental pollution is reduced; and design and preparation of high-density circuits are truly achieved.
Description
Technical field
The present invention relates to a kind of single-chip formal dress and first encapsulate the base island embedded encapsulating structure of after etching and manufacture method thereof.Belong to technical field of semiconductor encapsulation.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step one, see Figure 38, get the substrate that a glass fiber material is made,
Step 2, see Figure 39, perforate on desired position on glass fibre basal plate,
Step 3, see Figure 40, at back side coating one deck Copper Foil of glass fibre basal plate,
Step 4, see Figure 41, glass fibre basal plate punching position insert conductive materials,
Step 5, see Figure 42, at front coating one deck Copper Foil of glass fibre basal plate,
Step 6, see Figure 43, in glass fibre basal plate covering surface photoresistance film,
Step 7, see Figure 44, the position that photoresistance film is needing is carried out exposure imaging and is windowed,
Step 8, see Figure 45, to etch completing the part of windowing,
Step 9, see Figure 46, the photoresistance film of substrate surface to be divested,
Step 10, see Figure 47, carry out the coating of solder mask (being commonly called as green paint) on the surface of copper foil circuit layer,
Step 11, see Figure 48, after solder mask needs to carry out, window in the load of operation and the region of routing bonding,
Step 12, see Figure 49, the region of carrying out windowing in step 11 is electroplated, and relatively forms Ji Dao and pin,
Step 13, complete the concerned process steps such as follow-up load, routing, encapsulating, cutting.
Above-mentioned conventional high-density substrate encapsulation structure has the following disadvantages and defect:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must glass fibre be used, so just many thickness space of layer of glass thickness about 100 ~ 150 μm;
3, glass fibre inherently a kind of foaming substance, so easily because the time of placing and environment suck moisture and moisture, directly have influence on security capabilities or the reliability step of reliability;
4, fiberglass surfacing has been coated to the Copper Foil metal layer thickness of one deck about 50 ~ 100 μm, and the etching distance of metal level circuit and circuit is also because the characteristic of etching factor can only accomplish the etched gap (etching factor: the ability preferably manufactured is that etched gap is about equal to by the thickness etching object of 50 ~ 100 μm, see Figure 50), so the design and manufaction accomplishing high-density line that cannot be real;
5, because must use Copper Foil metal level, and Copper Foil metal level is the mode of employing high pressure stickup, so the thickness of Copper Foil is difficult to the thickness lower than 50 μm, otherwise is just difficult to operation as out-of-flatness or Copper Foil breakage or Copper Foil extension displacement etc.;
6, also because whole baseplate material be adopt glass fiber material, so significantly increase the thickness 100 ~ 150 μm of glass layer, cannot be real accomplish ultra-thin encapsulation;
7, conventional fiber glass sticks on the technology of Copper Foil because material property difference very large (coefficient of expansion), in the operation of adverse circumstances, easily cause stress deformation, directly has influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of single-chip formal dress is provided first to encapsulate base island embedded encapsulating structure of after etching and preparation method thereof, its technique is simple, do not need to use glass layer, decrease cost of manufacture, improve the safety and reliability of packaging body, decrease the environmental pollution that glass fiber material brings, and the employing of metal substrate line layer is electro-plating method, really can accomplish the Design and manufacture of high-density line.
The object of the present invention is achieved like this: a kind of single-chip formal dress first encapsulates the base island embedded encapsulating structure of after etching, it comprises Ji Dao and pin, described Ji Dao front is provided with chip by conduction or non-conductive bonding material, be connected with metal wire between described chip front side with pin front, the region of periphery, described base island, region between Ji Dao and pin, region between pin and pin, the region on Ji Dao and pin top, the region of Ji Dao and pin bottom and chip and metal wire are all encapsulated with plastic packaging material outward, the plastic packaging material at the described pin back side offers aperture, described aperture is connected with the pin back side, Metal Ball is provided with in described aperture, described Metal Ball and pin back face touch.
Single-chip formal dress first encapsulates a manufacture method for the base island embedded encapsulating structure of after etching, said method comprising the steps of:
Step one, get metal substrate
Step 2, metallic substrate surfaces copper pre-plating
Step 3, the operation of subsides photoresistance film
The photoresistance film can carrying out exposure imaging is sticked respectively in the front of metal substrate and the back side that complete preplating copper material film;
Step 4, metal substrate front removal unit divide photoresistance film
The metal substrate front utilizing exposure imaging equipment step 3 to be completed the operation of subsides photoresistance film is carried out graph exposure, development and removal unit and is divided figure photoresistance film, to expose the regional graphics that the follow-up needs in metal substrate front carry out electroplating;
Step 5, plating inert metal line layer
Inert metal line layer in plating in the region that metal substrate front removal unit divides photoresistance film in step 4;
Step 6, plated metal line layer
Inert metal surface in step 5 plates multilayer or single-layer metal line layer, and namely metallic circuit layer forms corresponding Ji Dao top and pin top after having electroplated on metallic substrates;
Step 7, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 8, coating bonding material
At base island top front face coated with conductive or nonconducting bonding material of step 6 formation;
Step 9, load
Chip is implanted on the Ji Dao top of step 8;
Step 10, routing
The operation of bond wire line is carried out between chip front side and pin front;
Step 11, encapsulating
Plastic packaging material is adopted to carry out plastic packaging in the metal substrate front in step 10;
Step 12, the operation of subsides photoresistance film
The photoresistance film can carrying out exposure imaging is sticked respectively in the front of metal substrate and the back side that complete plastic packaging work;
Step 13, metal substrate back side removal unit divide photoresistance film
The metal substrate back side utilizing exposure imaging equipment step 12 to be completed the operation of subsides photoresistance film is carried out graph exposure, development and removal unit and is divided figure photoresistance film, to expose the follow-up regional graphics needing to carry out chemical etching in the metal substrate back side;
Step 14, chemical etching
Chemical etching is carried out in the region that the metal substrate back side in step 13 completes exposure imaging;
Step 15, plated metal line layer
Multilayer or single-layer metal line layer on inert metal line layer plated surface, namely form corresponding Ji Dao bottom and pin bottom after metal plating completes on metallic substrates;
Step 10 six, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10 seven, encapsulating
Plastic packaging material is adopted to carry out plastic packaging at the metal substrate back side in step 10 six;
The surface perforate of step 10 eight, plastic packaging material
The surface of encapsulating plastic packaging material at the metal substrate back side in advance carries out needing follow-up region of planting Metal Ball to carry out perforate, specifically carries out perforate at the pin back side;
Step 10 nine, cleaning
Carry out the cleaning of oxidation material, lipid phase at metal substrate back side plastic packaging material tapping, the coating of coat of metal can be carried out simultaneously;
Step 2 ten, plant ball
At the metal substrate back side, plastic-sealed body tapping is implanted into Metal Ball, and the back face of Metal Ball and pin is touched;
Step 2 11, cutting finished product
Step 2 ten is completed the semi-finished product of planting ball and carry out cutting operation, make originally to integrate in array aggregate mode and the plastic-sealed body module more than contain chip is cut independent, obtained single-chip formal dress first encapsulates the base island embedded encapsulating structure of after etching, can adopt conventional diamond blade and the cutting equipment of routine.
In described step 10 nine to metal substrate back side plastic packaging material tapping clean carry out simultaneously coat of metal be coated to.
Be provided with static release ring between described Ji Dao and pin, described static release ring front is connected by metal wire with between chip front side.
Between described pin and pin, cross-over connection has passive device, and described passive device is connected across between pin front and pin front or is connected across between the pin back side and the pin back side.
Described pin has multi-turn.
Described Ji Dao comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and described Ji Dao top and Ji Dao bottom form by single or multiple lift metal plating, and described intermediate barrier layers is nickel dam or titanium layer or layers of copper.
Described pin comprises pin top, pin bottom and intermediate barrier layers, and described pin top and pin bottom form by single or multiple lift metal plating, and described intermediate barrier layers is nickel dam or titanium layer or layers of copper.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention does not need to use glass layer, so can reduce the cost that glass layer brings;
2, the present invention does not need the foaming substance using glass layer, so the grade of reliability can improve again, relatively will improve the fail safe of packaging body;
3, the present invention does not use glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4, two-dimensional metallic substrate circuit layer of the present invention adopted is electro-plating method, and the gross thickness of electrodeposited coating is about 10 ~ 15 μm, and the gap between circuit and circuit can reach the gap of less than 25 μm easily, so the technical capability of pin connection tiling in high density can be accomplished veritably;
5, two-dimensional metallic substrate of the present invention is metal level galvanoplastic because of what adopt, so come simple than the technique of glass fibre high pressure Copper Foil metal level, and do not have metal level because high pressure produces the damaged and metal level of metal level out-of-flatness, metal level and to extend the bad of displacement or puzzled;
6, two-dimensional metallic substrate circuit layer of the present invention carries out metal plating on the surface of metal base, so material characteristic is substantially identical, so coating circuit is substantially identical with the internal stress of metal base, the rear engineering (the surface mount work as high temperature eutectic load, high temperature tin material solder load and high temperature passive device) of adverse circumstances can be carried out easily and be not easy to produce stress deformation.
Accompanying drawing explanation
Fig. 1 ~ Figure 21 is each operation schematic diagram that single-chip formal dress of the present invention first encapsulates after etching base island embedded encapsulating structure embodiment 1 manufacture method.
Figure 22 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 1 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 22 (B) is Figure 22 (A).
Figure 23 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 2 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 23 (B) is Figure 23 (A).
Figure 24 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 3 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 24 (B) is Figure 24 (A).
Figure 25 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 4 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 25 (B) is Figure 25 (A).
Figure 26 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 5 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 26 (B) is Figure 26 (A).
Figure 27 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 6 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 27 (B) is Figure 27 (A).
Figure 28 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 7 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 28 (B) is Figure 28 (A).
Figure 29 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 8 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 29 (B) is Figure 29 (A).
Figure 30 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 9 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 30 (B) is Figure 30 (A).
Figure 31 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 31 (B) is Figure 31 (A).
Figure 32 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 32 (B) is Figure 32 (A).
Figure 33 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 33 (B) is Figure 33 (A).
Figure 34 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 34 (B) is Figure 34 (A).
Figure 35 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 35 (B) is Figure 35 (A).
Figure 36 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 36 (B) is Figure 36 (A).
Figure 37 (A) first encapsulates the structural representation of the base island embedded encapsulating structure embodiment 10 of after etching for single-chip formal dress of the present invention.
The vertical view that Figure 37 (B) is Figure 37 (A).
Figure 38 ~ Figure 49 is the manufacturing process flow diagram of traditional high-density base board encapsulating structure.
Figure 50 is the etching situation schematic diagram of fiberglass surfacing Copper Foil metal level.
Wherein:
Base island 1
Pin 2
Conduction or non-conductive bonding material 3
Chip 4
Metal wire 5
Plastic packaging material 6
Aperture 7
Coat of metal 8
Metal Ball 9
Static release ring 10
Passive device 11
Metal substrate 12
Copper material film 13
Photoresistance film 14
Inert metal line layer 15
Metallic circuit layer 16.
Embodiment
A kind of single-chip of the present invention formal dress first encapsulate the base island embedded encapsulating structure of after etching and manufacture method as follows:
Embodiment one: Dan Ji island individual pen pin
The structural representation of the base island embedded encapsulating structure embodiment 1 of after etching is first encapsulated see Figure 22 (A) and Figure 22 (B), Figure 22 (A) single-chip of the present invention formal dress.The vertical view that Figure 22 (B) is Figure 22 (A).As can be seen from Figure 22 (A) and Figure 22 (B), single-chip formal dress of the present invention first encapsulates the base island embedded encapsulating structure of after etching, it comprises base island 1 and pin 2, front, described base island 1 is provided with chip 4 by conduction or non-conductive bonding material 3, described chip 4 front is connected with metal wire 5 with between pin 2 front, the region of periphery, described base island 1, region between base island 1 and pin 2, region between pin 2 and pin 2, the region on base island 1 and pin 2 top, the region of base island 1 and pin 2 bottom and chip 4 and metal wire 5 is outer is all encapsulated with plastic packaging material 6, the plastic packaging material 6 at described pin 2 back side offers aperture 7, described aperture 7 is connected with pin 2 back side, Metal Ball 9 is provided with in described aperture 7, coat of metal 8 is provided with between described Metal Ball 9 and pin 2 back side, described Metal Ball 9 adopts tin or tin alloy material, described base island 1 is by Ji Dao top, intermediate barrier layers and Ji Dao bottom composition, Ji Dao top and Ji Dao bottom form by single or multiple lift metal plating, intermediate barrier layers is nickel dam, described pin 2 is by pin top, intermediate barrier layers and pin bottom composition, pin top and pin bottom form by single or multiple lift metal plating.
Its manufacture method is as follows:
Step one, get metal substrate
See Fig. 1, get the metal substrate that a slice thickness is suitable, the material of metal substrate can convert according to the function of chip and characteristic, such as: copper material, iron material, ferronickel material, zinc-iron material etc.
Step 2, metallic substrate surfaces copper pre-plating
See Fig. 2, plate one deck copper material film in metallic substrate surfaces, object is for basis is done in follow-up plating.(mode of plating can adopt chemical plating or metallide).
Step 3, the operation of subsides photoresistance film
See Fig. 3, stick in the front of metal substrate and the back side completing preplating copper material film the photoresistance film can carrying out exposure imaging respectively, to protect follow-up electroplated metal layer process operation, photoresistance film can be dry type photoresistance film also can be wet type photoresistance film.
Step 4, metal substrate front removal unit divide photoresistance film
See Fig. 4, the metal substrate front utilizing exposure imaging equipment step 3 to be completed the operation of subsides photoresistance film is carried out graph exposure, development and removal unit and is divided figure photoresistance film, to expose the regional graphics that the follow-up needs in metal substrate front carry out electroplating.
Step 5, plating inert metal line layer
See Fig. 5, inert metal line layer in plating in the region that metal substrate front removal unit divides photoresistance film in step 4, as the barrier layer of subsequent etch work, inert metal can adopt nickel material or titanium material or copper material, and plating mode can make chemical plating or metallide mode.
Step 6, plated metal line layer
See Fig. 6, multilayer or single-layer metal line layer on inert metal line layer plated surface in step 5, namely metallic circuit layer forms corresponding Ji Dao top and pin top after having electroplated on metallic substrates, described metallic circuit layer can adopt in silver, aluminium, copper, nickel gold and NiPdAu one or more, the mode of plating mode can be electroless plating also can be metallide.
Step 7, removal photoresistance film
See Fig. 7, remove the photoresistance film of metallic substrate surfaces, employing chemical medicinal liquid softens and the mode adopting high pressure water jets to remove removes photoresistance film.
Step 8, coating bonding material
See Fig. 8, at base island top front face coated with conductive or nonconducting bonding material of step 6 formation, object is the joint for follow-up implanted chip Hou Yuji island.
Step 9, load
See Fig. 9, implant chip on the Ji Dao top of step 8.
Step 10, wire bond
See Figure 10, carry out the operation of bond wire line between chip front side and pin front, it also can be banded that the material of described metal wire adopts the material of gold, silver, copper, aluminium or alloy, shape wiry can be thread.
Step 11, encapsulating
See Figure 11, adopt plastic packaging material to carry out plastic packaging in the metal substrate front in step 10, plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method or use pad pasting mode.Described plastic packaging material can adopt the epoxy resin of packing material or no-arbitrary pricing material.
Step 12, the operation of subsides photoresistance film
See Figure 12, stick in the front of metal substrate and the back side completing plastic packaging work the photoresistance film can carrying out exposure imaging respectively, photoresistance film can be dry type photoresistance film also can be wet type photoresistance film.
Step 13, metal substrate back side removal unit divide photoresistance film
See Figure 13, the metal substrate back side utilizing exposure imaging equipment step 12 to be completed the operation of subsides photoresistance film is carried out graph exposure, development and removal unit and is divided figure photoresistance film, to expose the follow-up regional graphics needing to carry out chemical etching in metal substrate front.
Step 14, chemical etching
See Figure 14, chemical etching is carried out in the region that the metal substrate back side in step 13 completes exposure imaging, and chemical etching is till inert metal line layer, and etching solution can adopt copper chloride or iron chloride.
Step 15, plated metal line layer
See Figure 15, multilayer or single-layer metal line layer is plated in inert metal surface, namely corresponding Ji Dao bottom and pin bottom is formed on metallic substrates after metal plating completes, coating kind can be copper nickel gold, copper nickeline, porpezite, gold or copper etc., and electro-plating method can be electroless plating or metallide.
Step 10 six, removal photoresistance film
See Figure 16, remove the photoresistance film of metallic substrate surfaces, employing chemical medicinal liquid softens and the mode adopting high pressure water jets to remove removes photoresistance film.
Step 10 seven, encapsulating
See Figure 17, adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 10 six, plastic packaging mode can adopt the spraying method of mould encapsulating mode, spraying equipment or use pad pasting mode.Described plastic packaging material can adopt the epoxy resin of packing material or no-arbitrary pricing material.
The surface perforate of step 10 eight, plastic packaging material
See Figure 18, the surface of encapsulating plastic packaging material at the metal substrate back side in advance carries out needing follow-up region of planting Metal Ball to carry out perforate, specifically carries out perforate at the pin back side, and the method for dry laser sintering or wet chemistry corrosion can be adopted to carry out perforate.
Step 10 nine, cleaning
See Figure 19, carry out the cleaning of oxidation material, lipid phase at metal substrate back side plastic packaging material tapping, can carry out the coating of coat of metal, coat of metal adopts oxidation-resistant material simultaneously.
Step 2 ten, plant ball
See Figure 20, at the metal substrate back side, plastic-sealed body tapping is implanted into Metal Ball, the back face of Metal Ball and pin is touched, and can adopt conventional ball attachment machine or adopt metal paste printing can form orbicule again after high-temperature digestion, the material of Metal Ball can be pure tin or ashbury metal.
Step 2 11, cutting finished product
See Figure 21, step 2 ten is completed the semi-finished product of planting ball and carry out cutting operation, make originally to integrate in array aggregate mode and the plastic-sealed body module more than contain chip is cut independent, obtained single-chip formal dress first encapsulates the base island embedded encapsulating structure of after etching, can adopt conventional diamond blade and the cutting equipment of routine.
The structural representation of the base island embedded encapsulating structure embodiment 2 of after etching is first encapsulated see Figure 23 (A) and Figure 23 (B), Figure 23 (A) single-chip of the present invention formal dress.The vertical view that Figure 23 (B) is Figure 23 (A).As can be seen from Figure 23 (A) and Figure 23 (B), the difference of embodiment 2 and embodiment 1 is only: be provided with static release ring 10 between described base island 1 and pin 2, and described static release ring 10 front is connected by metal wire 5 with between chip 4 front.
Embodiment 3: Dan Ji island individual pen pin passive device
The structural representation of the base island embedded encapsulating structure embodiment 3 of after etching is first encapsulated see Figure 24 (A) and Figure 24 (B), Figure 24 (A) single-chip of the present invention formal dress.The vertical view that Figure 24 (B) is Figure 24 (A).As can be seen from Figure 24 (A) and Figure 24 (B), the difference of embodiment 3 and embodiment 1 is only: by conductive bond material cross-over connection passive device 11 between described pin 2 and pin 2, described passive device 11 can be connected across between pin 2 front and pin 2 front, also can be connected across between pin 2 back side and pin 2 back side.
Embodiment 4: Dan Ji island individual pen pin static release ring passive device
The structural representation of the base island embedded encapsulating structure embodiment 4 of after etching is first encapsulated see Figure 25 (A) and Figure 25 (B), Figure 25 (A) single-chip of the present invention formal dress.The vertical view that Figure 25 (B) is Figure 25 (A).As can be seen from Figure 25 (A) and Figure 25 (B), the difference of embodiment 4 and embodiment 2 is only: by conductive bond material cross-over connection passive device 11 between described pin 2 and pin 2, described passive device 11 can be connected across between pin 2 front and pin 2 front, also can be connected across between pin 2 back side and pin 2 back side.
Embodiment 5: Dan Ji island multi-circle pin
The structural representation of the base island embedded encapsulating structure embodiment 5 of after etching is first encapsulated see Figure 26 (A) and Figure 26 (B), Figure 26 (A) single-chip of the present invention formal dress.The vertical view that Figure 26 (B) is Figure 26 (A).As can be seen from Figure 26 (A) and Figure 26 (B), embodiment 5 is only with the difference of embodiment 1: described pin 2 has multi-turn.
Embodiment 6: Dan Ji island multi-circle pin static release ring
The structural representation of the base island embedded encapsulating structure embodiment 6 of after etching is first encapsulated see Figure 27 (A) and Figure 27 (B), Figure 27 (A) single-chip of the present invention formal dress.The vertical view that Figure 27 (B) is Figure 27 (A).As can be seen from Figure 27 (A) and Figure 27 (B), embodiment 6 is only with the difference of embodiment 2: described pin 2 has multi-turn.
Embodiment 7: Dan Ji island multi-circle pin passive device
The structural representation of the base island embedded encapsulating structure embodiment 7 of after etching is first encapsulated see Figure 28 (A) and Figure 28 (B), Figure 28 (A) single-chip of the present invention formal dress.The vertical view that Figure 28 (B) is Figure 28 (A).As can be seen from Figure 28 (A) and Figure 28 (B), embodiment 7 is only with the difference of embodiment 3: described pin 2 has multi-turn.
Embodiment 8: Dan Ji island multi-circle pin static release ring passive device
The structural representation of the base island embedded encapsulating structure embodiment 8 of after etching is first encapsulated see Figure 29 (A) and Figure 29 (B), Figure 29 (A) single-chip of the present invention formal dress.The vertical view that Figure 29 (B) is Figure 29 (A).As can be seen from Figure 29 (A) and Figure 29 (B), embodiment 8 is only with the difference of embodiment 4: described pin 2 has multi-turn.
Embodiment 9: Duo Ji island individual pen pin
The structural representation of the base island embedded encapsulating structure embodiment 9 of after etching is first encapsulated see Figure 30 (A) and Figure 30 (B), Figure 30 (A) single-chip of the present invention formal dress.The vertical view that Figure 30 (B) is Figure 30 (A).As can be seen from Figure 30 (A) and Figure 30 (B), embodiment 9 is only with the difference of embodiment 1: described base island 1 has multiple.
Embodiment 10: Duo Ji island individual pen pin static release ring
The structural representation of the base island embedded encapsulating structure embodiment 10 of after etching is first encapsulated see Figure 31 (A) and Figure 31 (B), Figure 31 (A) single-chip of the present invention formal dress.The vertical view that Figure 31 (B) is Figure 31 (A).As can be seen from Figure 31 (A) and Figure 31 (B), embodiment 10 is only with the difference of embodiment 2: described base island 1 has multiple.
Embodiment 11: Duo Ji island individual pen pin passive device
The structural representation of the base island embedded encapsulating structure embodiment 11 of after etching is first encapsulated see Figure 32 (A) and Figure 32 (B), Figure 32 (A) single-chip of the present invention formal dress.The vertical view that Figure 32 (B) is Figure 32 (A).As can be seen from Figure 32 (A) and Figure 32 (B), embodiment 11 is only with the difference of embodiment 3: described base island 1 has multiple.
Embodiment 12: Duo Ji island individual pen pin static release ring passive device
The structural representation of the base island embedded encapsulating structure embodiment 12 of after etching is first encapsulated see Figure 33 (A) and Figure 33 (B), Figure 33 (A) single-chip of the present invention formal dress.The vertical view that Figure 33 (B) is Figure 33 (A).As can be seen from Figure 33 (A) and Figure 33 (B), embodiment 12 is only with the difference of embodiment 4: described base island 1 has multiple.
Embodiment 13: Duo Ji island multi-circle pin
The structural representation of the base island embedded encapsulating structure embodiment 13 of after etching is first encapsulated see Figure 34 (A) and Figure 34 (B), Figure 34 (A) single-chip of the present invention formal dress.The vertical view that Figure 34 (B) is Figure 34 (A).As can be seen from Figure 34 (A) and Figure 34 (B), embodiment 13 is only with the difference of embodiment 5: described base island 1 has multiple.
Embodiment 14: Duo Ji island multi-circle pin static release ring
The structural representation of the base island embedded encapsulating structure embodiment 14 of after etching is first encapsulated see Figure 35 (A) and Figure 35 (B), Figure 35 (A) single-chip of the present invention formal dress.The vertical view that Figure 35 (B) is Figure 35 (A).As can be seen from Figure 35 (A) and Figure 35 (B), embodiment 14 is only with the difference of embodiment 6: described base island 1 has multiple.
Embodiment 15: Duo Ji island multi-circle pin passive device
The structural representation of the base island embedded encapsulating structure embodiment 15 of after etching is first encapsulated see Figure 36 (A) and Figure 36 (B), Figure 36 (A) single-chip of the present invention formal dress.The vertical view that Figure 36 (B) is Figure 36 (A).As can be seen from Figure 36 (A) and Figure 36 (B), embodiment 15 is only with the difference of embodiment 7: described base island 1 has multiple.
Embodiment 16: Duo Ji island multi-circle pin static release ring passive device
The structural representation of the base island embedded encapsulating structure embodiment 16 of after etching is first encapsulated see Figure 37 (A) and Figure 37 (B), Figure 37 (A) single-chip of the present invention formal dress.The vertical view that Figure 37 (B) is Figure 37 (A).As can be seen from Figure 37 (A) and Figure 37 (B), embodiment 16 is only with the difference of embodiment 8: described base island 1 has multiple.
Claims (6)
1. single-chip formal dress first encapsulates a manufacture method for the base island embedded encapsulating structure of after etching, said method comprising the steps of:
Step one, get metal substrate
Step 2, metallic substrate surfaces copper pre-plating
Step 3, the operation of subsides photoresistance film
The photoresistance film can carrying out exposure imaging is sticked respectively in the front of metal substrate and the back side that complete preplating copper material film;
Step 4, metal substrate front removal unit divide photoresistance film
The metal substrate front utilizing exposure imaging equipment step 3 to be completed the operation of subsides photoresistance film is carried out graph exposure, development and removal unit and is divided figure photoresistance film, to expose the regional graphics that the follow-up needs in metal substrate front carry out electroplating;
Step 5, plating inert metal line layer
Inert metal line layer in plating in the region that metal substrate front removal unit divides photoresistance film in step 4;
Step 6, plated metal line layer
Multilayer or single-layer metal line layer on inert metal line layer plated surface in step 5, namely metallic circuit layer forms corresponding Ji Dao top and pin top after having electroplated on metallic substrates;
Step 7, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 8, coating bonding material
At base island top front face coated with conductive or nonconducting bonding material of step 6 formation;
Step 9, load
Chip is implanted on the Ji Dao top of step 8;
Step 10, routing
The operation of bond wire line is carried out between chip front side and pin front;
Step 11, encapsulating
Plastic packaging material is adopted to carry out plastic packaging in the metal substrate front in step 10;
Step 12, the operation of subsides photoresistance film
The photoresistance film can carrying out exposure imaging is sticked respectively in the front of metal substrate and the back side that complete plastic packaging work;
Step 13, metal substrate back side removal unit divide photoresistance film
The metal substrate back side utilizing exposure imaging equipment step 12 to be completed the operation of subsides photoresistance film is carried out graph exposure, development and removal unit and is divided figure photoresistance film, to expose the follow-up regional graphics needing to carry out chemical etching in the metal substrate back side;
Step 14, chemical etching
Chemical etching is carried out in the region that the metal substrate back side in step 13 completes exposure imaging;
Step 15, plated metal line layer
Plate multilayer or single-layer metal line layer in inert metal surface, after metal plating completes, namely form corresponding Ji Dao bottom and pin bottom on metallic substrates;
Step 10 six, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10 seven, encapsulating
Plastic packaging material is adopted to carry out plastic packaging at the metal substrate back side in step 10 six;
The surface perforate of step 10 eight, plastic packaging material
The surface of encapsulating plastic packaging material at the metal substrate back side in advance carries out needing follow-up region of planting Metal Ball to carry out perforate, specifically carries out perforate at the pin back side;
Step 10 nine, cleaning
Carry out the cleaning of oxidation material, lipid phase at metal substrate back side plastic packaging material tapping, the coating of coat of metal can be carried out simultaneously;
Step 2 ten, plant ball
At the metal substrate back side, plastic-sealed body tapping is implanted into Metal Ball, and the back face of Metal Ball and pin is touched;
Step 2 11, cutting finished product
Step 2 ten is completed the semi-finished product of planting ball and carry out cutting operation, make originally to integrate in array aggregate mode and contain plastic-sealed body module more than cutting of chip independent, obtain single-chip formal dress and first encapsulate the base island embedded encapsulating structure of after etching.
2. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island embedded encapsulating structure of after etching, it is characterized in that: between described Ji Dao (1) and pin (2), be provided with static release ring (10), be connected by metal wire (5) between described static release ring (10) front with chip (4) front.
3. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island embedded encapsulating structure of after etching, it is characterized in that: between described pin (2) and pin (2), cross-over connection has passive device (11), described passive device (11) is connected across between pin (2) front and pin (2) front or is connected across between pin (2) back side and pin (2) back side.
4. first encapsulate the manufacture method of the base island embedded encapsulating structure of after etching according to a kind of single-chip formal dress of claim 1 ~ 3 described in one of them, it is characterized in that: described pin (2) has multi-turn.
5. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island embedded encapsulating structure of after etching, it is characterized in that: described step 10 nine pairs of metal substrate back side plastic packaging material tappings clean carry out simultaneously coat of metal be coated to.
6. a kind of single-chip formal dress according to claim 1 first encapsulates the manufacture method of the base island embedded encapsulating structure of after etching, it is characterized in that: described Ji Dao (1) has multiple.
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| TW200845246A (en) * | 2007-05-09 | 2008-11-16 | Kinsus Interconnect Tech Corp | High-density fine line package structure and method for fabricating the same |
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| TW200845246A (en) * | 2007-05-09 | 2008-11-16 | Kinsus Interconnect Tech Corp | High-density fine line package structure and method for fabricating the same |
| CN101958300A (en) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | Double-sided graphic chip inversion module packaging structure and packaging method thereof |
| CN102403283A (en) * | 2011-11-25 | 2012-04-04 | 江苏长电科技股份有限公司 | Ball grid array packaging structure with basic islands and manufacturing method thereof |
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