TW200845246A - High-density fine line package structure and method for fabricating the same - Google Patents

High-density fine line package structure and method for fabricating the same Download PDF

Info

Publication number
TW200845246A
TW200845246A TW96116544A TW96116544A TW200845246A TW 200845246 A TW200845246 A TW 200845246A TW 96116544 A TW96116544 A TW 96116544A TW 96116544 A TW96116544 A TW 96116544A TW 200845246 A TW200845246 A TW 200845246A
Authority
TW
Taiwan
Prior art keywords
layer
ultra
fine
semiconductor element
density
Prior art date
Application number
TW96116544A
Other languages
Chinese (zh)
Inventor
Qian-Wei Zhang
ding-hao Lin
Original Assignee
Kinsus Interconnect Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kinsus Interconnect Tech Corp filed Critical Kinsus Interconnect Tech Corp
Priority to TW96116544A priority Critical patent/TW200845246A/en
Publication of TW200845246A publication Critical patent/TW200845246A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

A high-density fine line package structure of the present invention mainly comprises two boards with the similar structure; and a dielectric colloid film for combining the two boards. The semiconductor devices in the two boards are opposite to each other after they are assembled together. Each of the two boards is formed by an ultra-fine line, an insulation layer on a surface the same as that of the ultra-fine line, and a semiconductor device set above the ultra-fine line. Regarding the ultra-fine lines of each of the two boards, the part not covered by a solder mask can be used as the connection pads filled with solder balls or electrically coupled to the other semiconductor device through solders. The method of the present invention is mainly characterized in utilizing the electro plating instead of etching to form the above-mentioned ultra-fine lines, and removing the carriers or metal isolation layers for forming the ultra-fine lines during or at the end of the fabrication, so as to increase available layout space and fulfill the purpose of high-density.

Description

200845246 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種封裝結構的製造方法，尤指高密度細線構裝結 構及其製造方法。 【先前技術】 未來1C產業-個主要的挑戰，是如何運用適當的成本，有效組裝 各式功能在-個有限的封裝形式t，並使不同功能的晶粒達到最 佳化的表現。細’在數位、_、記紐及絲麵等領域的 應用中，不同功能的電子電路隨著在需要製程技術scaling下， έ產生不同的需求及絲。因此在單—晶粒上整合不同的功能並 不適S達成敢佳化的解決方案。隨著s〇c、Sip、Pip % (冰呢6 in Package)、P〇P (package—on—package)，以及堆疊 CSP技術的快速發展，可以預估未來數年最有效能的系統晶片，應 疋在-個封裝巾，充分利好維空間，整合使用異質性技術及不 同電壓操作環境的各種功能不同的晶粒。 具體來說，上述系統級封裝（System-in-Package, SiP)是在一 個封裝中，組裝不同ic種類的晶粒。基於Sip可延伸出一種新技 術’其可以讓多片晶粒堆疊在一個封裝模組中，並運用第三度空 間來達成更多功能或更高密度的整合。在這類封裝結構中，首先 200845246 被推出的是堆疊CSP，其產品均為memory combo，它可以在一個 BGA封裝中堆疊六層的記憶體晶粒。在這裡面，除了傳統的打線焊 接(wire bonding)，也可使用 solder bumps 或覆晶（flip-chip) 技術，而加入中介層（interposers)以利於堆疊，或散熱亦逐漸被 採用。 舉例來說’一個堆疊晶粒的封裝中會包含分開但互相用導線連結 的晶粒組成（die as building block)，可能包含一顆到數顆記 憶體晶粒的堆疊、一顆類比晶粒堆疊在另一顆soc或是數位晶粒 上，另有一顆獨立的RF晶粒位於一個多層相連結基板 (interconnected substrate)之上，而這些組成晶粒都有不同的 控制及I/O (Input/Output)路徑。此外，若在此堆疊晶粒中含記 憶體，則控制軟體會可寫入非揮發型記憶體(NVM : N〇n—v〇latile Memory) 〇 然而，在傳統超細線路技術無法再突破的緣故，而導致在製作如 " 以上所述更為複雜的封裝結構時，其整體的封裝體積仍難以大幅 縮小，無法符合電子裝置日趨短小輕薄的要求。 傳統在增層材料(Build up material)上如玻纖加強樹脂材料 (prepreg)增層法中製作5〇微米線距細線路，使用丨· 5〜& 〇⑽薄 銅皮，利用此銅皮做為電鍍(pattern plating)之導電層，最後再 使用快速侧（flash etching)咬餘h 5〜5· 〇um的底轉度。此法 因薄銅皮需要粗糙的表面與玻纖加強樹脂材料結合，需要存在一 6 200845246 定程度的粗链表面結構，但此結構會造成快速餘刻時必須加強咬 钱洙度’而造成電鑛之後的線寬損失，基於底銅的厚度，咬钱量 無法再減少’無法製作50微米間距以下的更細線距的高密度載板。 一般在封裝載板的超細線路層上電鍍鎳金時，為了將電鍍時所需 的電流傳入載板，尤其是欲電鍍的超細線路層，必須透過相連接 於超細線路層之導電線傳入，雖然此種做法可以將超細線路層完 全地用電鍍鎳金層包覆住，但是導電線在完成電鍍後仍會保留在 載板中，而佔用到有限的佈線空間。若欲減少導電線所佔用的佈 線空間，而將導電線的寬度作得比較窄時，會導致所電鍍出來的 電鍍鎳金層厚度不均勻，因此縮小導電線的寬度仍不是個提高佈 線密度的好辦法。 為求電性加強及減少雜訊，同時也為了提高佈線密度，目前載板 白改為播導電線之設計，但打金線區（wire bonding)仍須以電鍍 鎳金以達較佳接著性。雖打線區亦可用化學鎳金（或厚化金)製作 I但目前評比其可靠度不佳。所以，對既為無導線設計又須以電鍍 鎳金方式製作打線區塊，大都以GPP程序製作。 然而，在進行GPP程序前，由於電鑛鎳金層均是在形成防焊漆(SM) 前先形成的，故SM底下所佔電鍍鎳金層面積相對較大。由於SM 和金面之間的附著性較差，所以在對可靠度、耐熱度要求越來越 高的今天，以往的製作方式似已不足。 此外’無導電線電鍍(NPL)製程方法除了流程相當繁複外，在進行 7 200845246 鍍薄銅需特殊機器設備，且鍍薄鋼後蝕刻之參數較難控制，常會 發生Micro Short或經可靠度實驗時造成Micro油沉丨而產生不 可收拾的結果。 不論是何種無導電線電路(NPL)製程，有時仍依賴對一層金屬層進 行選擇性蝕刻，並定義未被蝕刻的金屬層即為超細線路層。但是， 依據現有技術來看，蝕刻仍屬於難以精確控制的製程，所以不能 依賴侧來達到超細線路的製作，否則其細線路能力將受到相當 大的阻礙。 【發明内容】 本發明之主要目的在提供—種高密度細線構裝結構及其製造方 法’其不依職刻形成線路的手段，僅利用圖案化光阻層定義出 超細線路騎纽置’细驗手段完缺細線路層（细可移除 的載體或其上的金屬阻隔層來傳遞電鍍電流），以實現超細線路， 而帶來薄化效果，_在製程中或結鱗去除絲形成超細線路 層所需的載體、金觀_，又能增加可佈線空間，實現高密度 的目的° 本翻製造方法也不需成本較高的半加層^ (semi-additive process，SAp)技術來製作細線路。 基於上述目的，本翻高紐赠齡結齡要包含_結構類 似的板體、用綠合二板_介電雜。二板體巾解導體元件 在組合之後彼此處__。二板體均由超細線路、與之相同平 200845246 面上的絕緣層、被絲在雜線路上的轉體元件所 板體的超細線路中，未被防焊層遮蔽者可作為連接塾 : 球或利用錫球紐連接至另—轉體元件。在本發日財八錫 = _射段來軸二板财自所麵私線路層主 衣壬中或結束時去除用來形成超細線路層所需的载體、 阻隔層’以增加可雜雜，實現高密度的目的。 =一本=:點與精神可以藉由以下_詳述及所附圖式得 【實施方式】 請參閱第1A〜1F圖，第1A〜1F圖為本發明安裝半導體元件之示音 圖。如第1A〜U) _示之步驟是採雜_形成_部分^ 1E〜1F圖所示之步驟則為安裝半導體元件卜 請參閱第2圖’第2圖為本發明安裝半導體树之示意圖。如第 圖所示’藉著錢實施如第1A〜1F _示之步驟，而 裝半導體元件2。 圖為本發明高密度細線構裝的製造 請參閱第3A〜3D圖，第3A〜3D 方法之示意圖。 簡單來說’树邮蚊細_餘構及魏造紐，主要是將 如f 3A圖所不之第—板體1與第二板體2組合成如第3C圖所示 之早-板體’並且為了增加可佈線空間，實現高密度的目的，在 200845246 事先製作第-板體丨麵二板體2時，主要如第u〜iF圖所示之 步Γ分別猎著電鍍而雜刻手段來形成第—板體1與第二板體2 所:的超細線路層16，並在製程中或結束時去除用來形成超細線 路層16所_體10、金屬阻隔層m如第3C圖所示），而增加 佈線空間與實現高密度的目的。 底下，先簡單描述第-板體丨與第二板體2的結構、以及如何將 單-板體，臭再描述超細線路層16的製作方法。 上的半導體絕緣層18、被一 與 =::=::=成單，，_ 圖所示準備依序堆昼第-板體t、= 電彼/處^=侧’且如第狀 荖， _ 電膠膜50與苐二板體2。接 Μ成單利用介電膠膜5°，使第-板體1與第二板體2 ^成早-板體。然後，去除形成超細線路層_需的載體1〇、 金屬阻隔層12，曝露出第一板體】 -，如_示，_::= 取外側的部分超細線路層16可作 / *又的目的在 再安裝至其他電路板上，或如第作3=塾而可填充錫球⑷以便 41。除此之外，若需要導通半導體元it安裝其他半導體元件 _形成金屬導雜(未_。件Η時，還可在介電膠 200845246 口、:充如第3D圖所不之錫球52、62之前，還可在第—板體1和/ 或第板體2的超細線路層丨6之上，選擇地形成防焊層51。未被 =焊層51^蔽住的超細線路層16断作紅述連接墊。 、、〜的疋，在本發明高密度細線構裝結構中，超細線路層 、>、u為複數層並且在最外層的超細線路層16，除了可安裝第三 半導體耕41之外，還可安裝被動元件(未描繪 線路層16上安萝主道触-丄 衣+ ¥體70件2G、、41時，可採用打線或覆晶 段安裝該第三铸體元件。底下，接魏卿樣路層16的製 造方法。 & 簡單來說’如第1C圖所示，關於超細線路層16的製造方法，其 ^要利用在製程中能傳遞電鍍電流金屬阻隔層丨2(或是載體W本 ，在不依賴餘刻形成超細線路層16(製作更細緻的線路才有辦 法達到）’僅利用圖案化光阻層14定義出超細線路層Μ所在位 置，以電鍍手段來完全超細線路層16，而提高製程細線能力，以 2足夕I/O的弟-半導體元件2〇，並在製程中或製程即將結束時 去除载體10、金屬阻隔層12，以增加可佈線空間。同時，本發明 起方法衫需细縣較高辭加躲(卜addi ti ve Process，SAP)技術來製作細線路。 具體來說，在如第1A〜1D _之製造樹，首先在細0上 形成金屬阻隔層12，如第1Α圖所示。為了形成超細線路層16， 先如第1Β圖所示在金屬阻隔層12上形成圖案化光阻層⑽所具 200845246 有的光阻開σ i4a即線路形成的位置） — 金屬阻隔層12傳遞紐電流，而在、口弟1C _不利用 丨⑽形成超細線路層16。最後，去= 二屬_ 太除圖案化光阻層14。 Π細線路層16之後’還需在鄰近超細線路層Μ且在金 屬阻層12之上，填充絕緣層18，如❿圖所示。 在進行填充絕緣層18之前，為了提高超細線路層16附著至埴充 絕緣㈣峨性，絲條物16嶋作表面處理， 明加超崎闕16絲面積大小與域。上絲域理可採用 粗超細線路層16的表面或是在超細線路層Μ的表面上形成 讀個微小銅凸塊（或稱之為銅瘤）。不論哪種增加表面積的手 段，其目的都是藉著增加接觸面積，以便在如第π圖所示去除原 本支__層16 _㈣、金雜_2之後，超細線路 層16仍可穩固地被峡在絕緣層18中、以及其他封裝體的部分。 如第1Ε圖所示，在超細線路層16之上安裝第—半導體元件2〇。 若保留面積適當並經過適當表面處理也能透過這層金屬幫助熱發 散至外界，提高整體的元件運作穩定度。 在超細線路層16之上安裝第—半導體元件2Q時，可採用如第 1E〜1F圖所示打線或如第2圖所示之覆晶手段安裝第一半導體元 件20。若採用打線手段來安裝第一半導體元件2〇時，如第圖 所示先用導熱f 22將第-半導體元件2〇黏貼在銅面上，並利用 打線機將導線24分別連接至第一半導體元件2〇的端點、特定的 12 .200845246 超細線路層16之上，接著再以封膠26包覆住第一半導體元件2〇、 導線24，如第1F圖所示。 如第2圖所示，若採用覆晶手段來安裝第二半導體元件4〇時，則 利用錫球42電性連接至超細線路層16並充填封膠44。如第汕 圖所示’若採用覆晶手段來安裝第三半導體元件41時，則利用錫 球52電性連接至超細線路層16並充填封膠54。 藉由以上難频實侧之魏，鱗魏更加清楚描述本發明 之罐麟神’ 麟以上麟揭露的健频實酬來對本發 明之範嘴加以限制。相反地，其目的是希望能涵蓋各種改變及具 相等性的雜於本發贿欲ψ請之專·_範脅内。 【圖式簡單說明】 第1A〜1F圖為本發明安裝半導體元件之示意圖。 第2圖為本發明安裝半導體元件之示意圖。 、第3A〜3D圖為本發明高密度細線構裳的製造方法之示意圖。 【主要元件符號說明】 1第一板體 2第二板體 10載體 12金屬阻隔層 13 200845246 14圖案化光阻層 16超細線路層 18絕緣層 20、40、41半導體元件 22導熱膠 24導線 26、44、54 封膠 42、52、62 錫球 50介電膠膜 51防焊層200845246 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a package structure, and more particularly to a high-density fine wire structure and a method of manufacturing the same. [Prior Art] A major challenge for the 1C industry in the future is how to properly assemble various functions in a limited package form with appropriate cost, and to achieve the best performance of different functional grains. In the application of “definite” in the fields of digital, _, neon and silk, different functional electronic circuits produce different demands and wires with the need for process technology scaling. Therefore, integrating different functions on the single-die is not suitable for achieving a solution. With the rapid development of s〇c, Sip, Pip% (Package-on-package), P〇P (package-on-package), and stacked CSP technology, it is possible to estimate the most efficient system chips in the next few years. Should be wrapped in a package of towels, fully benefit the dimensional space, the integration of the use of heterogeneous technology and different voltage operating environments of various functions of different crystal grains. Specifically, the above system-in-package (SiP) is a package in which different ic types of crystal grains are assembled. Based on Sip, a new technology can be extended, which allows multiple dies to be stacked in a single package and uses a third space for more functionality or higher density integration. In this type of package structure, the first to be introduced in 200845246 is the stacked CSP, which is a memory combo, which can stack six layers of memory die in a BGA package. In this case, in addition to the conventional wire bonding, solder bumps or flip-chip technology can be used, and interposers are added to facilitate stacking, or heat dissipation is gradually adopted. For example, a package with a stacked die will contain a die as building block that is separated but interconnected by wires. It may contain a stack of one to several memory cells, an analog die stack. On another soc or digital die, a separate RF die is placed on a multi-layer interconnected substrate with different control and I/O (Input/ Output) path. In addition, if the stacked die contains memory, the control software can be written to the non-volatile memory (NVM: N〇n-v〇latile Memory). However, the traditional ultra-fine line technology can no longer be broken. For this reason, when manufacturing a more complicated package structure as described above, the overall package volume is still difficult to be greatly reduced, and it is unable to meet the requirements of increasingly short and thin electronic devices. Conventionally, a 5 〇 micron line fine line is formed on a Build up material such as a glass reinforced resin material (prepreg) layering method, and a copper sheet is used by using 丨·5~& 〇(10) thin copper skin. As a conductive layer for pattern plating, finally use the flash etching to bite the bottom rotation of h 5~5· 〇um. This method requires a rough surface to be combined with the glass fiber reinforced resin material because of the thin copper skin. It is necessary to have a thick chain surface structure of a certain degree of 200845246, but this structure will cause a strong residual moment to strengthen the biteness and cause electricity. The line width loss after the mine, based on the thickness of the bottom copper, can no longer be reduced by the amount of bite money. It is impossible to make a high-density carrier with a finer line spacing below 50 micron pitch. Generally, when nickel gold is electroplated on the ultra-fine circuit layer of the package carrier, in order to introduce the current required for electroplating into the carrier, especially the ultra-fine circuit layer to be electroplated, it is necessary to conduct electricity through the connection to the ultra-fine circuit layer. The wire is introduced, although this method can completely cover the ultra-fine circuit layer with the electroplated nickel-gold layer, but the conductive wire will remain in the carrier after completing the plating, occupying a limited wiring space. If the wiring space occupied by the conductive wires is to be reduced, and the width of the conductive wires is made narrow, the thickness of the electroplated nickel gold layer to be plated is not uniform, so reducing the width of the conductive wires is not an increase in wiring density. good idea. In order to improve power and reduce noise, and also to improve the wiring density, the current carrier white is designed to broadcast conductive lines, but the wire bonding still needs to be plated with nickel gold for better adhesion. . Although the wire-bonding zone can also be made of chemical nickel gold (or thickened gold) I, but the current rating is not reliable. Therefore, in the case of both the non-wire design and the electroplating nickel gold method, most of the wiring blocks are produced by the GPP program. However, before the GPP procedure, since the electro-mineral nickel-gold layer is formed before the formation of the solder resist (SM), the area of the electroplated nickel-gold layer under the SM is relatively large. Due to the poor adhesion between SM and gold surface, the current production methods seem to be insufficient in today's increasingly demanding reliability and heat resistance. In addition, the process of non-conducting electroplating (NPL) process is quite complicated. In the case of 7 200845246, thin copper is required for special equipment, and the parameters of etching after thin steel plating are difficult to control. Micro Short or reliability test often occurs. When the Micro oil sinks, it produces an unstoppable result. Regardless of the non-conductive line (NPL) process, it is sometimes dependent on selective etching of a metal layer and defining a metal layer that is not etched as an ultra-fine circuit layer. However, according to the prior art, etching is still a process that is difficult to precisely control, so it is not possible to rely on the side to achieve the fabrication of ultra-fine lines, otherwise its fine line capability will be considerably hindered. SUMMARY OF THE INVENTION The main object of the present invention is to provide a high-density thin-line structure and a method for manufacturing the same, which means that the line is not formed by the use of the pattern, and only the patterned photoresist layer is used to define the ultra-fine line. The inspection means completes the thin circuit layer (the fine removable carrier or the metal barrier layer thereon to transfer the plating current) to realize the ultra-fine circuit, which brings the thinning effect, _ in the process or the scale removal wire formation The carrier and gold view required for the ultra-fine circuit layer can increase the wiring space and achieve the purpose of high density. The manufacturing method does not require a relatively high cost semi-additive process (SAp) technology. To make a fine line. Based on the above purposes, the age of the dynasty is to include a slab of similar structure and a green slab. The two-plate towel-dissolving conductor elements are __ at each other after combination. The two plates are made of ultra-fine lines, the same as the insulation layer on the surface of 200845246, and the ultra-fine line of the body of the rotating element on the miscellaneous line. If it is not shielded by the solder mask, it can be used as a connection. : Ball or solder ball to connect to another - swivel element. In the present day, the company has a carrier and a barrier layer to form an ultra-fine circuit layer in the middle or at the end of the main layer of the private circuit layer. Miscellaneous, achieving high density. = one book =: point and spirit can be obtained by the following detailed description and the drawings. [Embodiment] Please refer to Figs. 1A to 1F, and Figs. 1A to 1F are diagrams showing the mounting of semiconductor elements of the present invention. The steps shown in Fig. 1A to U) are the steps shown in the figure of Fig. 1 to 1E to 1F. The semiconductor element is mounted. Referring to Fig. 2, Fig. 2 is a schematic view showing the mounting of a semiconductor tree according to the present invention. As shown in the figure, the semiconductor element 2 is mounted by performing the steps as shown in Figs. 1A to 1F. The figure shows the manufacture of the high-density fine line structure of the present invention. Referring to Figures 3A to 3D, a schematic diagram of the 3A to 3D methods. Simply put, 'trees and mosquitoes _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 'In order to increase the space available for wiring and achieve high density, when the first-plate body 2 board 2 was prepared in advance in 200845246, the steps as shown in the figure u~iF are respectively etched and etched. The ultra-fine wiring layer 16 of the first plate body 1 and the second plate body 2 is formed and removed during the process or at the end to form the ultrafine circuit layer 16 body 10, the metal barrier layer m such as the 3C Figure shows), while increasing wiring space and achieving high density. Next, the structure of the first-plate body and the second plate body 2, and how to form the ultra-fine circuit layer 16 will be described briefly. The upper semiconductor insulating layer 18 is formed into a single and =::=::=, and the _ figure is prepared to sequentially stack the first-plate body t, = electric/where ^= side' and as the first state , _ electric film 50 and second plate 2. The first plate body 1 and the second plate body 2 are formed into an early-plate body by using a dielectric film of 5°. Then, the carrier 1〇 and the metal barrier layer 12 which are required to form the ultrafine wiring layer are removed, and the first plate body is exposed. As shown in the figure, the _::= part of the outer ultrafine wiring layer 16 can be used as /* A further object is to reinstall to other boards, or to fill the solder balls (4) for 41 as in the case of 3 = 。. In addition, if it is necessary to turn on the semiconductor element to install other semiconductor components _ forming metal conduction impurities (not _. Η, can also be in the dielectric glue 200845246 mouth: filling the tin ball 52 as shown in the 3D figure, Before 62, the solder resist layer 51 may be selectively formed on the ultra-fine wiring layer 6 of the first plate body 1 and/or the plate body 2. The ultrafine circuit layer not covered by the solder layer 51 In the high-density fine-line structure of the present invention, the ultra-fine wiring layer, >, u is a plurality of layers and the ultra-fine wiring layer 16 at the outermost layer is removed. In addition to the installation of the third semiconductor plough 41, a passive component can also be installed (the same is not depicted on the circuit layer 16 on the main road of the road - the clothing + 70 pieces of 2G, 41, the wire can be used to install the wire Three casting elements. Underneath, the manufacturing method of the Weiqing sample layer 16 is used. & Simply, as shown in Fig. 1C, the manufacturing method of the ultrafine wiring layer 16 is to be utilized in the process. Electroplating current metal barrier layer 丨2 (or carrier W, to form ultra-fine wiring layer 16 without relying on the residuals (to make a more detailed circuit to do Achieved] 'Using the patterned photoresist layer 14 to define the position of the ultra-fine circuit layer ,, to completely superfine the wiring layer 16 by electroplating, and to improve the process thin-line capability, to the second-party I/O 2〇, and during the process or at the end of the process, the carrier 10 and the metal barrier layer 12 are removed to increase the wiring space. At the same time, the method of the present invention requires a fine county to evade (addi ti ve Process, SAP) technology to make fine lines. Specifically, in the manufacturing tree such as 1A to 1D, the metal barrier layer 12 is first formed on the thin 0, as shown in Fig. 1. In order to form the ultrafine wiring layer 16, first As shown in FIG. 1 , a patterned photoresist layer (10) is formed on the metal barrier layer 12, and the photoresist opening σ i4a is a position where the line is formed) — the metal barrier layer 12 transmits a current, and the brother 1C _ Do not use 丨 (10) to form the ultrafine wiring layer 16. Finally, go = two genus _ too thin patterned photoresist layer 14. After the thin circuit layer 16 'have to be adjacent to the ultrafine wiring layer 在 and in the metal resistive layer 12 Above, fill the insulating layer 18, as shown in the figure. Before 18, in order to improve the adhesion of the ultra-fine circuit layer 16 to the 绝缘-filled insulation (four), the wire 16 is treated as a surface treatment, and the size and domain of the 16-wire area of the super-striped shovel are used. The surface of the layer 16 is formed on the surface of the ultrafine circuit layer to form a small copper bump (or copper tumor). Regardless of the means for increasing the surface area, the purpose is to increase the contact area so that After removing the original branch __layer 16 _(4), Jinza_2 as shown in the πth diagram, the ultrafine wiring layer 16 can still be stably immersed in the insulating layer 18, and other parts of the package. As shown, the first semiconductor element 2 is mounted over the ultrafine wiring layer 16. If the reserved area is appropriate and properly surface treated, the metal can help the heat to be dissipated to the outside world, improving the stability of the overall component operation. When the first semiconductor element 2Q is mounted on the ultrafine wiring layer 16, the first semiconductor element 20 may be mounted by wire bonding as shown in Figs. 1E to 1F or by flip chip as shown in Fig. 2. When the first semiconductor element 2 is mounted by wire bonding, the first semiconductor element 2 is first adhered to the copper surface by the heat transfer f 22 as shown in the figure, and the wire 24 is respectively connected to the first semiconductor by a wire bonding machine. The end of the element 2 turns, on the specific 12.200845246 ultrafine circuit layer 16, and then the first semiconductor element 2, the wire 24 is covered with a sealant 26, as shown in Fig. 1F. As shown in Fig. 2, when the second semiconductor element 4 is mounted by flip chip bonding, the solder ball 42 is electrically connected to the ultrafine wiring layer 16 and filled with the sealant 44. When the third semiconductor element 41 is mounted by flip chip bonding as shown in Fig. 1, the solder ball 52 is electrically connected to the ultrafine wiring layer 16 and filled with the sealant 54. With the above-mentioned difficulties, the Wei Wei, the scale Wei, more clearly describes the health-funded remuneration disclosed by the tanker Lin Lin of the present invention to limit the scope of the present invention. On the contrary, the purpose is to cover all kinds of changes and equalities in this special issue. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1F are schematic views showing the mounting of a semiconductor element of the present invention. Fig. 2 is a schematic view showing the mounting of a semiconductor element of the present invention. 3A to 3D are schematic views showing a manufacturing method of the high-density fine-line structure of the present invention. [Main component symbol description] 1 first plate body 2 second plate body 10 carrier 12 metal barrier layer 13 200845246 14 patterned photoresist layer 16 ultra-fine circuit layer 18 insulating layer 20, 40, 41 semiconductor element 22 thermal adhesive 24 wire 26, 44, 54 sealant 42, 52, 62 solder ball 50 dielectric film 51 solder mask

Claims (1)

200845246 十、申請專利範圍： •種同山度、、、田線構裝結構的製造方法，該製造方法 包含： (a)在一载體上形成一金屬阻隔層； ⑻在該金屬阻隔層上形成〆圖案化光阻層，該 圖案化光阻層具有一光阻開口； (c) 利用該金屬阻隔層傳遞電鍍電流，而在該光 阻開口内的該金屬阻隔層上電鍍形成一超細 線路層； (d) 去除該圖案化光阻層； (e) 在該金屬阻隔層之上且在該超細線路層的側 邊’填充一絕緣層； (f) 在該超細線路層之上，安裝一第一半導體元 件； (g) 重複步驟（a)至步驟（f)，而在一超細線路層 之上’安裝一第二半導體元件； (h) 藉著一介電膠膜，使步驟（a)至步驟（f)所形 成的一第一板體與步驟（g)所形成的一第二 板體被組合成單一板體；以及 15 200845246 (i)去除屬於該第一板體和該第二板體的該载 體、該金屬阻隔層，而曝露出該超細線路層， 部分該超細線路層可作為一焊球墊，該焊球 墊可填充一錫球。 2·如申請專利範圍第1項所述之高密度細線構裝結構 的製造方法，其中製造方法進一步包含： 在該超細線路層選擇地形成一防烊層，未被該防 焊層遮蔽者可作為一連接墊。 3·如申請專利範圍第2項所述之高密度細線構裝結構 的製造方法，其中已填充該錫球的該連接墊可電性 連接至一第三半導體元件。 4·如申請專利範圍第3項所述之高密度細線構裝結構 的製造方法，其中在該超細線路層上安裝該第三半 ‘體元件時，可採用打線或覆晶手段安裝該第三半 導體元件。 5.如申μ專利範圍第丨項所述之高密度細線構裝結構 的製造方法，其中在該超細線路層上安裝該第一半 導體元件或該第二半導體元件時，可採用打線或覆 晶手段安裝該第一半導體元件或該第二半導體元 件0 200845246 6 · —種高密度細線構裝結構，該構裝結構包含： 一第一板體，包含： 一超細線路層， 一絕緣層，被形成在該超細線路層的相同平 面上；以及 一第一半導體元件，被安裝在該超細線路層 上； 一第二板體，包含·· 一超細線路層； 纟G緣層，被形成在該超細線路層的相同平 面上； 第二半導體元件，被安裝在該超 上； 細線路層 第一板體與該第二板體 介電膠膜，被形成在該 體與該第=板體被組合成 之間，而使該第一 I 一板體； 中，在該第—板體和兮 外的該超細線路厚可；板體中曝露在 球塾。 曰了作為填充一錫球的一烊 17 200845246 7·如申請專利範圍第6項所述之高密度細線構裝結 構，其中該結構進一步包含： 一防焊層，被選擇地形成在該第一板體和/或該 第二板體的該超細線路層之上，未被該防焊 層遮蔽者可作為一連接墊。 8. 如申請專利範圍第7項所述之高密度細線構裝結 構，其中已填充一錫球的該連接墊可電性連接至一 第三半導體元件。 9. 如申請專利範圍第8項所述之高密度細線構震結 構’其中在該超細線路層上安裝該第三半導體元件 時，可柘用打線或覆晶手段安裝該第三半導體元件。 10. 如申請專利範圍第6項所述之高密度細線構裝結 構’其中在該超細線路層上安裝該第—半導體元件 ί 或該第二半導體元件時，可接k A > ® θ 4 j抓用打線或覆晶手段安 裝該第一半導體元件或該第二半導體元件。 18200845246 X. Patent application scope: • Manufacturing method for the same mountain, and line structure, the manufacturing method comprises: (a) forming a metal barrier layer on a carrier; (8) on the metal barrier layer Forming a patterned photoresist layer, the patterned photoresist layer having a photoresist opening; (c) transferring a plating current by using the metal barrier layer, and plating a superfine layer on the metal barrier layer in the photoresist opening a circuit layer; (d) removing the patterned photoresist layer; (e) filling an insulating layer over the metal barrier layer and on a side of the ultrafine wiring layer; (f) in the ultrafine wiring layer Mounting a first semiconductor component; (g) repeating steps (a) through (f), and mounting a second semiconductor component over an ultrafine wiring layer; (h) by means of a dielectric film , a first plate formed by steps (a) to (f) and a second plate formed by step (g) are combined into a single plate; and 15 200845246 (i) removal belongs to the first The plate body and the carrier of the second plate body and the metal barrier layer expose the ultrafine The circuit layer, a part of the ultra-fine circuit layer can be used as a solder ball pad, and the solder ball pad can fill a solder ball. 2. The method of manufacturing a high-density fine-wire structure according to claim 1, wherein the manufacturing method further comprises: selectively forming a tamper-proof layer on the ultra-fine wiring layer, not being shielded by the solder resist layer Can be used as a connection pad. 3. The method of manufacturing a high-density thin-line structure according to claim 2, wherein the connection pad filled with the solder ball is electrically connected to a third semiconductor element. 4. The method for manufacturing a high-density fine-line structure according to claim 3, wherein when the third-half body member is mounted on the ultra-fine circuit layer, the wire can be mounted by wire bonding or flip chip bonding. Three semiconductor components. 5. The method of manufacturing a high-density thin-line structure according to the above aspect of the invention, wherein the first semiconductor element or the second semiconductor element is mounted on the ultra-fine wiring layer, and a wire bonding or a covering may be employed. The first semiconductor element or the second semiconductor element is mounted by a crystal means, and the high-density thin-line structure comprises: a first plate body comprising: an ultra-fine circuit layer, an insulating layer, Formed on the same plane of the ultrafine wiring layer; and a first semiconductor component mounted on the ultrafine wiring layer; a second panel including an ultrafine wiring layer; a 纟G edge layer, Formed on the same plane of the ultrafine circuit layer; a second semiconductor component mounted on the super; a thin circuit layer first plate and the second plate dielectric film formed on the body and the The first plate body is combined into the first plate, and the ultra-fine line outside the first plate body and the outer plate is thick; the plate body is exposed to the ball. A high-density fine-wire structure as described in claim 6, wherein the structure further comprises: a solder resist layer selectively formed on the first Above the ultra-fine wiring layer of the board body and/or the second board body, the soldering layer is not shielded by the solder mask layer. 8. The high-density thin-line structure as described in claim 7, wherein the connection pad filled with a solder ball is electrically connected to a third semiconductor element. 9. The high-density thin-line structure structure as described in claim 8 wherein the third semiconductor element is mounted on the ultra-fine wiring layer, the third semiconductor element can be mounted by wire bonding or flip chip bonding. 10. The high-density fine-wire structure according to claim 6, wherein the first semiconductor element ί or the second semiconductor element is mounted on the ultra-fine wiring layer, and k A > The first semiconductor element or the second semiconductor element is mounted by wire bonding or flip chip bonding. 18
TW96116544A 2007-05-09 2007-05-09 High-density fine line package structure and method for fabricating the same TW200845246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW96116544A TW200845246A (en) 2007-05-09 2007-05-09 High-density fine line package structure and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW96116544A TW200845246A (en) 2007-05-09 2007-05-09 High-density fine line package structure and method for fabricating the same

Publications (1)

Publication Number Publication Date
TW200845246A true TW200845246A (en) 2008-11-16

Family

ID=44822827

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96116544A TW200845246A (en) 2007-05-09 2007-05-09 High-density fine line package structure and method for fabricating the same

Country Status (1)

Country Link
TW (1) TW200845246A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856283A (en) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 First packaged and then etched packaging structure with single chip normally installed and base islands buried and preparation method of structure
CN102856270A (en) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 Single-chip flip, etching-after-packaging and non-pad packaging structure and manufacturing method thereof
CN102867791A (en) * 2012-05-09 2013-01-09 江苏长电科技股份有限公司 Multi-chip reversely-arranged etched-encapsulated base island-buried encapsulating structure and manufacturing method thereof
CN102867790A (en) * 2012-05-09 2013-01-09 江苏长电科技股份有限公司 Multi-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof
CN102867789A (en) * 2012-05-09 2013-01-09 江苏长电科技股份有限公司 Single-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof
CN102881670A (en) * 2012-05-09 2013-01-16 江苏长电科技股份有限公司 Multi-chip positive packaging structure for embedding basic island by first packaging and second etching, and manufacturing method for multi-chip positive packaging structure
TWI401753B (en) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng Method for making a stackable package

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401753B (en) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng Method for making a stackable package
CN102867790A (en) * 2012-05-09 2013-01-09 江苏长电科技股份有限公司 Multi-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof
CN102867791A (en) * 2012-05-09 2013-01-09 江苏长电科技股份有限公司 Multi-chip reversely-arranged etched-encapsulated base island-buried encapsulating structure and manufacturing method thereof
CN102856283A (en) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 First packaged and then etched packaging structure with single chip normally installed and base islands buried and preparation method of structure
CN102867789A (en) * 2012-05-09 2013-01-09 江苏长电科技股份有限公司 Single-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof
CN102881670A (en) * 2012-05-09 2013-01-16 江苏长电科技股份有限公司 Multi-chip positive packaging structure for embedding basic island by first packaging and second etching, and manufacturing method for multi-chip positive packaging structure
CN102856270A (en) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 Single-chip flip, etching-after-packaging and non-pad packaging structure and manufacturing method thereof
CN102881670B (en) * 2012-05-09 2015-03-04 江苏长电科技股份有限公司 Multi-chip positive packaging structure for embedding basic island by first packaging and second etching, and manufacturing method for multi-chip positive packaging structure
CN102867789B (en) * 2012-05-09 2015-03-04 江苏长电科技股份有限公司 Single-chip positively-arranged first-encapsulated second-etched base island-exposed encapsulating structure and manufacturing method thereof
CN102856283B (en) * 2012-05-09 2015-04-29 江苏长电科技股份有限公司 First packaged and then etched packaging structure with single chip normally installed and base islands buried and preparation method of structure
CN102856270B (en) * 2012-05-09 2015-04-29 江苏长电科技股份有限公司 Single-chip flip, etching-after-packaging and non-pad packaging structure and manufacturing method thereof
CN102867790B (en) * 2012-05-09 2015-04-29 江苏长电科技股份有限公司 Multi-chip positively-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof
CN102867791B (en) * 2012-05-09 2015-06-03 江苏长电科技股份有限公司 Multi-chip reversely-arranged etched-encapsulated base island-buried encapsulating structure and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US7622377B2 (en) Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US7790270B2 (en) Wiring board and semiconductor device
JP2005209689A (en) Semiconductor device and its manufacturing method
US9462704B1 (en) Extended landing pad substrate package structure and method
TW201715621A (en) Molded interconnect substrate and the method for manufacturing the same
TW200845246A (en) High-density fine line package structure and method for fabricating the same
TWI728936B (en) Electronic packaging and manufacturing method thereof
WO2021018014A1 (en) Tsv-based multi-chip package structure and method for manufacturing same
TW201501263A (en) Semiconductor packages and methods of packaging semiconductor devices
TW201314853A (en) Package substrate having holder and fabricating method thereof, package structure having holder and fabricating method thereof
TW200903757A (en) Semiconductor packages
TW200828554A (en) Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same
US8471375B2 (en) High-density fine line structure and method of manufacturing the same
US20090008766A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
KR20240017393A (en) Semiconductor device and manufacturing method thereof
TWI389276B (en) Package substrate structure and fabrication method thereof
CN113130420B (en) Embedded packaging structure and manufacturing method thereof
TWI576979B (en) Package substrate and method for manufacturing the same
CN104112673B (en) Chip package base plate and preparation method thereof
JP2010021468A (en) Circuit substrate, and manufacturing method thereof
TWI406374B (en) Semiconductor package of chip using copper process
CN101959374B (en) Method for manufacturing multilayer printed circuit board
TW200939442A (en) Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
JP2008124301A (en) Semiconductor and its manufacturing method
JP2007103855A (en) Substrate for semiconductor device and semiconductor device