TWI389276B - Package substrate structure and fabrication method thereof - Google Patents

Description

Package substrate structure and its preparation method

The invention relates to a semiconductor structure and a manufacturing method, in particular to a package substrate structure and a manufacturing method thereof.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. At present, a package substrate for carrying a semiconductor wafer includes a wire-bonded package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA); and is required for operation of a microprocessor, a wafer set, and a graphics chip. Packaged substrates with wiring also need to improve the quality of the transmitted chip signals, improve the bandwidth, control impedance and other functions in order to cope with the development of high I / O number of packages.

In the current flip chip technology, a semiconductor wafer is electrically connected to a package substrate, and an electrode pad is disposed on a surface of the semiconductor integrated circuit (IC) wafer, and the package substrate has a corresponding electric power. The conductive pad and the conductive bump or other conductive adhesive material may be appropriately disposed between the semiconductor wafer and the package substrate, and the semiconductor wafer is disposed on the package substrate with the electrical contact surface facing downward.

Please refer to FIGS. 1A to 1C for a schematic cross-sectional view of a conventional package substrate structure.

As shown in FIG. 1A, first, a substrate body 10 having at least one surface 10a is provided, a wiring layer 11 is formed on the surface 10a of the substrate body 10, and the circuit layer 11 has a plurality of electrical contact pads 112.

As shown in FIG. 1B, a solder resist layer 12 is formed on the surface 10a and the circuit layer 11, and a plurality of openings 120 are formed in the solder resist layer 12, so that the respective electrical contact pads 112 are correspondingly exposed to the openings. 120.

As shown in FIGS. 1C and 1C', the conductive bumps 13 are formed in a printed manner on the electrical contact pads 112 in each of the openings 120, as shown in FIG. 1C; or by the conductive layer 14. The conductive bumps 13' are formed by electroplating on the electrical contact pads 112. As shown in FIG. 1C', the method for forming the conductive bumps 13' by electroplating is a mature technology, and details are not described herein.

However, in the above-mentioned package substrate process, the electrical contact pad 112 is disposed in the fine pitch layout of the high-density wiring, and the processing cost is high in the solder resist layer 12 due to alignment difficulty; and the opening 120 is difficult to be completely exposed. The contact area of the electrical contact pad 112 is too small, so that the contact area formed by the conductive bumps 13 , 13 ′ electrically connected to the electrical contact pad 112 is insufficient, and the bonding force is insufficient. The problem of cracking. For example, when the distance between the electrical contact pads 112 is only 100 μm, the alignment tolerance of the opening 120 of the solder resist layer 12 is only plus or minus 10 μm, and the size of the opening 120 is only 40-50 μm, so the alignment is difficult. Poor reliability.

Therefore, how to provide a package substrate structure and a manufacturing method thereof to avoid the prior art, in a fine pitch layout of high-density wiring, it is difficult to form an opening in the solder resist layer to completely expose the electrical contact pad, resulting in the above-mentioned deficiency, It has become an urgent issue to be overcome in the industry.

In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a package substrate structure and a method for fabricating the same, which can eliminate the formation of openings in the solder resist layer, thereby avoiding the lack of electrical connection defects due to the small opening.

To achieve the above and other objects, the present invention provides a package substrate structure, comprising: a substrate body having an internal circuit layer disposed on at least one surface thereof, and the internal circuit layer has a plurality of electrical connection pads; a dielectric layer, The device is disposed on the substrate body and the inner circuit layer, and has a plurality of openings for respectively exposing the electrical connection pads; the circuit layer is disposed on the dielectric layer, and is electrically conductive in the opening a blind hole electrically connected to the electrical connection pad, wherein the circuit layer has a plurality of electrical contact pads; a plurality of conductive bumps are correspondingly disposed on each of the electrical contact pads; and the first insulating protective layer is disposed on The dielectric layer and the circuit layer have at least one opening for exposing the electrical contact pads and the conductive bumps thereon; and a second insulating protective layer is disposed in the opening, and each of the conductive bumps The height of the block is higher than the thickness of the second insulating protective layer, so that each of the conductive bumps is exposed to the second insulating protective layer.

According to the above structure, the surface of the exposed conductive bump is provided with a surface treatment layer, and the material forming the surface treatment layer is gold, silver, electroplated nickel/gold, electroless nickel/gold, and nickel immersion gold. (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin; or a solder material on the conductive bump.

The invention provides a method for fabricating a package substrate structure, comprising: providing a substrate body, forming an internal circuit layer on at least one surface thereof, wherein the internal circuit layer has a plurality of electrical connection pads; and the substrate body and the internal circuit layer Forming a dielectric layer, and forming a plurality of openings in the dielectric layer to respectively expose the electrical connection pads; forming a circuit layer on the dielectric layer, and forming a conductive blind hole in the opening, Electrically connected to the electrical connection pad, the circuit layer has a plurality of electrical contact pads; conductive bumps are respectively formed on the electrical contact pads; and a first insulating protective layer is formed on the dielectric layer and the circuit layer, And forming at least one opening in the first insulating protective layer, exposing the electrical contact pads and the conductive bumps thereon; and forming a second insulating protective layer in the opening, and the thickness of the second insulating protective layer The height of the conductive bumps is higher than the thickness of the second insulating protective layer, so that the conductive bumps are exposed to the second insulating protective layer.

The method for manufacturing the circuit layer and the conductive bump comprises: forming a conductive layer on the dielectric layer, the hole wall of the opening, and the electrical contact pad in the opening; forming a first resist layer on the conductive layer And forming a plurality of open-resist layer open regions in the first resistive layer, and a portion of the resistive opening regions corresponding to the openings of the dielectric layers, so that a portion of the conductive layer is exposed in the open region of the resist layer; Forming the circuit layer on the conductive layer in the open region of the layer, and forming the conductive via hole in the opening of the dielectric layer to electrically connect to the internal circuit layer, and the circuit layer has a plurality of electrical contact pads; Forming a second resist layer on the first resist layer and the circuit layer, and forming a plurality of resistive layer openings in the second resist layer to correspondingly expose the respective electrical contact pads, wherein the barrier layer opening is larger or smaller The electrical contact pad; electroplating to form a conductive bump on the electrical contact pad in the opening of the resist layer; and removing the second resist layer, the first resist layer and the conductive layer covered thereby.

According to the above method, the step of forming the conductive bump includes forming a solder material on the conductive bump; if a solder material is not formed on the conductive bump, forming a surface on the exposed conductive bump The layer is treated, and the material forming the surface treatment layer is gold, silver, electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion). Tin) or electroplated tin.

The package substrate structure and the manufacturing method thereof are mainly for forming a dielectric layer and a circuit layer on the substrate body, and when the circuit layer is formed by electroplating, the conductive bumps are electroplated on the electrical contact pads of the circuit layer, and then Forming a first insulating protective layer on the dielectric layer and the wiring layer, and forming the opening in the first insulating protective layer to expose the electrical contact pads and the conductive bumps thereon at a time, and then Forming a second insulating protective layer in the opening of the insulating protective layer, and making the thickness of the second insulating protective layer smaller than the first insulating protective layer, and exposing each of the conductive bumps, so as to avoid the conventional formation The holes are correspondingly exposed to the absence of each of the electrical contact pads.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

[First Embodiment]

Please refer to FIGS. 2A to 2J, which are schematic diagrams of the structure of the package substrate and the method of manufacturing the same according to the present invention.

As shown in FIG. 2A, at least one substrate body 20 having an internal wiring layer 21 formed on the surface thereof is provided, and the internal wiring layer 21 has a plurality of electrical connection pads 211 for passing through conductive vias (PTH) or conductive via holes. The inner circuit layer 21 is electrically connected to the lower layer or the other side of the substrate body 20. However, there are many types of internal structures of the substrate, which are well known in the industry, and are not technical features of the present invention, and therefore will not be described again, and are hereby described.

As shown in FIG. 2B, a dielectric layer 22 is formed on the substrate body 20 and the internal wiring layer 21, and a plurality of openings 220 are formed in the dielectric layer 22 to expose the respective electrical connection pads 211.

As shown in FIG. 2C, a conductive layer 23 is formed on the dielectric layer 22, the hole wall of the opening 220, and the electrical connection pad 211 in the opening 220. Then, a first resistance is formed on the conductive layer 23. a plurality of resistive opening regions 240a are formed in the first resistive layer 24a, and a portion of the resistive opening region 240a corresponds to the opening 220 of each of the dielectric layers 22, so that a portion of the conductive layer 23 is exposed. The barrier opening region 240a.

As shown in FIG. 2D, a wiring layer 25 is formed on the conductive layer 23 in the open region 240a, and a conductive via 251 is formed in the opening 220 of the dielectric layer 22 to electrically connect to the interior. The circuit layer 21 is electrically connected to the pad 211, and the circuit layer 25 has a plurality of electrical contact pads 252.

As shown in FIG. 2E, a second resist layer 24b is formed on the first resist layer 24a and the circuit layer 25, and a plurality of resistive opening 240b is formed in the second resist layer 24b to correspondingly expose the electrical properties. The contact pad 252; wherein the aperture of the resistive opening 240b is smaller than the size of the electrical contact pad 255.

As shown in FIG. 2F, the conductive bumps 26 are plated on the electrical contact pads 252 of the resistive opening 240b; since the aperture of the resistive opening 240b is smaller than the size of the electrical contact pads 252, The conductive bumps 26 are smaller in size than the electrical contact pads 252.

As shown in FIG. 2F', in another embodiment, the aperture of the barrier opening 240b may be larger than the size of the electrical contact pad 252, so that the size of the conductive bump 26' is larger than the electrical contact. Pad 252.

As shown in FIGS. 2G and 2G', the second resist layer 24b, the first resist layer 24a and the conductive layer 23 covered thereon are removed, and the dielectric layer 22, the wiring layer 25 and the conductive bumps 26 are exposed.

As shown in FIG. 2H, the first insulating layer 27 is formed on the dielectric layer 22 and the wiring layer 25, and at least one opening 270 is formed in the first insulating protective layer 27. The electrical contact pads 252 and the conductive bumps 26 thereon are exposed.

As shown in FIG. 2I, a second insulating protective layer 28 is formed in the opening 270, and the thickness of the second insulating protective layer 28 is smaller than the first insulating protective layer 27, and the height of each of the conductive bumps 26 is high. The thickness of the second insulating protective layer 28 is such that each of the conductive bumps 26 is exposed to the second insulating protective layer 28.

As shown in FIGS. 2J and 2J', the surface treatment layers 29, 29' are formed on the exposed conductive bumps 26, 26'; wherein the material forming the surface treatment layer 29, 29' is gold or silver. , electroplated nickel / gold, electroless nickel / gold, nickel immersion gold (ENIG), nickel palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplating tin. If the structure of the 2G' diagram is used as a subsequent process, a structure as shown in Fig. 2J' will be formed.

The present invention further provides a package substrate structure, comprising: a substrate body 20 having an inner circuit layer 21 disposed on at least one surface thereof, and the inner circuit layer 21 has a plurality of electrical connection pads 211; a dielectric layer 22 The substrate body 20 and the internal circuit layer 21 are provided with a plurality of openings 220 for respectively exposing the electrical connection pads 211; the circuit layer 25 is disposed on the dielectric layer 22 and is opened thereon. The conductive hole 251 is disposed in the hole 220 to electrically connect to the internal circuit layer 21, and the circuit layer 25 has a plurality of electrical contact pads 252; the plurality of conductive bumps 26 are correspondingly disposed on the respective electrical contact pads. The first insulating protective layer 27 is disposed on the dielectric layer 22 and the circuit layer 25, and has at least one opening 270 for exposing the electrical contact pads 252 and the conductive bumps 26 thereon; The second insulating protective layer 28 is disposed in the opening 270, and the thickness of the second insulating protective layer 28 is smaller than the first insulating protective layer 27, and the height of each of the conductive bumps 26 is higher than the second insulating The thickness of the protective layer 28 is such that each of the conductive bumps 26 is exposed to the second insulation protection 28.

According to the above package substrate structure, the surface treatment layer 29 is formed on the exposed conductive bumps 26, and the material forming the surface treatment layer 29 is gold, silver, electroplated nickel/gold, electroless nickel/gold, and chemical Nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin.

[Second embodiment]

Please refer to FIG. 3A to FIG. 3C , which are schematic diagrams of another embodiment of the package substrate structure and the manufacturing method thereof according to the present invention. The difference from the previous embodiment is that when the conductive bump is formed by electroplating, the conductive bump is also disposed on the conductive bump. A solder material is formed.

As shown in FIG. 3A, a structure as shown in FIG. 2F is provided, and a conductive bump 26 is electroplated on the electrical contact pad 252 in the barrier opening 240b, and then electroplated on the conductive bump 26. A solder material 30 is formed.

As shown in FIG. 3B, the second resistive layer 24b, the first resistive layer 24a and the conductive layer 23 covered thereon are removed, and the dielectric layer 22, the wiring layer 25, the conductive bumps 26 and the solder material 30 are exposed. .

As shown in FIGS. 3C and 3C', a first insulating protective layer 27 is formed on the dielectric layer 22 and the wiring layer 25, and at least one opening 270 is formed in the first insulating protective layer 27 to expose the electrical properties. Contact pad 252, conductive bumps 26, 26' and solder material 30, 30', and a second insulating protective layer 28 is formed in the opening 270, and the thickness of the second insulating protective layer 28 is smaller than the first insulating protective layer 27, the height of each of the conductive bumps 26, 26' is higher than the thickness of the second insulating protective layer 28, so that a portion of the conductive bumps 26, 26' and the solder material 30, 30' convex thereon Out of the second insulating protective layer 28. If a structure as shown in Fig. 2F' is provided as a subsequent process in the present embodiment, a structure as shown in Fig. 3C' will be formed.

The present invention further provides a package substrate structure, comprising: a substrate body 20 having an inner circuit layer 21 on at least one surface thereof, and the inner circuit layer 21 has a plurality of electrical connection pads 211; the dielectric layer 22 is provided On the substrate body 20 and the internal circuit layer 21, a plurality of openings 220 are formed to respectively expose the electrical connection pads 211; the circuit layer 25 is attached to the dielectric layer 22, and the openings 220 are formed in the openings 220. The conductive via 251 is electrically connected to the internal circuit layer 21, and the circuit layer 25 has a plurality of electrical contact pads 252. The plurality of conductive bumps 26 are disposed on the respective electrical contact pads 252. The first insulating protective layer 27 is disposed on the dielectric layer 22 and the circuit layer 25, and has at least one opening 270 for exposing the electrical contact pads 252 and the conductive bumps 26 thereon; the second insulation The protective layer 28 is disposed in the opening 270, and the thickness of the second insulating protective layer 28 is smaller than the first insulating protective layer 27, and the height of each of the conductive bumps 26 is higher than the second insulating protective layer 28. a thickness of the conductive bumps 26 exposed to the second insulating protective layer 28; And the solder material 30 is provided based on the exposed portions of the conductive bumps 26.

The package substrate structure and the manufacturing method thereof are mainly for forming a dielectric layer and a circuit layer on the substrate body, and when the circuit layer is formed by electroplating, the conductive bumps are electroplated on the electrical contact pads of the circuit layer, and then Forming a first insulating protective layer on the dielectric layer and the wiring layer, and forming the opening in the first insulating protective layer to expose the electrical contact pads and the conductive bumps thereon at a time, and then Forming a second insulating protective layer in the opening of the insulating protective layer, and making the thickness of the second insulating protective layer smaller than the first insulating protective layer, and exposing each of the conductive bumps, so as to avoid the conventional formation The holes are correspondingly exposed to the absence of each of the electrical contact pads.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

10,20. . . Substrate body

10a. . . surface

11,25. . . Circuit layer

112,252. . . Electrical contact pad

12. . . Solder mask

120,220. . . Opening

13,13’,26,26’. . . Conductive bump

14,23. . . Conductive layer

twenty one. . . Internal circuit layer

211. . . Electrical connection pad

twenty two. . . Dielectric layer

24a. . . First resistive layer

240a. . . Resistive open area

24b. . . Second resistive layer

240b. . . Resistive opening

251. . . Conductive blind hole

27. . . First insulating protective layer

270. . . Opening

28. . . Second insulating protective layer

29,29’. . . Surface treatment layer

30,30’. . . Solder material

1A to 1C are schematic cross-sectional views showing a conventional method of fabricating a package substrate; wherein the 1C' is another embodiment of FIG. 1C;

2A to 2J are schematic cross-sectional views showing a first embodiment of a package substrate structure and a method of manufacturing the same according to the present invention; wherein the 2F', 2G', and 2J' patterns are another of the 2F, 2G, and 2J patterns, respectively. Implementation aspect;

3A to 3C are cross-sectional views showing a second embodiment of the package substrate structure and the method of manufacturing the same according to the present invention; wherein the 3C' is another embodiment of the 3Cth diagram.

20. . . Substrate body

twenty one. . . Internal circuit layer

211. . . Electrical connection pad

twenty two. . . Dielectric layer

220. . . Opening

25. . . Circuit layer

251. . . Conductive blind hole

252. . . Electrical contact pad

26. . . Conductive bump

27. . . First insulating protective layer

270. . . Opening

28. . . Second insulating protective layer

Claims (10)

A package substrate structure includes: a substrate body having an inner circuit layer disposed on at least one surface thereof, wherein the inner circuit layer has a plurality of electrical connection pads; and the dielectric layer is disposed on the substrate body and the inner circuit layer And a plurality of openings for respectively exposing the electrical connection pads; the circuit layer is disposed on the dielectric layer, and a conductive blind hole is disposed in the opening to electrically connect to the electricity a connection pad, and the circuit layer has a plurality of electrical contact pads; a plurality of conductive bumps are correspondingly disposed on the respective electrical contact pads; a first insulating protective layer is disposed on the dielectric layer and the circuit layer, and Having at least one opening to expose the electrical contact pads and the conductive bumps thereon; and a second insulating protective layer disposed in the opening, wherein the second insulating protective layer has a thickness smaller than the first insulating protection The height of each of the conductive bumps is higher than the thickness of the second insulating protective layer, so that each of the conductive bumps is exposed to the second insulating protective layer. The package substrate structure of claim 1, wherein the exposed conductive bumps are provided with a surface treatment layer. The package substrate structure of claim 2, wherein the material for forming the surface treatment layer is gold, silver, electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel palladium immersion Gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin. For example, the package substrate structure of the first application of the patent scope includes a solder material disposed on the conductive bump. A method for fabricating a package substrate structure includes: providing a substrate body, forming an internal circuit layer on at least one surface thereof, and the internal circuit layer has a plurality of electrical connection pads; forming a dielectric on the substrate body and the internal circuit layer a plurality of openings are formed in the dielectric layer to respectively expose the electrical connection pads; a circuit layer is formed on the dielectric layer, and conductive via holes are formed in the openings to electrically connect to The electrical connection pad, the circuit layer has a plurality of electrical contact pads; conductive bumps are respectively formed on the electrical contact pads; a first insulating protective layer is formed on the dielectric layer and the circuit layer, and the first Forming at least one opening in the insulating protective layer to expose the electrical contact pads and the conductive bumps thereon; and forming a second insulating protective layer in the opening, wherein the second insulating protective layer has a thickness smaller than the first The insulating protective layer, and the height of each of the conductive bumps is higher than the thickness of the second insulating protective layer, so that each of the conductive bumps is exposed to the second insulating protective layer. The method for manufacturing a package substrate structure according to claim 5, further comprising forming a surface treatment layer on the exposed conductive bumps. The method for manufacturing a package substrate structure according to claim 6, wherein the material for forming the surface treatment layer is gold, silver, electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel Peptide immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin. The method for manufacturing a package substrate structure according to claim 5, wherein the circuit layer and the conductive bump are formed on the dielectric layer, the hole wall of the opening, and the electrical contact pad in the opening. Forming a conductive layer; forming a first resist layer on the conductive layer, and forming a plurality of open resist regions in the first resist layer, and a portion of the resist opening region corresponding to the openings of the dielectric layers, The conductive layer is exposed in the open area of the resist layer; the circuit layer is plated on the conductive layer in each open area of the resist layer, and the conductive blind hole is formed in the opening of the dielectric layer to be electrically connected to the conductive layer An inner circuit layer, wherein the circuit layer has a plurality of electrical contact pads; a second resist layer is formed on the first resist layer and the circuit layer, and a plurality of resistive layer openings are formed in the second resist layer to respectively The electrical contact pad is plated on the electrical contact pads in each of the barrier openings to form conductive bumps; and the second resist layer, the first resist layer and the conductive layer covered thereon are removed. The method of fabricating a package substrate structure according to claim 8 , wherein the step of forming the conductive bump is further included on the conductive bump to form a solder material. The method of fabricating a package substrate structure according to claim 8 , wherein the aperture of the barrier layer is larger or smaller than the size of the electrical contact pad.