TWI478312B - Stack package substrate - Google Patents

Description

Stacked package structure

The present invention relates to a semiconductor structure, and more particularly to a stacked package structure.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. At present, a package substrate for carrying a semiconductor wafer includes a wire-bonded package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA); and is required for operation of a microprocessor, a wafer set, and a graphics chip. Packaged substrates with wiring also need to improve the quality of the transmitted chip signals, improve the bandwidth, control impedance and other functions in order to cope with the development of high I / O number of packages.

In the current packaging technology, a semiconductor wafer is electrically connected to a package substrate, and an electronic pad is disposed on a surface of the semiconductor integrated circuit (IC) wafer, and the package substrate has corresponding electrical properties. Contact pads, and conductive bumps, other conductive adhesive materials or gold wires may be appropriately disposed between the semiconductor wafer and the package substrate to electrically connect the semiconductor wafer to the package substrate.

In today's packaging technology, in order to meet the requirements of multi-function, high-actuation power, a package structure product in which semiconductor packages are stacked on each other is derived.

Referring to FIG. 1 , it is a schematic cross-sectional view of a conventional stacked package structure; as shown, a plurality of package structures 1 , 1 ′ are provided, the package structure 1 having a first surface 10 a and a second surface 10 b . A plurality of first electrical contact pads 101 are disposed on the first surface 10a of the package substrate 10, and a plurality of second electrical contact pads 102 are disposed on the second surface 10b. The first electrical contact pads 101 are disposed on the first surface 10b. Correspondingly, the semiconductor wafer 11 having the electrode pads 110 is disposed, and the solder bumps 12 are respectively formed on the first electrical contact pads 101, and the conductive bumps 13 are formed on the electrode pads 110 of the semiconductor wafer 11 to make the semiconductor The conductive bumps 13 of the wafer 11 are electrically connected to the solder bumps 12 of the package substrate 10, and the underfill material 14 is filled between the semiconductor wafer 11 and the package substrate 10 to form the package structure 1; The solder balls 2 are respectively formed on the second electrical contact pads 102 of the second surface 10b of the package substrate 10, and the first surface 10a of the package substrate 10' of the other package structure 1' has a plurality of corresponding packages. The third electrical contact pad 103 of the second electrical contact pad 102 of the structure 1, The solder balls 2 are electrically connected to the third electrical contact pads 103 to stack and electrically connect the package structure 1 to the other package structure 1'.

The third electrical contact pads 103 on the package substrate 10' are closely arranged and formed in the third package. The solder mask of the electrical contact pad 103 has a narrow opening, and the center of the solder ball 2 is not completely corresponding to the central portion of the third electrical contact pad 103 of the package structure 1', and is slightly offset. In the case where the electrical connection is achieved by the reflow process, the solder balls 2 are not completely accurately placed in the central portion of the third electrical contact pad 103, resulting in the solder balls 2 and the third electrical properties. Stress may occur between the contact pads 103 or between the solder balls 2 and the second electrical contact pads 102, which may cause the solder balls 2 and the second electrical contact pads 102 or the solder balls 2 to The interface between the third electrical contact pads 103 is prone to breakage and peeling, thus affecting the electrical connection.

In addition, when applied to a package stack structure with a high wiring density, since the solder balls 2 are spherical after being reflowed, the solder balls 2 may be too small in pitch and the ball diameter is too large, resulting in the solder balls. The occurrence of mutual bridging between 2 occurs.

Therefore, how to provide a package substrate and a package structure to avoid the prior art, in the fine pitch layout of high-density wiring, because the solder ball is not completely accurately placed in the central portion of the third electrical contact pad The stress causes the lack of fracture and peeling between the solder ball and the electrical contact pad, and the problem that the solder ball is bridged to each other due to the excessive diameter of the solder ball and the small spacing between the solder balls has become a problem. The problem that needs to be overcome.

In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a stacked package structure, which can avoid the problem of occurrence of eccentric stress between the electrical connection structures in the reflow process and the bridge connection short circuit of the electrical connection structure.

To achieve the above and other objects, the present invention provides a stacked package structure in which a first package is stacked on a second package, the first package being attached to a first package substrate having a first surface and a second surface. a first semiconductor wafer is mounted on the first surface, and the second package is attached to the second surface of the second package substrate having the third surface and the fourth surface, and the second semiconductor wafer is attached to the first surface. The second surface of the package substrate is electrically connected to the third surface of the second package substrate by an electrical connection structure, and the electrical connection structure comprises: a plurality of implant pads disposed on the second surface; the plurality of metals The buffer layer is correspondingly disposed on each of the pillar pads, and the material forming the metal buffer layer is a solder material; and the plurality of bumps are correspondingly disposed on each of the metal buffer layers, and the melting point of the pillar is higher than The metal buffer layer.

According to the above-mentioned stacked package structure, the first and second semiconductor wafers are electrically connected to the first and second package substrates by a wire bonding structure or a flip chip structure; the material forming the solder material is a low melting point metal. The material of the low melting point metal layer is tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / copper (Cu), tin (Sn) / silver (Ag), tin (Sn) / zinc (Zn), or tin (Sn) / indium (In); the material forming the stud is one of a group consisting of aluminum (Al), copper (Cu), and nickel (Ni).

According to the above, the barrier layer is formed between the metal buffer layer and the pillar pad, and the material forming the barrier layer is nickel (Ni).

In addition, according to the above, the soldering material is formed on the protruding post or a surface treatment layer is formed on the exposed surface of the protruding post, and the material forming the surface treating layer is electroplated nickel/gold, electroless nickel/gold plating. Nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin.

And further comprising: a first insulating protective layer formed on the second surface of the first package substrate and exposing the studs; or the first insulating protective layer is formed on the first package substrate The second surface and the side surfaces of the plurality of pillars expose the top surfaces of the pillars; and a solder material is formed on the top surface of the pillars.

According to the above, the contact pad is disposed on the third surface of the second package substrate and corresponding to each of the protrusions, and the contact pads are provided with a solder material.

The present invention provides another stacked package structure, the electrical connection structure is disposed on the third surface of the second package substrate; and the first insulation protection layer is formed on the third package substrate. Forming, and exposing the protrusions; or the first insulating protection layer is formed on the third surface of the second package substrate and the side surfaces of the protrusions, and exposing the top surfaces of the protrusions; The top surface forms a solder material.

According to the above, the contact pad is disposed on the second surface of the first package substrate and corresponding to each of the protrusions, and the contact pads are provided with a solder material.

The stacked package structure of the present invention mainly comprises forming a metal buffer layer of a low melting point metal on the pillar pad of the first or second package substrate, and forming a pillar of a high melting point metal on the metal buffer layer to form the pillar by the metal The buffer layer is first melted in the reflow process compared to the stud, so that the stud can be elastically deflected by the first molten metal buffer layer during the reflow process, so that the studs are During the cooling process of the metal buffer layer, the stress caused by the offset is avoided, and the bumps are not spherically formed after the solder balls are reflowed, and the distance between the solder balls and the solder balls is reduced to cause bridging. The problem of short circuit can avoid the lack of conventional technology.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

[First Embodiment]

FIG. 2A is a cross-sectional view showing a first embodiment of the stacked package structure of the present invention. As shown in the figure, the stacked package structure includes a first package 3 and a second package 4, and the first The package 3 is stacked on the second package 4, wherein the first package 3 is attached to the first surface 31a of the first package substrate 31 having the first surface 31a and the second surface 31b. a semiconductor wafer 32, and the second package 4 is attached to the third surface 41c of the second package substrate 41 having the third surface 41c and the fourth surface 41d, and the second semiconductor wafer 42 is attached to the first package. The second surface 31b of the substrate 31 is electrically connected to the third surface 41c of the second package substrate 41 by the electrical connection structure 33. The first package substrate 31 and the second package substrate 41 have a plurality of conductive lines inside and The structure of electrically connected conductive vias and or conductive blind vias (not shown). There are many process technologies for forming a conductive line, a conductive via, and a conductive blind via a package substrate, but it is a well-known process technology in the industry, which is not a technical feature of the present invention and therefore will not be further described.

The electrical connection structure 33 includes a plurality of pillar pads 331 , a plurality of metal buffer layers 332 , and a plurality of pillars 333 .

The plurality of implant pads 331 are disposed on the second surface 31b of the first package substrate 31. The metal buffer layers 332 are correspondingly disposed on the implant pads 331 and the metal buffer layer 332 is formed. The material is a solder material, and the material forming the solder material may be a low melting point metal, and the material of the low melting point metal layer may be tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / Copper (Cu), tin (Sn) / silver (Ag), tin (Sn) / zinc (Zn), or tin (Sn) / indium (In); and the studs 333, corresponding to each of the metals The buffer layer 332 has a higher melting point than the metal buffer layer 332. The material forming the protrusion 333 may be a group of aluminum (Al), copper (Cu), and nickel (Ni). One.

The first semiconductor wafer 32 and the second semiconductor wafer 42 are electrically connected to the first package substrate 31 and the second package substrate 41 by a wire bonding structure (not shown) or a flip chip structure.

According to the above, the contact pad 410 is disposed on the third surface 41c of the second package substrate 41, and corresponding to each of the protrusions 333, a solder material 43 may be disposed on the contact pad 410. The stud 333 is electrically connected by the solder material 43.

[Second embodiment]

FIG. 2B is a cross-sectional view showing a second embodiment of the stacked package structure of the present invention. The difference from the previous embodiment is that the electrical connection structure 33 is disposed on the third surface 41c of the second package substrate 41. The electrical connection structure 33 includes a plurality of implant pads 331 , a plurality of metal buffer layers 332 , and a plurality of bumps 333 , and the implant pads 331 are disposed on the third surface 41 c of the second package substrate 41 . The contact pad 410 is disposed on the second surface 31b, and the rest is the same for the metal buffer layer 332 and the protrusion 333, and details are not described herein.

In addition, according to the first and second embodiments, the fourth surface 41d of the second package substrate 41 is provided with a plurality of ball pads 411, and the ball pad 411 can form a solder ball or a pin (Fig. It is not shown in the formula), and the solder ball or pin is electrically connected to other electronic devices; and there are many techniques for forming solder balls or pins on the ball pad to electrically connect other electronic devices, but it is well known in the industry. The process technology is not a technical feature of this case, so it will not be repeated.

The stacked package structure of the present invention is formed on each of the pillar pads to form a metal buffer layer, and a pillar is formed on the metal buffer layer, and the metal buffer layer of the low melting point metal is used for the high melting point in the reflow process. The metal studs are first melted, so that the studs can be elastically deflected by the first molten metal buffer layer during the reflow process, so that the studs are avoided during the cooling process of the metal buffer layers. Due to the stress generated by the offset, and the posts are not spherically known after the reflow, the distance between the solder balls and the solder balls is reduced to cause a bridge short circuit, thereby avoiding the conventional knowledge. The lack of technology.

Referring to FIG. 3A and FIG. 3B , the electrical connection structure 33 may include a barrier layer 34 formed between the metal buffer layer 332 and the pillar pad 331 to form the barrier layer. The material of 34 is nickel (Ni).

Referring to FIGS. 4A and 4B, the difference from the above embodiment is that a solder material 35 is formed on the stud 333.

Referring to FIGS. 5A and 5B, the difference from the foregoing embodiment is that the surface treatment layer 36 is formed on the exposed surface of the stud 333, and the material forming the surface treatment layer 36 is electroplated nickel/gold, electroless nickel plating/ Gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin.

Referring to FIGS. 6A and 6B , the difference from the foregoing embodiment is that an insulating protective layer 37 is formed on the package substrate 31 and the studs 333 are exposed.

Referring to FIGS. 7A and 7B , the difference from the above embodiment is that the insulating protection layer 37 can be formed on the side of the protrusions 333 and expose the top surfaces of the protrusions 333 .

Referring to FIGS. 8A and 8B, the difference from the above embodiment is that the top surface of the stud 333 forms a solder material 35.

The package structure of the present invention is electrically connected to the first and second semiconductor wafers respectively by a wire bonding structure or a flip chip structure on the first surface of the first package substrate and the third surface of the second package substrate. The electrical connection structure of the second surface of the first package substrate or the third surface of the second package substrate is formed on the pillar pad to form a metal buffer layer of a low melting point metal, and a high melting point is formed on the metal buffer layer The metal stud is first melted in the reflow process by the metal buffer layer, so that the stud can provide elastic deflection by the first molten metal buffer layer in the reflow process So that the pillars are prevented from being stressed by the offset during the cooling process of the metal buffer layers, and the pillars are not spherically formed after the solder balls are reflowed, resulting in solder balls. The problem that the distance between the ball and the solder ball becomes smaller causes a bridge short circuit, thereby avoiding the lack of the prior art.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

1, 1’. . . Package structure

10, 10', 31. . . Package substrate

101. . . First electrical contact pad

102. . . Second electrical contact pad

103. . . Third electrical contact pad

10a, 31a. . . First surface

10b, 31b. . . Second surface

11. . . Semiconductor wafer

110. . . Electrode pad

12. . . Solder bump

13. . . Conductive bump

14. . . Bottom filling material

2. . . Solder balls

3. . . First package

31. . . First package substrate

32. . . First semiconductor wafer

33. . . Electrical connection structure

331. . . Plant pad

332. . . Metal buffer layer

333. . . Tab

34. . . Barrier layer

35, 43. . . Welding materials

36. . . Surface treatment layer

37. . . Insulating protective layer

4. . . Second package

41. . . Second package substrate

41c. . . Third surface

41d. . . Fourth surface

410. . . Contact pad

411. . . Ball pad

42. . . Second semiconductor wafer

1 is a schematic cross-sectional view of a conventional stacked package structure;

2A and 2B are cross-sectional views showing an embodiment of the stacked package structure of the present invention;

3A and 3B are cross-sectional views showing a first embodiment of the electrical connection structure of the present invention;

4A and 4B are cross-sectional views showing a second embodiment of the electrical connection structure of the present invention;

5A and 5B are schematic cross-sectional views showing a third embodiment of the electrical connection structure of the present invention;

6A and 6B are cross-sectional views showing a fourth embodiment of the electrical connecting structure of the present invention;

7A and 7B are cross-sectional views showing a fifth embodiment of the electrical connection structure of the present invention;

8A and 8B are cross-sectional views showing a sixth embodiment of the electrical connecting structure of the present invention.

3. . . First package

31. . . First package substrate

31a. . . First surface

31b. . . Second surface

32. . . First semiconductor wafer

33. . . Electrical connection structure

331. . . Plant pad

332. . . Metal buffer layer

333. . . Tab

4. . . Second package

41. . . Second package substrate

41c. . . Third surface

41d. . . Fourth surface

410. . . Contact pad

411. . . Ball pad

42. . . Second semiconductor wafer

43. . . Welding materials

Claims (22)

A stacked package structure is configured by stacking a first package onto a second package, the first package being attached to the first surface of the first package substrate having the first surface and the second surface a second semiconductor wafer is mounted on the third surface of the second package substrate having the third surface and the fourth surface, and the second surface of the first package substrate is electrically connected The structure is electrically connected to the third surface of the second package substrate, and the electrical connection structure comprises: a plurality of implant pads disposed on the second surface; and a plurality of metal buffer layers corresponding to each of the implants The material of the metal buffer layer is a solder material; the plurality of bumps are correspondingly disposed on each of the metal buffer layers, and the melting point of the protruding column is higher than the metal buffer layer; and the first insulating protective layer The surface of the first insulating protective layer is flush with the top surface of the studs to expose the top surfaces of the studs on the second surface of the first package substrate and the side surfaces of the pillars. The stacked package structure of claim 1, wherein the first and second semiconductor wafers are electrically connected to the first and second package substrates by a wire bonding structure or a flip chip structure. The stacked package structure of claim 1, wherein the material forming the solder material is a low melting point metal, and the material of the low melting point metal is tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / copper (Cu), tin (Sn) / silver (Ag), tin (Sn) / zinc (Zn), or tin (Sn) / indium (In). The stacked package structure of claim 1, wherein the material forming the stud is one of a group consisting of aluminum (Al), copper (Cu), and nickel (Ni). For example, the stacked package structure of claim 1 includes a barrier layer formed between the metal buffer layer and the implant pad. The stacked package structure of claim 5, wherein the material forming the barrier layer is nickel (Ni). The stacked package structure of claim 1 or 5, comprising a solder material, is formed on the top surface of the stud. The stacked package structure of claim 1 or 5, further comprising a surface treatment layer formed on the exposed surface of the stud. The stacked package structure of claim 8 , wherein the material for forming the surface treatment layer is electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), and nickel-palladium immersion gold (ENEPIG). , electroless tin plating (Immersion Tin) or electroplating tin. The stacked package structure of claim 1 , further comprising a contact pad disposed on the third surface of the second package substrate and corresponding to each of the protrusions. For example, the stacked package structure of claim 10, including the solder material, is disposed on the contact pads. A stacked package structure is configured by stacking a first package onto a second package, the first package being attached to the first surface of the first package substrate having the first surface and the second surface a wafer, and the second package is attached to the second surface and the second surface a second semiconductor wafer is mounted on the third surface of the package substrate, and a third surface of the second package substrate is electrically connected to the second surface of the first package substrate by an electrical connection structure, and the electrical connection structure The system includes: a plurality of planting pad pads disposed on the third surface; a plurality of metal buffer layers correspondingly disposed on each of the planting column pads, and the material forming the metal buffer layer is a solder material; the plurality of protruding columns are Correspondingly disposed on each of the metal buffer layers, and the melting point of the protruding pillar is higher than the metal buffer layer; and the first insulating protective layer is formed on the second surface of the first package substrate and the side surfaces of the pillars, The first insulating protective layer surface is flush with the top surfaces of the studs to expose the top surfaces of the studs. The stacked package structure of claim 12, wherein the first and second semiconductor wafers are electrically connected to the first and second package substrates by a wire bonding structure or a flip chip structure. The stacked package structure of claim 12, wherein the material forming the solder material is a low melting point metal, and the material of the low melting point metal is tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / copper (Cu), tin (Sn) / silver (Ag), tin (Sn) / zinc (Zn), or tin (Sn) / indium (In). The stacked package structure of claim 12, wherein the material forming the stud is one of a group consisting of aluminum (Al), copper (Cu), and nickel (Ni). For example, the stacked package structure of claim 12 includes a barrier layer formed between the metal buffer layer and the pillar pad. The stacked package structure of claim 16, wherein the material forming the barrier layer is nickel (Ni). The stacked package structure of claim 12 or 16 further comprises a solder material formed on a top surface of the stud. The stacked package structure of claim 12 or 16, further comprising a surface treatment layer formed on the exposed surface of the stud. The stacked package structure of claim 19, wherein the material for forming the surface treatment layer is electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), Electroless tin plating (Immersion Tin) or electroplating tin. The stacked package structure of claim 12, further comprising a contact pad disposed on the second surface of the first package substrate and corresponding to each of the protrusions. The stacked package structure of claim 21, comprising a solder material, is disposed on the contact pads.