M347677 八、新型說明： 【新型所屬之技術領域】 本創作係有關於-種封裝基板，尤指一種具有長方步 或its]形㈣之電性連接結構之封裝基板。 / 【先前技術】 在半導體封裝製程中，覆晶式⑻ip Chip)係為—種 因應南密度線路之需求所發展出的半導體晶片封裝技 術:其係於封裝基板之電性接觸塾上形成導電元件或其他 具導電性之結合材料，並在足以使導電元絲融之迴焊溫 度下’將導電it件迴焊以結合至半導體晶片之電極塾上， 使半導體晶片電性連接封裝基板。 請參閱第1A、18圖，習知覆晶式封裝件係包括：具 有線路層100及複數電性接觸墊101之基板主H 10、設 於基板主體10、線路層1〇〇及電性接觸墊1〇1上之防焊M347677 VIII. New Description: [New Technology Field] This creation is about a kind of package substrate, especially a package substrate with a long-range or electric connection structure. / [Prior Art] In the semiconductor packaging process, the flip-chip (8) ip chip is a semiconductor chip packaging technology developed in response to the demand of the south density line: it forms a conductive element on the electrical contact 封装 of the package substrate. Or a conductive bonding material, and re-welding the conductive member to the electrode electrode of the semiconductor wafer at a reflow temperature sufficient to melt the conductive wire to electrically connect the semiconductor wafer to the package substrate. Please refer to FIGS. 1A and 18 . The conventional flip chip package includes: a substrate main H 10 having a circuit layer 100 and a plurality of electrical contact pads 101 , a substrate body 10 , a circuit layer 1 , and electrical contacts. Anti-welding on pad 1〇1
層11、設於防焊層11上之半導體晶片13、以及如第1A 圖所示之設於防焊層u及半導體晶片13之間之底膠 (Underfill) 15、或如第1β圖所示之包覆基板主體⑺ 具半導體晶片13之-側之封模塑脂（molding resin) 16 ’且該封模塑脂16並填人防焊層u及半導體晶片u 之間。該防焊層11設有複數開孔11〇，以顯露各該電性 接觸塾101，.亥半導體晶片13具有複數電極整，且各 該電性接觸塾1 01藉由球狀焊料凸塊14，以對應電性連 接各該電極墊130’俾使該半導體晶# 13f性連接基板 主體10。 M347677 惟，該電性接觸墊101、該開孔110、及該焊料凸塊 14位於防焊層11上之輪廓均為圓形，如第lc圖所示， •在細凸塊間距的要求下，需製作較小之開孔11〇，不僅提 β高對位精度之難度，且焊料凸塊14與電性接觸墊1〇1之 '接著面積變小，導致結合力下降。舉例而言，開孔11〇 的孔徑是80#m，若開孔11〇與電性接觸墊1〇1之對位允 許公差為±20/zm，則電性接觸墊1〇1的寬度不可小於 籲/zm，因此若欲將電性接觸墊1〇1之寬度製成小於12〇#瓜， 則開孔110的孔徑亦需小於8〇 ^ m，但受限於顯露於防焊 層11開孔110中之電性接觸墊1〇1面積必須提供與焊料 凸塊14間足夠之結合力，則該開孔11〇的孔徑不易製成 小於80//m之尺寸，俾使製程上難以再縮小電性接觸墊 1 〇 1之覓度，以致於難以達到再縮小細間距的需求。 若能縮小電性接觸墊101之寬度，雖能相對縮小墊距 (pad pitch)dl ,卻將使焊料凸塊14之尺寸相對縮小，而 _使防焊層11及半導體晶片13之間之空隙變小，導致提高 底膠15填充或採用液態模封方式（liquidm〇lding，㈣π molding)之困難度。此外，於封裝時，亦將提高半導體 晶片13之電極墊13 〇對位之困難度。 因此，為配合成本考量，業界雖已陸續採用液態模封 方式作覆晶式產品之封裝’但面臨最大問題係為焊料凸塊 尺寸變化（間距縮小、高度變低）時之封裝困難，及封膠 不易注入間隙中而衍生品質可靠度等問題；故，習知技術 之種種問題實已成為目前業界所亟待克服的難題。 6 M347677 【新型内容】 鑒於上述習知技術的缺點，本創作之主要目的在於提 供一種利於細間距需求之封裝基板。 、 為達上揭目的及其他目的，本創作提供一種封裝基 =括.基板主體，係具有線路層及電性連接該線路 二=電性接觸墊’且該電性接觸墊之輪廓係為長方形 =开厂防焊層，係設於該基板主體、線路層及電性接 ㈣上’且具有複數開孔’以對應顯露電性接觸塾，而該 為長方形或橢圓形;以及金屬凸塊，係設： 接觸墊上且突出防烊層，該金屬凸塊位於防焊 層上之輪廓係為長方形或橢圓形。 #後2述Γ4,前述之基板主體係可為具有核心層之多 ^線路板’亦或復可具有㈣㈣及導電通孔4前述之 路。 泠電目孔，以氧性連接導電通孔及内層線 上述結構中，前述之金屬凸塊係可由例如錫、银、 銅、鎳/金、鎳/絶/金、或上述之組合 採 鍍或電鍍方式形成。 儿』抹化The layer 11, the semiconductor wafer 13 provided on the solder resist layer 11, and the underfill 15 disposed between the solder resist layer u and the semiconductor wafer 13 as shown in FIG. 1A, or as shown in the first β-graph The coated substrate body (7) has a molding resin 16' on the side of the semiconductor wafer 13, and the molding compound 16 is filled between the solder resist layer u and the semiconductor wafer u. The solder resist layer 11 is provided with a plurality of openings 11 〇 to expose the respective electrical contacts 101. The semiconductor wafer 13 has a plurality of electrodes, and each of the electrical contacts 110 is formed by a spherical solder bump 14 The semiconductor wafer 130 is electrically connected to the electrode pad 130 ′ to electrically connect the substrate body 10 . M347677 only, the electrical contact pad 101, the opening 110, and the solder bump 14 are located on the solder resist layer 11 in a circular shape, as shown in the figure lc, • at the requirement of the fine bump pitch It is necessary to make a small opening 11〇, which not only improves the difficulty of β high alignment accuracy, but also reduces the bonding area of the solder bump 14 and the electrical contact pad 1〇1, resulting in a decrease in bonding strength. For example, the aperture of the opening 11〇 is 80#m, and if the alignment tolerance of the opening 11〇 and the electrical contact pad 1〇1 is ±20/zm, the width of the electrical contact pad 1〇1 cannot be Less than y / zm, so if the width of the electrical contact pad 1 〇 1 is made less than 12 〇 # melon, the aperture of the opening 110 also needs to be less than 8 〇 ^ m, but limited by the exposed solder mask 11 The area of the electrical contact pad 1〇1 in the opening 110 must provide sufficient bonding force with the solder bumps 14, and the aperture of the opening 11〇 is not easily made into a size smaller than 80//m, which makes the process difficult. The thickness of the electrical contact pad 1 〇 1 is further reduced, so that it is difficult to achieve the need to reduce the fine pitch. If the width of the electrical contact pad 101 can be reduced, the pad pitch dl can be relatively reduced, but the size of the solder bump 14 is relatively reduced, and the gap between the solder resist layer 11 and the semiconductor wafer 13 is made. Smaller, resulting in increased difficulty in filling the primer 15 or using liquid molding (liquid molding). In addition, the difficulty of aligning the electrode pads 13 of the semiconductor wafer 13 is also improved at the time of packaging. Therefore, in order to meet the cost considerations, the industry has gradually adopted the liquid mold sealing method as the package of the flip chip type product. However, the biggest problem is the packaging difficulty when the solder bump size is changed (the pitch is reduced, the height is lowered), and the package is difficult. The problem that the glue is not easily injected into the gap and the quality reliability is derived; therefore, the problems of the prior art have become a difficult problem to be overcome in the industry. 6 M347677 [New Content] In view of the above shortcomings of the prior art, the main purpose of this creation is to provide a package substrate that is advantageous for fine pitch requirements. In order to achieve the purpose and other purposes, the present invention provides a package base = a substrate body having a circuit layer and electrically connecting the line 2 = electrical contact pad 'and the outline of the electrical contact pad is a rectangle The factory solder mask is provided on the substrate body, the circuit layer and the electrical connection (4) and has a plurality of openings to correspond to the exposed electrical contact 塾, which is rectangular or elliptical; and the metal bumps, The utility model is characterized in that: the contact pad is protruded and the anti-mite layer is protruded, and the outline of the metal bump on the solder resist layer is rectangular or elliptical. #后第二述4, the foregoing substrate main system may be a plurality of circuit boards having a core layer or may have (4) (four) and conductive vias 4 as described above. In the above structure, the metal bumps may be made of, for example, tin, silver, copper, nickel/gold, nickel/absolute/gold, or a combination thereof. The plating method is formed. Wipe
依上述結構，該封裝基板復可包括表 W 於金屬凸塊之表面，其係可例如^⑽ 化錄/飽/金、電錄錄/金、錫錯（SnPb)、 、錫銀（SnAg)、上述之組合、或有機保焊 由上可知，本創作封裝基板藉由將電性接觸整、防焊 7 r M347677 層開孔、及金屬凸塊之輪 電性接觸塾具有長、短= :::為長方形或橢圓形’使該 縮減墊距及開孔寬度，在^寸^ ’其^邊方向有利於 之知失，以提供電性接觸墊盥 、 而可達到細間距… 塊間足夠之結合力， 择 而，目的，或者，若不縮小墊距，則可 二立二Γ咖之空間以佈設較多線路，並且在相同封 精度的製程能力下較容易完成接點的對位。 半導：ta 凸塊於調整高度且具較佳共面性，與 π為長方形或擴圓形，相較於習知技術，更有利；= 體晶片間之間距縮小及底膠或模封塑脂填充：質 二:;】可縮小封裝結鉢^ 以下藉由特定的具體實施例說明本創作之實施方 =本創作所屬技術領域中具有通常知識者可由本說明書 斤揭不之内容輕易地瞭解本創作之其他優點及功效。 Μ 2㈣2圖’糊作提供—軸裝基板，係包括： 基板主體20、防焊声w、LV κρ 主體係為具有核心m二m^述之基板 缞敗r 土㈤、 夕9線路板，且内部具有内層 芦2〇〇 ^式）及導電通孔（未圖式），而表面具有線路 二=層2:1具有複數_^ 、 笔丨生連接V電通孔及内層線路。 ^ ’有關於封裝基板之基板主體2〇之種類繁多，惟 斤周知，且其並非本案技術特徵，故圖示僅繪製相 8 M347677 關結構、，而非用以限制本創作，俾不再贊述，特此述明。 , 所述之防綷層21设於基板主體20、線路層200及各 ^該電度接觸墊201上，且具有複數開孔210，以對應顯露 各該電性接觸塾201 ;所述之金屬凸塊22設於顯露之電 ,性接觸整201±’且突出該防焊層21表面，該金屬凸塊 t 22之材料為錫（Sn)、銀（Ag)、金（Au)、銅（Cu)、鎳/金 (Ni/Au)、鎳/鈀/金（Ni/Pd/Au)、或上述之組合之其中一 籲者，且採化鍍或電鍍方式形成，於本實施例甲，該金屬凸 塊2 2之材料係為銅。 所述之電性接觸墊2〇 1及金屬凸塊22之尺寸係大於 開孔210之尺寸，或等於開孔21〇之尺寸（未圖式），且 電性接觸墊201之尺寸係大於金屬凸塊22之尺寸，或等 於金屬凸塊22之尺寸（未圖式）。 請一併參閱第3A至3D圖，於本實施例中，該電性接 觸墊2 01之輪麼係為長方形及橢圓形之其中一者，該開孔 _ 210之輪廓係對應電性接觸墊2〇1之輪廓而呈長方形及橢 圓形之其中一者，且該金屬凸塊22位於防焊層21上之輪 廓為圓形（未圖式）、長方形及橢圓形之其中一者，且電 性接觸墊201、開孔210及金屬凸塊22三者之形狀可交 互搭配，以配合不同細間距需求及對位精度之需要。 當應用於細間距線路的封裝基板時，本創作藉由將開 孔210及電性接觸墊2〇 1輪廓製成長方形或橢圓形，以具 有長、短兩邊之特性，其在短邊方向有利於縮減墊距 (d2<dl，dl見第ία、1B圖，d2見第2圖）及開孔21〇寬 9 M347677 度，在長邊方向則補償短邊對開孔210面積之損失，以提 供電性接觸墊201與金屬凸塊22間足夠之結合力，而可 達到細間距需求之目的，或者在不縮小墊距d2之情況 下，可有效增加電性接觸墊201間之空間以佈設較多線路。 . 請一併參閱第4圖，該封裝基板復包括表面處理層 220，係設於金屬凸塊22之表面，其係為化錫（Sn)、化銀 • (Ag)、化金（Au)、電鍍錫、化鎳/金、化鎳/纪/金、電鍍 籲鎳/金、錫鉛（SnPb)、錫銀銅（SnAgCu)、錫銀（SnAg)、上 述之組合、或有機保焊膜（〇sp)。 。月一併參閱第5A、5B圖，係為應用本發明封裝基板 之封裝結構，如第5Α圖所示之結構復包括設於封裝基板 上之半^體晶片23、以及設於封裝基板之防焊層21與該 半導體晶片23之間之底膠25 ;或者如第5β圖所示，以 封模塑脂26包覆封裝基板具半導體晶片23之一側，並填 入防焊層21及半導體晶片23之間；所述之半導體晶片、 鲁23具有複數電極墊23〇,透過焊料“以電性H士 基板之金屬凸塊22。 封衣 ,當應於於封裝製程時，金屬凸塊22之輪廓設計為長 方形或橢圓形，在相同封裝對位精度的製程能力 完成接點的對位。 再者，本創作藉由使用金屬凸塊22將可減少谭料Μ ，使用，且金屬凸塊22之高度與體積均易於調控 及半導體晶片23之間之空隙為所要求之尺寸，並 △差軟小而具較佳共面性，與半導體晶片23形成電性 10 M347677 接點以提供較佳之可靠度，且金屬凸塊22位於防谭層21 上之輪廓亦可為長方形或橢圓形，相較於習知技術，更有 ,利方；基板主體2〇與半導體晶片23間之間距縮小及底膠 # 25或封模塑脂26填充品質之可靠度，俾有效縮小封裝結 構厚度，而符合薄小化需求。 综上所述’本創作藉由電性接觸墊之輪廓係為長方形 或橢圓形，该防焊層之開孔之輪廓呈長方形或橢圓形，且According to the above structure, the package substrate may include a surface of the metal bump, which may be, for example, ^10 (10) chemical recording/saturated/gold, electric recording/gold, tin-spot (SnPb), tin-silver (SnAg). The combination of the above, or the organic welding can be seen from the above, the original package substrate is made of electrical contact, anti-welding 7 r M347677 layer opening, and the metal bumps of the ferroelectric contact 塾 have length and short =: :: is rectangular or elliptical 'to make the reduced pad distance and opening width, in the ^ inch ^ 'the direction of the ^ is beneficial to know, to provide electrical contact pads, and can achieve fine pitch... The combination of force, choice, purpose, or, if the pad distance is not reduced, the space of the two cafés can be set up to lay more lines, and the alignment of the contacts can be easily completed under the process capability of the same sealing precision. Semi-conducting: ta bumps are height-adjusted and have better coplanarity, and π is rectangular or expanded, which is more advantageous than conventional techniques; = shrinkage between body wafers and undercoat or mold-sealing Grease filling: quality 2:;] can reduce the package of the package ^ The following describes the implementation of the creation by a specific embodiment = the general knowledge in the technical field of the present invention can be easily understood by the contents of this manual Other advantages and effects of this creation. Μ 2 (4) 2 Figure 'Provided to provide - shaft mounted substrate, including: substrate body 20, welding proof sound w, LV κρ main system is the core m m m described substrate 缞 r r soil (five), eve 9 circuit board, and The inner layer has an inner layer of reed type and a conductive through hole (not shown), and the surface has a line 2 = layer 2:1 has a complex number _^, a pen-connected V-electrode hole and an inner layer line. ^ 'There are many kinds of substrate bodies 2 about the package substrate, but they are well known, and they are not technical features of this case. Therefore, the diagram only draws the phase 8 M347677 structure, instead of limiting the creation, no longer like The description is hereby stated. The anti-mite layer 21 is disposed on the substrate body 20, the circuit layer 200, and each of the electrical contact pads 201, and has a plurality of openings 210 for correspondingly exposing the respective electrical contacts 201; The bump 22 is disposed on the exposed electric power, and is in contact with the surface of the solder resist layer 21, and the material of the metal bump t 22 is tin (Sn), silver (Ag), gold (Au), copper ( Cu), nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), or a combination of the above, and formed by plating or electroplating, in this embodiment A, The material of the metal bumps 2 2 is copper. The size of the electrical contact pad 2〇1 and the metal bump 22 is larger than the size of the opening 210 or equal to the size of the opening 21 (not shown), and the size of the electrical contact pad 201 is larger than the metal. The size of the bump 22 is equal to or equal to the size of the metal bump 22 (not shown). Please refer to FIG. 3A to FIG. 3D. In the embodiment, the wheel of the electrical contact pad 201 is one of a rectangular shape and an elliptical shape. The contour of the opening hole _ 210 corresponds to the electrical contact pad. 2〇1 is one of a rectangular shape and an elliptical shape, and the metal bump 22 is located on the solder resist layer 21 and has a circular shape (not shown), a rectangular shape, and an elliptical shape, and is electrically The shapes of the contact pads 201, the openings 210 and the metal bumps 22 can be interactively matched to meet the requirements of different fine pitch requirements and alignment accuracy. When applied to a package substrate of a fine pitch line, the present invention has a rectangular or elliptical shape by forming the opening 210 and the electrical contact pad 2〇1 to have the characteristics of long and short sides, which is advantageous in the short side direction. In order to reduce the pad distance (d2 < dl, dl see the ία, 1B, d2 see Figure 2) and the opening 21 〇 width 9 M347677 degrees, in the long-side direction compensates for the loss of the short-edge hole 210 area to provide The electrical contact pad 201 and the metal bumps 22 have sufficient bonding force to achieve the fine pitch requirement, or the space between the electrical contact pads 201 can be effectively increased without reducing the pad pitch d2. Multiple lines. Referring to FIG. 4 together, the package substrate further includes a surface treatment layer 220, which is disposed on the surface of the metal bump 22, which is made of tin (Sn), silver (Ag), and gold (Au). , electroplating tin, nickel/gold, nickel/gold/gold, electroplating nickel/gold, tin-lead (SnPb), tin-silver-copper (SnAgCu), tin-silver (SnAg), combinations of the above, or organic solder mask (〇sp). . Referring to FIGS. 5A and 5B, the package structure of the package substrate of the present invention is applied, and the structure shown in FIG. 5 includes the semiconductor wafer 23 disposed on the package substrate and the protection provided on the package substrate. a primer 25 between the solder layer 21 and the semiconductor wafer 23; or as shown in FIG. 5β, the package substrate is coated with one side of the semiconductor wafer 23 with a molding grease 26, and the solder resist layer 21 and the semiconductor are filled. Between the wafers 23, the semiconductor wafers and the ruins 23 have a plurality of electrode pads 23 〇 through the solder "the metal bumps 22 of the electrical H-substrate. Sealing, when the package process, metal bumps 22 The outline is designed as a rectangle or an ellipse, and the alignment of the contacts is completed in the same package alignment precision. Furthermore, the use of the metal bumps 22 can reduce the tan, use, and metal bumps. The height and volume of 22 are easily regulated and the gap between the semiconductor wafers 23 is of the required size, and the difference is small and has good coplanarity, forming an electrical 10 M347677 contact with the semiconductor wafer 23 to provide better. Reliability, and the metal bumps 22 are located The outline of the tan layer 21 may also be rectangular or elliptical, which is more advantageous than the prior art; the distance between the substrate main body 2 and the semiconductor wafer 23 is reduced and the primer # 25 or the molding grease 26 The reliability of the filling quality, 俾 effectively reduce the thickness of the package structure, and meet the requirements of thinning. In summary, the design of the electrical contact pad is rectangular or elliptical, and the opening of the solder resist layer The outline is rectangular or elliptical, and
該=屬凸塊之輪廓為圓形、長方形或橢圓形，以使應用於 子衣基板日守，塾距可藉由該電性接觸塾及防焊層之開孔具 有短邊而得以縮小，而利於達到細間距需求之目的。〃 上述實施例僅例示性說明本創作之原理及其功效，而 非用於限制本創作。任何本創作所屬技術領域中具有通常 知識者均可在不違#本創作之精神及㈣下，對上述實施 例進行心飾與改變。因此，本創作之權利保護範圍，應如 後述之申請專利範圍所列。The contour of the convex bump is circular, rectangular or elliptical so as to be applied to the substrate of the substrate, and the pitch can be reduced by the short side of the opening of the electrical contact and the solder resist layer. It is conducive to the purpose of fine pitch requirements. The above embodiments are merely illustrative of the principles of the present invention and their effects, and are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field of this creation can make modifications and changes to the above embodiments without violating the spirit of this creation and (4). Therefore, the scope of protection of this creation should be as listed in the scope of the patent application described later.
【圖式簡單說明】 f 1Α及1Β圖係為習知覆晶式封裝件之剖面示意圖； 第1C圖係為習知覆晶式縣件之局部放大上視示意 第2圖係為本創作封裝基板之剖面示意圖； ☆第3Α至3D®係為本創作縣基板之金屬凸塊之不同 態樣之上視示意圖； 第4圖係為本創作封|基板之另一實施態樣之剖面 不意圖；以及 11 M347677 第5A及5B圖係為本創作封裝基板之封裝應用之剖面 示意圖。 【主要元件符號說明】 10，20 基板主體 100, 200 線路層 101，201 電性接觸墊 11，21 防焊層 110, 210 開孔 鼸 13, 23 半導體晶片 1 30, 230 電極墊 14 焊料凸塊 15, 25 底膠 16, 26 封模塑脂 22 金屬凸塊 220 表面處理層 24 • 焊料 _ dl，d2 墊距 ， 12[Simple diagram of the diagram] The f 1Α and 1Β diagrams are schematic cross-sectional views of a conventional flip-chip package; the 1C diagram is a partial enlargement of the conventional flip-chip type of the condition. Schematic diagram of the cross section of the substrate; ☆ 3rd to 3D® is a schematic view of different aspects of the metal bumps of the substrate of the creation county; Fig. 4 is a cross-sectional view of another embodiment of the creation of the substrate And 11 M347677 Figures 5A and 5B are schematic cross-sectional views of the packaging application of the authoring package substrate. [Main component symbol description] 10,20 substrate main body 100, 200 wiring layer 101, 201 electrical contact pad 11, 21 solder resist layer 110, 210 opening 鼸 13, 23 semiconductor wafer 1 30, 230 electrode pad 14 solder bump 15, 25 primer 16, 26 molding grease 22 metal bumps 220 surface treatment layer 24 • solder _ dl, d2 pad, 12