丄呼δ!). 九、發明說明： 【發明所屬之技術領域】 強化j m關於—種封裝基板結構及製法，尤指種 強化電性連接結構之封裝基種 【先前技術】 八衣法 r小隨：電：產業的蓬勃發展’電子產品之外型趨向輕薄丄 δ ) ) ) ) ) ) ) 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明With: Electricity: the booming industry's appearance
研於方θ力：上則逐漸迤入高性能、高功能、高速度化的 =方向。傳統半導體封I結構係將半導體晶片之非作用 4貼於封|基板上，再進行打線接合（whbQ涵叫）， :將半導體晶片之作用面以覆晶接合(Flip chip)電性連 接至該封裳基板，再於封裝基板之背面植設焊料球以盘一 印刷電路板進行電性連接。 μ參閱第1圖’係為習知封裝基板上整合有打線及覆 曰曰接置半導體晶片之剖視圖；首先提供—具有相對之第 一及第二表面10a’10b之基板本體10，該第-表面10a •具有複數覆晶焊塾· 101及打線墊102，而該第二表面⑽ 具有複數植球塾103,且該第一及第二表面1〇a，i〇b上分 別設有第一及第二防焊層11a，lib，並形成複數第一、第 二及第三開孔l10a，llla，11〇b，以對應露出各該覆晶焊 墊101、打線墊102及植球墊1〇3 ,又於該打線墊1〇2及 植球墊103上形成例如為電鍍鎳/金（Ni/Au)、或化鍍鎳/ 金（Ni/Au)之表面處理層12，而在該覆晶焊墊1〇1上形成 例如為焊錫材料（Snpb，SnAg，SnCu，SnAgCu)之焊料凸塊 13 ;或者’在該覆晶焊墊ι〇1上僅形成有例如為有機保焊 110863DP02 5 1359485 , 膜（OSP)、化錫（IT)或焊錫材料之表面處理層（圖未示）。 上述之覆晶焊墊101藉由焊料凸塊13以接置第一 導體晶片14a，該第一半導體晶片14a具有作用面⑷a 及非作用面142a，而該作用面⑷a具有複數第一電極塾 143a，且該第一電極塾143a藉由導電凸塊144以接合該 焊料凸塊13,俾使該第-半導體晶片…以覆晶電= 接該基板本體10〇 又，該第一半導體晶片14a之非作用面142a上以結 >合材料15接置第二半導體晶片14b之非作用面i42b，: 該第二半導體晶片14b之作用面"lb具有複數第二電極 墊143b，以藉係如金線之導線16電性連接該打線墊丨〇2, 並於該第一防焊層lla、打線墊1〇2、導線16、第一及第 二半導體晶片14a，14b表面覆蓋提供保護效果之封 料 17。 " 惟，隨著電子裝置朝向輕薄短小的方向推進，使各覆 晶焊墊101、打線墊1〇2及植球墊103之間的間距不斷縮 =，且該第一及第三開孔11〇a，11〇b相對縮小，而該覆晶 焊墊101與植球墊103露出之面積亦逐漸縮小，導致該覆 曰曰焊墊1 01與焊料凸塊13、或植球墊1 〇3與焊料球（圖未 不）之間的結合面積縮小，且該覆晶焊墊1〇1、打線墊1〇2 及植球墊103通常係為銅，再加上因應無鉛的環保需求， 俾使該表面處理層及禪料凸塊13面臨下列不利於電性 連接可靠度的問題： 其一’當該表面處理層12之材料為焊錫 6 H0863DP02 1359485 (SnPb, SnAg,SnCu,SnAgCu)、化錫（IT)、及有機保焊膜 (OSP)時，將難以防止產生銅遷移（c〇pper 而 導致短路；此外，隨著銅與錫接合面產生之介面合金共化 物（IMC，Intermatallic Compound)層不斷增厚而相對使 v覆晶焊墊或植球墊103之厚度不斷減薄，對於接點可 养度造成不利之影響。 其二，當該表面處理層12為電鍍鎳/金（Ni/Au)時， 其厚度公差將難以達到細間距對厚度均勻性的要求，應用 鲁於覆晶焊墊101或植球塾1〇3上將容易發生谭料凸塊^ 或焊料球脫落，應用於打線墊1〇2上將容易發生導線Μ 脫落》 — —其三，當該表面處理層12為化鍍鎳/金（Ni/Au)時， 若應用於覆晶焊墊1〇1或植球墊1〇3上，鎳（Ni)之材質特 性將容易造成焊料凸塊13或焊料球脫落，而不利於手持 式產品之應用；又’若應用於打線墊1〇2上，則由於以化 *鐘方式所形成之金層較簿，日纟士 # s权潯且結構不緻密，致使與導線 16接著不良。 > 其四 虽該銲料凸塊13之製作為網版印刷 2 =塊13之體積及高度之平均值與公差控制不易 =以達壯㈣的要求；若應用於覆晶料a】上， 鬼13之體積平均值偏小或高度平均值偏低時， 邮封裝之底膠（underflU)填充；又，若該焊料凸塊^ 之租積平均值偏大或高度古 路之接㈣射h」、 谷易發生造成堯 之接_、..占橋接（brldge)現象；另外，若該谭料凸塊η ^ 110863DP02 1359485 而度公差偏大時，則由於共面性⑹灿咖㈣不良，導 致接點應力（stress) *平衡而容易造成晶片被破壞。 且制Γ此1如何設計—種克服上述種種問題之封録板及 、衣k貝已成目鈾業界返欲解決的課題。 【發明内容】 鐘於前述習知技術之缺失，本發明之—目㈣在於提 _、種封裝基板及其製法，能滿足整合打線封裝與覆晶封 裝應用於細間距設計之需求。 本發明之另-目的係在於提供—種提升電性連接可 罪度之封裝基板及其製法。 ^達上述及其他目的’本發明之封裝基板，係包括： j本體’係具有相對應之第一表面及第二表面，於該第 數有複數覆晶焊塾及打線塾，而該第二表面具有複 防焊展且該第一表面及第二表面分別設有第一及第二 =二=:防焊層具有複數第一及第二開孔，以對應 門 ^ bb焊塾及打線墊，該第二防焊層具有複數第三 =上以對應露出各該植球塾；第一凸塊，係設於該覆晶 及化鎳/絶/金層，係設於該第-凸塊、打線塾 及植球塾表面上。 前述之封裝基板中，命么 可士 可為銅之第-凸塊的寬度係 可大於或寻於該第一防焊層 凸塊上具有凹陷部。…-開孔的孔徑，且該第-依上述之結構，復可包枯 焊塾與第—凸=電層，係設於該覆晶 弟 ¥電層可包含有鈀（pd)材， 110863DP02 8 1359485 而該第—開孔中之第—表面上並無該紀材殘存。 匕外如述之封裝基板復可包括係為銅之第二凸塊， 知η又於該植球墊上，且為該化鎳/鈀/金層所覆蓋，又於誃 第二凸塊與植球塾之間設有第二導電層，且該第二凸塊I 具有凹陷部。 本發明復提供—種封裝基板製法，係包括：提供一基 板本，’該基板本體具有相對應H面及第二表面， ;s第表面形成有複數覆晶焊墊及打線墊，而該第二表 =域有，數植球塾’且該第—表面及第二表面分別形^ 一 及第一防焊層；於該第一防焊層形成複數第一及第 2孔，以對應露出各該覆晶焊墊及打線塾，料第二防 ^層形成複數第三開孔，以對應露出各該植球塾；於該第 2焊層表面、覆晶焊塾、打線塾及基板本體之第一表面 八=第一導電層；於該第一導電層及第二防焊層上 :別：成有第-阻層及第二阻層，且該第一阻層中形成有 二=，以露出該覆晶焊整上之第-導電層；於該第 “二二：第一導電層上電鍵形成有第-凸塊；移除 —層與弟一阻層及其所覆蓋之第一導電岸.以及 於該f凸塊及打線塾上化鐘形成有化制巴/金曰層’。 的寬法中’該第一凸塊係可為鋼，且該第-凸塊 t二凸:上或等於該第一防焊層之第-開孔的孔 弟凸境上復可形成有凹陷部。 為促St:/一導電層可包含有_)材，係 、金“積之觸媒，以使該第一導電層順利形成於該 110863DP02 9 ^^9485. 第-防輝層表面、覆晶禪墊、打線塾及基板 面上；復包括移除該第一阻層及其覆蓋之第弟= 藉由鳩喊含硫腦m— 蝕刻液進行微蝕刻，以穿入 」CS)之 :以-王移除該鈀材’而使該第二開孔 中之弟一表囬上亚無殘存該鈀材。 此外’前述之製法，復可包 有化鎳/鈀/全爲…:匕括於該植球塾上化鍍形成 ” 。攻於该植球墊上電鍍形成有係可為銅 之第二凸塊，於該第二凸塊上化鐘形成有:::銅 或於該第二凸塊上形成有凹陷部。 純/金層’ 第之製法，該第二凸塊之製法，係包括··於該 弟-防知層表面及該植球墊上形成第二導電層，·於 ΪΪ::層上：成有第二阻層，且該第二阻層中形成有第二 广二以路出該植球墊上之部份第二導電層；於該第二 二：：中之弟二導電層上電鍍形成該第二凸塊;以及移 除該弟二防焊層上之第二阻層及其所覆蓋之第二導電層。 1Α /ίί可知’本發明之封裝基板及其製法，藉由該化錄 『金層及第：凸塊之設計’相較於習知之電練金 1 U方式’該化鎳/免/金層可防止產生銅遷移以避免 講，且該化錄/鈀/金層以化鍍製作，其厚度公差易於達 =間距對厚度均勾性的要求，應用於覆晶焊塾或植球Research on the square θ force: On the top, it gradually breaks into the high-performance, high-function, high-speed = direction. The conventional semiconductor package I structure attaches the non-acting 4 of the semiconductor wafer to the sealing substrate, and then performs wire bonding (whbQ nicking): electrically connecting the active surface of the semiconductor wafer to the flip chip. The substrate is sealed, and solder balls are implanted on the back surface of the package substrate to electrically connect the disk to the printed circuit board. Referring to FIG. 1 , a cross-sectional view of a semiconductor package in which a wire bonding and a bonding semiconductor are integrated on a conventional package substrate is provided. First, a substrate body 10 having a first and second surface 10 a ′ 10b opposite to the first surface is provided. The surface 10a has a plurality of flip chip pads 101 and a wire pad 102, and the second surface (10) has a plurality of ball bumps 103, and the first and second surfaces 1a, ib are respectively provided with a first surface And the second solder resist layer 11a, lib, and forming a plurality of first, second and third openings l10a, 11la, 11〇b, correspondingly exposing each of the flip chip 101, the wire pad 102 and the ball pad 1 〇3, a surface treatment layer 12 such as electroplated nickel/gold (Ni/Au) or nickel/gold (Ni/Au) is formed on the wire pad 1〇2 and the ball pad 103, and A solder bump 13 such as a solder material (Snpb, SnAg, SnCu, SnAgCu) is formed on the flip chip 1〇1; or 'On the flip chip ι1, only the organic solder resist 110863DP02 5 is formed. 1359485, surface treatment layer of film (OSP), tin (IT) or solder material (not shown). The above-mentioned flip chip 101 is connected to the first conductor wafer 14a by a solder bump 13 having an active surface (4)a and an inactive surface 142a, and the active surface (4)a has a plurality of first electrodes 塾143a And the first electrode 塾 143a is bonded to the solder bump 13 by the conductive bumps 144, so that the first semiconductor wafer is flipped on the substrate body 10, and the first semiconductor wafer 14a is The non-active surface 142a is connected to the non-active surface i42b of the second semiconductor wafer 14b by a junction material: the active surface of the second semiconductor wafer 14b has a plurality of second electrode pads 143b. The wire 16 of the gold wire is electrically connected to the wire pad 2, and the surface of the first solder resist layer 11a, the wire bonding pad 1 2, the wire 16, and the first and second semiconductor wafers 14a, 14b are provided with a protective effect. Sealing material 17. " However, as the electronic device is advanced in a light, short, and short direction, the spacing between each of the flip chip pads 101, the wire pad 1〇2, and the ball pad 103 is continuously reduced, and the first and third openings are 11〇a, 11〇b is relatively reduced, and the exposed area of the flip chip 101 and the ball pad 103 is gradually reduced, resulting in the overlay pad 101 and the solder bump 13, or the ball pad 1 3, the bonding area between the solder ball and the solder ball is reduced, and the flip chip 1 〇 1, the wire pad 1 〇 2 and the ball pad 103 are usually copper, and in response to the environmental requirements of lead-free, The surface treatment layer and the embossing bump 13 face the following problems that are not conducive to electrical connection reliability: [When the surface treatment layer 12 is made of solder 6 H0863DP02 1359485 (SnPb, SnAg, SnCu, SnAgCu), When tin (IT) and organic solder mask (OSP) are used, it is difficult to prevent copper migration (c〇pper and cause short circuit; in addition, interface alloys (IMC, Intermatallic Compound) are produced along with copper and tin joints. The layer is continuously thickened and the thickness of the v-cladding pad or the ball-filled pad 103 is continuously reduced. The point can be adversely affected by the nutrient. Second, when the surface treatment layer 12 is electroplated nickel/gold (Ni/Au), the thickness tolerance thereof will be difficult to achieve the requirement of fine pitch and thickness uniformity, and the application is applied to the flip chip. On the pad 101 or the ball 塾1〇3, the tan bumps or the solder balls are likely to fall off, and the application of the wire mat 1 2 can easily cause the wire 脱落 to fall off — the third, when the surface treatment layer 12 For the plating of nickel/gold (Ni/Au), if applied to the flip chip 1〇1 or the ball pad 1〇3, the material properties of nickel (Ni) will easily cause the solder bumps 13 or solder balls to fall off. However, it is not conducive to the application of hand-held products; and if it is applied to the wire mat 1〇2, the gold layer formed by the method of forming the clock is better than the book, and the structure is not dense, resulting in And then the wire 16 is bad. > Fourth, although the solder bump 13 is made of screen printing 2 = the average volume and height of the block 13 and the tolerance control is not easy = to meet the requirements of the strong (four); if applied to flip chip On the material a], when the volume average of the ghost 13 is small or the height average is low, the undergap of the postal package (underflU) In addition, if the average value of the solder bumps is too large or the height of the ancient road is connected (4), the valley is easy to occur, and the bristles are caused by the bristles. In addition, if the tan Material bump η ^ 110863DP02 1359485 When the degree tolerance is too large, the coplanarity (6) can cause damage to the wafer due to the poor balance of stress (stress) * and how to design this type Overcoming the above-mentioned problems, the seal board and the clothing k shell have become the subject of the uranium industry. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the present invention (4) is to provide a package substrate and a method for manufacturing the same, which can meet the requirements of the integrated wire bonding package and the flip chip package for the fine pitch design. Another object of the present invention is to provide a package substrate for improving the electrical connection reliability and a method of manufacturing the same. The above-mentioned and other objects are as follows: The package substrate of the present invention comprises: a body having a corresponding first surface and a second surface, wherein the plurality has a plurality of flip-chip solder wires and wire bonds, and the second The surface has a re-proof soldering and the first surface and the second surface are respectively provided with first and second=two=: the solder resist layer has a plurality of first and second openings, so as to correspond to the gate bb welding and the wire mat The second solder resist layer has a plurality of third=upper to correspondingly expose the respective ball bumps; the first bump is disposed on the flip chip and the nickel/nano/gold layer, and is disposed on the first bump , on the surface of the ball and on the surface of the ball. In the foregoing package substrate, the width of the first bump of the copper may be greater than or may be found on the bump of the first solder resist layer. ...-opening aperture, and the first-in accordance with the above structure, the composite can be coated with a solder joint and a first convex-electrical layer, and the electrical layer of the laminated crystal may comprise palladium (pd) material, 110863DP02 8 1359485 and the first surface of the first opening has no such residual material. The package substrate as described above may include a second bump which is copper, and the η is on the ball pad, and is covered by the nickel/palladium/gold layer, and the second bump and the substrate are A second conductive layer is disposed between the balls, and the second bump 1 has a recess. The invention provides a method for manufacturing a package substrate, comprising: providing a substrate body, wherein the substrate body has a corresponding H surface and a second surface; s the surface is formed with a plurality of flip chip pads and a wire pad, and the The second table=domain has a number of ball 塾' and the first surface and the second surface are respectively formed and a first solder resist layer; a plurality of first and second holes are formed in the first solder resist layer to correspondingly expose Each of the flip chip and the wire splicing layer forms a plurality of third openings to expose the respective ball slabs; the surface of the second solder layer, the flip chip, the wire 塾 and the substrate body The first surface 八=the first conductive layer; on the first conductive layer and the second solder resist layer: another: a first resistive layer and a second resistive layer, and the first resistive layer is formed with two= And exposing the first conductive layer on the flip chip; in the second “second: the first conductive layer is electrically formed with a first bump; the removed layer and the first resist layer and the covered layer thereof a conductive bank. And in the f bump and the wire on the wire, the formation of a chemical bar/gold layer". In the wide method, the first bump can be steel. The first bump-t biconvex: a hole above or equal to the first opening of the first solder resist layer may be formed with a recessed portion. The St:/ a conductive layer may include a material , the system, the gold "catalyst, so that the first conductive layer is smoothly formed on the surface of the 110863DP02 9 ^ ^ 9485. the first - anti-glare layer, the crystal zen pad, the wire 塾 and the substrate surface; The first resistive layer and its covered first brother = micro-etched by shouting a sulfur-containing brain m-etching solution to penetrate "CS": the king removes the palladium material and makes the second opening The younger brother of Kong Zhong returned to Shangya without the remaining palladium. In addition, the 'preparation method, the composite nickel/palladium/all... is formed on the ball slab." The plating is formed on the ball pad to form a second bump which can be copper. The second bump is formed with::: copper or a depressed portion formed on the second bump. The pure/gold layer' method of manufacturing the second bump, the method comprising: Forming a second conductive layer on the surface of the anti-knowledge layer and the ball pad, on the layer: a second resist layer, and the second resist layer is formed in the second resist layer a portion of the second conductive layer on the ball pad; electroplating the second bump on the second conductive layer of the second second:: and removing the second resist layer on the solder resist layer The second conductive layer covered by the present invention. The package substrate of the present invention and the method for manufacturing the same are described by the "gold layer and the design of the bump" compared with the conventional electric gold 1 U method. 'The nickel/free/gold layer prevents the migration of copper to avoid the mention, and the chemical/palladium/gold layer is made by chemical plating, and the thickness tolerance is easy to reach = the pitch to the thickness Seeking for the application of flip chip or ball
登乃至應用於第'一凸持月笛-_TLH 龙及弟—凸塊上’可避免焊料凸塊 次斗枓球脱洛，並易於進行打線接合。 另外’相較於習知之網版印刷方式，該第一凸塊以電 錢‘作’其體積與高度之平均值與公差易於控制，能避免 110863DP02 1359485 封裝結構底膠填充困難、接點橋接、及凸塊共面性不良所 ,—致之接點應力不平衡現象，且凹陷部之設計可進一步減少 -晶片與封裝基板間之應力。 因此本發明之封裝基板不僅可達到提升電性連接可 •赤度之目的，且能滿足整合打線封裝與覆晶封裝應用於細 . 間距設計之需求。 【實施方式】 、以下係藉由特定的具體實施例說明本發明之實施方 •式’ 4習此技蟄之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 [第一實施例] 請麥閱第2A至2E圖，係為本發明封裝基板及其製法 的剖視圖。 如第2A圖所示’提供一基板本體2〇，談基板本體2〇 具有相對應之第一表面20a及第二表面2〇b，於該第一表 φ面20a上形成有複數覆晶焊墊201及打線墊202，而於該 第二表面20b上形成有複數植球墊2〇3,且於該第一表面 20a及第二表面2〇b上分別形成有第一防焊層21a及第二 防焊層21b，而於該第一防焊層21a中形成有複數第一及 第二開孔210a，211a，以使各該第一開孔210a對應露出 各該覆晶焊墊201，而使各該第二開孔211a對應露出各 該打線墊202及其周圍之第一表面20a，又於該第二防焊 層21b中形成複數第三開孔21〇b，以對應露出各該植球 203 ° π 110863DP02 1359485 執2(U、斤不，於該第一防焊層21a表面、覆晶焊 ί第hi 2及基板本體2G之第—表面施上形 :為促、隹=223，且該第—導電層如含有纪⑽材， 金屬沉積之觸媒’以使該第一導電層22a順利形 防焊層21a表面、覆晶焊㈣卜打線塾202 及基板本體20之第一表面2〇a上。 接著，於該第一導電層22a上形成有第一阻層心， 而在該第二防焊層21b上形成有第二阻層23b，且該第一 ^且，23a中形成有第—開口區2咖，以露出該覆晶焊塾 及其周圍第-防焊層21a上之第一導電層22a。 如第2C圖所示’於該第一開口區230a中之第一導電 層22a上電鍍形成有係為銅之第一凸塊24a。 如第2D圖所示，移除該第一阻層2如及其所覆蓋之 第-導電I 22a，以露出該第一防焊層.21a、第一凸塊 4a打線塾202及其周圍之第一表面2〇a;且移除該第 一阻層23b，以露出該第二防焊層21b及植球墊2〇3。 另外叫併參閱第2D’圖，移除該第一阻層23a所 復盍之第一導電層22a後，該第二開孔21 la中之打線墊 202周圍之第一表面2 〇a上易殘存纪（pd)材，而於後續製 私中，當於各該打線墊202上形成化鎳/鈀/金（Ni/Pd/Au) 層時’該第一表面20a因殘存其上之鈀材將導致一同形成 有化鎳/鈀/金（Ni/Pd/Au)層，而使各該打線墊202之間形 成橋接之短路現象；為避免發生短路現象，故藉由含有氰 (Cyanide，CN)或含硫脲（Thiourea, (NH2)2CS)之蝕刻液 12 110863DP02 1359485 之打線墊202周圍之 進行微蝕刻，以將第二開孔211a中 第—表面20a上之鈀材完全移除。 如第2E圖所示，接著 於該第 9n9 ….凸塊24a、打線墊 2及植球墊2G3上化錢形成有化鎳~金（Ni/pd/Au)層 ，且金（An)形成在最外層，而位於該第一防焊層 表=上之第-凸塊24a的寬度係大於該第—防焊^仏 之第一開孔210a的孔徑。 如帛2E，圖所示，該第一凸塊24a上亦可具有凹陷部 馨24〇a;或者如第2E，，圖所示，位於該第一防焊層仏表面 上之第一凸塊24a，的寬度係等於該第一防焊層2ia之第 一開孔210a的孔徑；又，於第2E，、2E„圖之第一凸塊 24a, 24a外路之表面上形成該化錄/ |巴/金層25。 本發明復提供一種封裝基板，如第2E圖所示，係包 括：基板本體20、第一凸塊24a及化鎳/鈀/金層25;所 述之基板本體20具有相對應之第一及第二表面 參20a’20b，於該第一表面20a上具有複數覆晶焊墊2〇1及 打線墊202,而於該第二表面20b上具有複數植球墊2〇3, 且於該第一及第二表面20a，20b上分別設有第一及第二 防焊層21a，21b，而該第一防焊層2la具有複數第一及第 一開孔210a，211 a，以分別對應露出各該覆晶焊塾1及 打線墊202 ’又該第二防焊層21b具有複數第三開孔 210b，以對應露出各該植球墊203 ;所述之第一凸塊24a 係為銅且設於該覆晶焊墊201上；所述之化鎳/飽/金層 25設於該第一凸塊24a、打線墊202及植球墊203上，且 110863DP02 13 1359485 金（Au)形成在最外層。 上述之結構復包括第一導電層22a，係設於該覆晶焊 塾與第一凸塊⑽之間’且該第一導電層仏包含有 _細)材，而該第二開孔，中之第_表面 益 該鈀材殘存。 …' - 又，上述之結構中，位於第—防焊層2la表面上之第 一凸塊24a的寬度係大於第一開孔21〇a的孔徑（如第 所不）、或等於第一開孔21 Oa的孔徑（如第2£”所示）， •且該第一凸塊2乜上可具有凹陷部24〇a(如第Μ，所 [第二實施例] 不。 、請參閱第3A至3D圖，係為本發明之另一實施製造 方法’與第一實施例之不同處係在於該植球塾上形成=第 二凸塊。 “如f 3A圖所示，提供一係如第2A圖所示之結構，接 :’於該第-防焊層21a上形成有第—導電層如，且該 §弟:導電層22a含有纪⑽材，並於該第一導電層^ 上形成有第一阻層23a，且於該第__阻屏 一叫^ 弟阻層23a中形成有第 —，口區23〇a’以露出該覆晶焊整2〇1及其周圍上之第 ^電層22a;而於該第二防焊芦2〗 層化及植球墊2〇3上形 有第—钕電層22b，並於該第-導#禺99h 阻屏x弟一绔电層22b上形成第二 曰咖’且於該第二阻層饥中形成有第二開口區 咖’以露出該植球㈣3及其周圍上之第 如第3B圖所示，於哕笔广 α斤丁於。亥弟-開口區230a +之第一導電 ^ 电鍍形成有係為銅之第一凸塊24a，且於該第二 110863DP02 14 1359485 . 開口區2鳥中之第二導電層22b上電鐘形成有係為銅之 第二凸塊24b。 . 如第3C圖所示，移除該第一阻層23a及其所覆蓋之 ，第一導電層22a，以露出該第一防焊層21a、第一凸塊 .24a、第二開孔211a中之打線墊202及其周圍之第一表面 20a;且移除該第二阻層23b，以露出該第二防焊層21b 及第二凸塊24b;此外，藉由含有氰（Cyanide，CN)或含 硫脲（Thi〇urea，（NH2) 2 CS)之蝕刻液進行微蝕刻，以將 •第二開孔211a中之打線墊202周圍之第一表面2〇a上之 把材完全移除。 如第3D圖所示，於該第一凸塊24a、打線墊2〇2及 第二凸塊24b上化鍍形成有化鎳/鈀/金（Ni/pd/Au)層 25，且金（Au)形成在最外層；請參閱第3D，圖，該第二凸 塊24b上亦可形成有凹陷部240b。 本發明復提供一種封裝基板，如第3D圖所示，係包 φ括：基板本體20、第一及第二凸塊24a，24b及化鎳/鈀/ 金層25 ;所述之基板本體2〇具有相對應之第一及第二表 面20a，20b，於該第一表面20a上具有複數覆晶焊墊2〇1 及打線墊202，而於該第二表面2〇b上具有複數植球墊 203 ’且於該第一及第二表面2〇a，2〇b上分別設有第一及 第二防焊層21a，21b，而該第一防焊層21a具有複數第一 及第二開孔210a，211a，以分別對應露出各該覆晶焊墊 201及打線墊202，又該第二防焊層21b具有複數第三開 孔210b，以對應露出各該植球墊2〇3 ;所述之第一凸塊 110863DP02 15 1359485 24a係為銅且設於該覆晶焊墊2〇1上；所述之第二凸塊 24b係為銅且設於該植球塾203上；所述之化錄/把/金層 25設於該第一凸塊24a、打線墊2〇2及第二凸塊2仆表面 上’且金（A u)形成在最外層。 上述之結構復包括第一導電層2 2 a，係設於該覆晶焊 墊20丨與第一凸塊24a之間，且該第一導電層22a包含有 鈀（Pd)材，而於該第二開孔211a中之第一表面2〇a上並 無該，材殘存；上述之結構亦包括第二導電層22b，係設 •於該第二凸塊24b與植球墊203之間。It is applied to the 'one convex moonlight-_TLH dragon and brother-bump' to avoid solder bumps, and the ball is easy to be wire-bonded. In addition, compared with the conventional screen printing method, the first bump is easy to control with the average value and tolerance of the volume and height, and can avoid the difficulty of filling the primer of the 110863DP02 1359485 package structure, the bridge of the joint, And the coplanarity of the bumps, resulting in joint stress imbalance, and the design of the recesses can further reduce the stress between the wafer and the package substrate. Therefore, the package substrate of the present invention can not only achieve the purpose of improving the electrical connection and the redness, but also meet the requirements of the integrated wiring and flip chip packaging for fine pitch design. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present specification. [First Embodiment] Figs. 2A to 2E are cross-sectional views showing a package substrate of the present invention and a method of manufacturing the same. As shown in FIG. 2A, a substrate body 2 is provided, and the substrate body 2 has a corresponding first surface 20a and a second surface 2〇b, and a plurality of flip-chip solders are formed on the first surface φ surface 20a. a pad 201 and a wire pad 202, and a plurality of ball pads 2〇3 are formed on the second surface 20b, and a first solder resist layer 21a is formed on the first surface 20a and the second surface 2〇b, respectively. a second solder resist layer 21b, and a plurality of first and second openings 210a, 211a are formed in the first solder resist layer 21a, so that each of the first openings 210a correspondingly exposes each of the flip chip pads 201, And each of the second openings 211a correspondingly exposes the first surface 20a of each of the bonding pads 202 and the periphery thereof, and a plurality of third openings 21〇b are formed in the second solder resist layer 21b to respectively expose the respective openings Planting ball 203 ° π 110863DP02 1359485 2 (U, jin not, on the surface of the first solder mask 21a, the surface soldering ф hi 2 and the surface of the substrate body 2G - surface applied: for promotion, 隹 = 223 And the first conductive layer, such as containing the material (10), the metal deposition catalyst 'so that the first conductive layer 22a smoothly forms the surface of the solder resist 21a, and the soldering (four) beat line The first surface 2〇a of the substrate 202 and the substrate body 20. Next, a first resistive layer is formed on the first conductive layer 22a, and a second resist 23b is formed on the second solder resist 21b. And a first opening region 2 is formed in the first portion, 23a to expose the first conductive layer 22a on the flip chip and the surrounding solder mask layer 21a. As shown in FIG. 2C' A first bump 24a is formed by electroplating on the first conductive layer 22a in the first opening region 230a. As shown in FIG. 2D, the first resist layer 2 is removed as described above. Conducting I 22a to expose the first solder resist layer .21a, the first bump 4a and the first surface 2〇a around the wire 202; and removing the first resist layer 23b to expose the second The solder resist layer 21b and the ball pad 2〇3. Further, referring to FIG. 2D′, after removing the first conductive layer 22a multiplexed by the first resist layer 23a, the line in the second opening 21 la The first surface 2 〇a around the pad 202 is easily residible (pd) material, and in subsequent manufacturing, when a nickel/palladium/gold (Ni/Pd/Au) layer is formed on each of the bonding pads 202 'The first surface 20a remains on it The palladium material will result in the formation of a nickel/palladium/gold (Ni/Pd/Au) layer together, so that a short circuit between the wire pads 202 is formed; in order to avoid a short circuit, the cyanide is contained. Cyanide, CN) or thiourea (Thiourea, (NH2) 2CS) etchant 12 110863DP02 1359485 around the wire pad 202 is micro-etched to completely shift the palladium material on the first surface 20a of the second opening 211a except. As shown in FIG. 2E, a nickel-gold (Ni/pd/Au) layer is formed on the 9th 9th bump 24a, the wire pad 2, and the ball pad 2G3, and gold (An) is formed. At the outermost layer, the width of the first bump 24a on the first solder mask surface is greater than the aperture of the first opening 210a of the first solder resist. As shown in FIG. 2E, the first bump 24a may also have a recessed portion 24a; or as shown in FIG. 2E, the first bump on the surface of the first solder resist layer. The width of 24a is equal to the aperture of the first opening 210a of the first solder resist layer 2ia; and the recording is formed on the surface of the outer path of the first bumps 24a, 24a of the 2E, 2E. The bar/gold layer 25. The present invention further provides a package substrate, as shown in FIG. 2E, comprising: a substrate body 20, a first bump 24a, and a nickel/palladium/gold layer 25; Corresponding first and second surface references 20a'20b having a plurality of flip-chip pads 2〇1 and wire pads 202 on the first surface 20a and a plurality of ball pads 2 on the second surface 20b 〇3, and first and second solder resist layers 21a, 21b are respectively disposed on the first and second surfaces 20a, 20b, and the first solder resist layer 21a has a plurality of first and first openings 210a, 211 a, in order to respectively expose each of the flip chip 1 and the wire pad 202 ′, and the second solder resist layer 21 b has a plurality of third openings 210 b to correspondingly expose each of the ball pads 203 ; The bump 24a is made of copper and is disposed on the flip chip 201. The nickel/saturated/gold layer 25 is disposed on the first bump 24a, the bonding pad 202 and the ball pad 203, and 110863DP02 13 1359485 Gold (Au) is formed on the outermost layer. The above structure includes a first conductive layer 22a disposed between the flip chip and the first bump (10) and the first conductive layer includes _fine And the second opening, wherein the first surface is beneficial to the palladium material. ...' - Further, in the above structure, the width of the first bump 24a on the surface of the first solder resist layer 2la is larger than The aperture of an opening 21〇a (as in the first) or equal to the aperture of the first opening 21 Oa (as shown by the second £), and the first protrusion 2 may have a recess 24 〇a (as in the second embodiment, [second embodiment] No. Please refer to FIGS. 3A to 3D, which is another embodiment of the present invention. The manufacturing method is different from the first embodiment in that the ball is placed. Forming = second bump. "As shown in FIG. 3A, a structure as shown in FIG. 2A is provided, and: a first conductive layer is formed on the first solder resist layer 21a, and the § The conductive layer 22a is provided with a material (10), and a first resist layer 23a is formed on the first conductive layer ^, and a first region is formed in the first resist layer 23a. 〇a' to expose the flip-chip solder 2 〇 1 and its surrounding electrical layer 22a; and the second solder resist 2 stratified and the ball pad 2 〇 3 on the first a layer 22b, and forming a second ' ' on the first 导 禺 h h h h 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且(4) 3 and its surroundings as shown in Figure 3B, in the 哕 广 α α α α 。. The first conductive layer of the diaper-opening region 230a+ is plated with a first bump 24a that is copper, and is formed on the second conductive layer 22b of the open area 2 bird. It is a second bump 24b of copper. As shown in FIG. 3C, the first resistive layer 23a and the first conductive layer 22a covered by the first resistive layer 23a are removed to expose the first solder resist layer 21a, the first bumps 24.a, and the second openings 211a. The wire pad 202 and the surrounding first surface 20a thereof; and the second resist layer 23b is removed to expose the second solder resist layer 21b and the second bump 24b; furthermore, by containing cyanide (Cyanide, CN Or an etchant containing thiourea (Thi〇urea, (NH2) 2 CS) is microetched to completely shift the material on the first surface 2〇a around the bonding pad 202 in the second opening 211a except. As shown in FIG. 3D, a nickel/palladium/gold (Ni/pd/Au) layer 25 is formed on the first bump 24a, the wire pad 2〇2, and the second bump 24b, and gold ( Au) is formed on the outermost layer; see FIG. 3D, the second bump 24b may also be formed with a recess 240b. The present invention further provides a package substrate. As shown in FIG. 3D, the package φ includes: a substrate body 20, first and second bumps 24a, 24b, and a nickel/palladium/gold layer 25; The first surface and the second surface 20a, 20b have a plurality of flip-chip pads 2〇1 and a wire pad 202 on the first surface 20a, and a plurality of ball-planting balls on the second surface 2〇b The pad 203' is provided with first and second solder resist layers 21a, 21b on the first and second surfaces 2a, 2b, respectively, and the first solder resist layer 21a has a plurality of first and second Opening holes 210a, 211a, respectively, respectively exposing each of the flip chip 201 and the wire pad 202, and the second solder resist layer 21b has a plurality of third openings 210b to correspondingly expose the ball pads 2〇3; The first bumps 110863DP02 15 1359485 24a are made of copper and disposed on the flip chip 2〇1; the second bumps 24b are made of copper and disposed on the bulb 203; The chemical recording/pushing/gold layer 25 is disposed on the first bump 24a, the wire bonding pad 2〇2, and the second bump 2 servant surface, and gold (Au) is formed on the outermost layer. The first conductive layer 22a is disposed between the flip chip 20丨 and the first bump 24a, and the first conductive layer 22a comprises a palladium (Pd) material. The first surface 2〇a of the second opening 211a does not have the material remaining thereon; the above structure also includes the second conductive layer 22b between the second bump 24b and the ball pad 203.
另外，位於該第一防焊層21a表面上之第一凸塊2/ 的寬度係大於第-開孔21Ga的孔徑（如第3DH 不）、或等於第一開孔21〇3的孔徑（圖未示），且該第· 凸塊2乜上可具有凹陷部240a(如第3D，圖所示）；又 =於=第二防焊層21b表面上之第二凸塊灿的寬度大力 第二開孔210b的孔徑（如第3D，，圖所示卜或等力 的孔徑（圖未示）’且該第二凸塊24b上夺 可具有凹陷部240b (如第3D，圖所示）。 如4圖’藉由該覆晶焊塾2〇1上的第—凸勒 25, Γ面灿及非作用面2他，且該作用适 251a 了有硬數第一電極墊253&，並在該第一 上形成有導電凸塊254，俾 ' 電凸㈣以接合該第—l=C53a藉由導 H 〇c 〇尾’而使該第一本邋；a*曰 5a以覆晶電性連接至該基板本體別。 110863DP02 16 1^^9485 . 又於該第—半導體晶片25a之非作用面252a上以 。材々斗26接且第二半導體晶片25b之非作用面252b， ，而該第二半導體晶片25b之作用面251b具有複數第二電 ^墊、^53b’且該第二電極墊253b以係如金線之導線 Z性遥接至該打線塾2G2，並於該第一防焊層⑴、打線 •塾202、導線27、第一及第二半導體晶片253，挪表面覆 设提供保護作用之封膠材料28。 本發明藉由該化鎳/ίε/金層25以易於防止產生銅遷 夕此避免知·路，又，銅與錫間因具有化鎳/鈀/金層25， T高溫迴焊後’可獲得較均勾且增層速率緩慢之介面合金 ，、化物層，得避免電性接點品質之劣化。 再者，相較於習知之電鍍錄/金（Ni/Au)方式，本發明 之化錄〜金層25係以化鑛製作，其厚度公差易於達到 ^距對厚度均勻性的要求，應用於覆晶焊塾則或植球 ’乃至應用於第一凸塊24a，24a，及第二凸塊24bIn addition, the width of the first bump 2/ located on the surface of the first solder resist layer 21a is larger than the aperture of the first opening 21Ga (such as 3DH) or equal to the aperture of the first opening 21〇3 (Fig. Not shown, and the second bump 2 can have a recess 240a (as shown in FIG. 3D, shown); and = the width of the second bump on the surface of the second solder resist 21b The aperture of the second opening 210b (as shown in FIG. 3D, the aperture or the equivalent aperture (not shown)' and the second protrusion 24b may have a recess 240b (as shown in FIG. 3D) As shown in Fig. 4, by the first lacquer 25 on the flip chip 塾2〇1, the Γ surface and the non-active surface 2, and the effect 251a has a hard number first electrode pad 253 & A conductive bump 254 is formed on the first surface, and the first protrusion is formed by bonding the first 邋; a* 曰 5a to the flip chip Is connected to the substrate body. 110863DP02 16 1^^9485 . Also on the non-active surface 252a of the first semiconductor wafer 25a, the material bucket 26 is connected to the non-active surface 252b of the second semiconductor wafer 25b, The second half The active surface 251b of the bulk wafer 25b has a plurality of second electrical pads, 53b' and the second electrode pads 253b are connected to the wire 2G2 by a wire such as a gold wire, and the first solder mask is (1), wire bonding 塾 202, wire 27, first and second semiconductor wafer 253, the surface of the sealing material is provided with a protective sealing material 28. The present invention is easy to prevent copper from being formed by the nickel/ίε/gold layer 25 In the future, we will avoid knowing the road. In addition, copper and tin will have a nickel/palladium/gold layer 25, and after T high-temperature reflow, we can obtain a more uniform interface alloy with a slower layering rate and a chemical layer. In addition, compared with the conventional electroplating/gold (Ni/Au) method, the chemistry-gold layer 25 of the present invention is made of mineral ore, and the thickness tolerance thereof is easy to reach. The requirement for thickness uniformity is applied to the flip chip or the ball to be applied to the first bumps 24a, 24a and the second bumps 24b.
^，可避免導電凸塊254或焊料球（圖未示）脫落；此外， 發明之化鎳/鈀/金層25應用於打線墊2〇2上時，易於 進行打線接合。 另外，相車交於習知之網版印刷方式，本發明之 塊24a，24a，及第二凸塊24b係以 凸 度之平均值與公差易於控制 封：：错“積與高 紐^ 此避免封裝結構底膠填充困 U接點橋接、及凸塊共面性不良所致之接點應力不平衡 2 ’且弟-凸塊24a之凹陷部2咖之設計可進一步減 乂晶片與封裝基板間之應力。 110863DP02 17 1359485 河'上所述，本發明之封裝基板及其製法，藉由該化鎳 /纪/金層及第一凸塊之設計，不僅達到提升電性連接可靠 *度之目的，且能滿足整合打線封裝與覆晶封裝應用於細間 ’距設計之需求。 ' 、上僅為本發明之較佳貫施例而已，並非用以限定本 發明之實質技術内容範圍，本發明之實質技術内容係廣義 地定義於下述之申請專利範圍中，任何他人完成之技術實 體或方法’若是與下述之中請專利範圍所定義者係完全相 •同’亦或為同一等效變更，均將被視為涵蓋 範圍中。 。 【圖式簡單說明】 •第1圖係為習知封裝基板及半導體晶片之剖視示意 第2A至2E圖係為本發明之封裝基板及其製法的第一 實施例之剖視示意圖；其中，第2D，圖係為第2d^, the conductive bump 254 or the solder ball (not shown) can be prevented from falling off; in addition, when the inventive nickel/palladium/gold layer 25 is applied to the wire pad 2〇2, wire bonding is facilitated. In addition, the phase car is handed over to the conventional screen printing method, and the blocks 24a, 24a and the second bump 24b of the present invention are easy to control with the average value and tolerance of the crown: wrong "product and high" The package structure underfill fills the U-contact bridge, and the joint stress imbalance caused by the poor coplanarity of the bumps 2' and the design of the recessed portion of the bump-bump 24a can further reduce the gap between the wafer and the package substrate The stress of the 110863DP02 17 1359485 river, the package substrate of the present invention and the manufacturing method thereof, by the design of the nickel/ki/gold layer and the first bump, not only achieve the purpose of improving the reliability of the electrical connection And the invention can meet the requirements of the integrated wire-bonding package and the flip-chip package for the thin-footed design. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the technical content of the present invention. The technical content is broadly defined in the scope of the patent application below, and any technical entity or method completed by others is “completely identical” or equivalent to the one defined in the patent scope below. Changes will be 1 is a schematic cross-sectional view of a conventional package substrate and a semiconductor wafer. FIGS. 2A to 2E are first embodiment of the package substrate of the present invention and a method for manufacturing the same. A schematic cross-sectional view of the example; wherein, the 2D, the figure is the 2d
•部士視放大示意圖，第2E，及2E，，圖係為第2£圖之其他與 施態樣之剖視示意圖； A 第3A至3D圖係為本發明之封裝基板及其製法 實-狀剖視示意圖；其中，第3D，圖係為第 貫施態樣之剖視示意圖；以及 圖係為本發明之封録板及半導體^之剖視 第 示意圖 【主要元件符號說明】 20 基板本體 】]〇863DP〇2 18 1359485. 101，201 覆晶焊墊 102, 202 打線墊 103,203 植球墊 ' 10a, 20a 第一表面 10b, 20b 弟·一表面 11a, 21a 第一防焊層 lib, 21b 第二防焊層 11 0a, 210a 第一開孔 • 110b,210b 第三開孔 111a,211a 第二開孔 12 表面處理層 13 焊料凸塊 14a, 25a 第一半導體晶片 14b, 25b 第二半導體晶片 141a，141b, 251a, 251b 作用面 142a, 142b, 252a, 252b 非作用面 143a,253a 第一電極墊 143b,253b 第二電極墊 144, 254 導電凸塊 15, 26 結合材料 16, 27 導線 17, 28 封膠材料 22a 第一導電層 22b 第二導電層 19 110863DP02 1359485 23a 第一阻層 23b 第二阻層 230a 第一開口區 230b 第二開口區 24a，24a， 第一凸塊 24b 第二凸塊 240a,240b 凹陷咅P 25 化鎳/纪/金層 20 110863DP02• A section of the enlarged view, 2E, and 2E, the figure is a cross-sectional view of the other aspects of the second form; A 3A to 3D are the package substrate of the present invention and the method of manufacturing the same - 3D, the diagram is a schematic cross-sectional view of the first embodiment; and the diagram is a cross-sectional view of the mask and the semiconductor of the present invention. [Main component symbol description] 20 substrate body 】]〇863DP〇2 18 1359485. 101,201 flip chip 102, 202 wire pad 103,203 ball pad '10a, 20a first surface 10b, 20b brother · a surface 11a, 21a first solder mask lib, 21b Second solder mask layer 110a, 210a first opening hole 110b, 210b third opening hole 111a, 211a second opening hole 12 surface treatment layer 13 solder bump 14a, 25a first semiconductor wafer 14b, 25b second semiconductor wafer 141a, 141b, 251a, 251b active surface 142a, 142b, 252a, 252b non-active surface 143a, 253a first electrode pad 143b, 253b second electrode pad 144, 254 conductive bump 15, 26 bonding material 16, 27 wire 17, 28 sealing material 22a first conductive layer 22b second conductive layer 19 110863DP02 1359485 23a first resistive layer 23b second resistive layer 230a first open region 230b second open region 24a, 24a, first bump 24b second bump 240a, 240b recessed 25P 25 nickel/ki/gold layer 20 110863DP02