TWI407538B - Package substrate and fabrication method thereof - Google Patents

Package substrate and fabrication method thereof Download PDF

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Publication number
TWI407538B
TWI407538B TW097144626A TW97144626A TWI407538B TW I407538 B TWI407538 B TW I407538B TW 097144626 A TW097144626 A TW 097144626A TW 97144626 A TW97144626 A TW 97144626A TW I407538 B TWI407538 B TW I407538B
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TW
Taiwan
Prior art keywords
copper pillar
solder
resist layer
layer
copper
Prior art date
Application number
TW097144626A
Other languages
Chinese (zh)
Other versions
TW201021182A (en
Inventor
Ying Chih Chan
Hung Sheng Hu
Original Assignee
Unimicron Technology Corp
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Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW097144626A priority Critical patent/TWI407538B/en
Publication of TW201021182A publication Critical patent/TW201021182A/en
Application granted granted Critical
Publication of TWI407538B publication Critical patent/TWI407538B/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

The invention provides a package substrate and a method of fabricating the same, comprising a substrate body having a plurality of electrical connecting pads formed on at least one surface thereof; a solder mask layer formed on the substrate body and with a plurality of openings for correspondingly exposing each of the connecting pads therefrom; a first copper pillar formed on each connecting pad and protruding from the solder mask layer; and a second copper pillar disposed on the first copper pillar and having a diameter smaller than that of the first copper pillar, such that a larger pitch can be provided between the semiconductor chip and the substrate by the first and second copper pillars, thereby facilitating formation of a fine-pitched package structure and avoiding the drawbacks of uneven stresses caused by poor underfilling in the subsequent packaging process.

Description

封裝基板及其製法Package substrate and its preparation method

本發明係關於一種封裝基板及其製法，尤指一種封裝基板之電性接觸墊上形成有凸柱之結構及製法。The invention relates to a package substrate and a manufacturing method thereof, in particular to a structure and a manufacturing method for forming a stud on an electrical contact pad of a package substrate.

在現行覆晶式(Flip chip)半導體封裝技術中，係於半導體晶片上設有電極焊墊，並於該電極焊墊上形成焊錫凸塊，且在一具有電性接觸墊之封裝基板上形成位於電性接觸墊表面之焊錫凸塊，俾藉由該焊錫凸塊及焊錫凸塊兩者電性連接，以提供該半導體晶片與該封裝基板電性連接。In the current Flip chip semiconductor packaging technology, an electrode pad is disposed on a semiconductor wafer, and solder bumps are formed on the electrode pad, and are formed on a package substrate having an electrical contact pad. The solder bumps on the surface of the electrical contact pad are electrically connected by the solder bumps and the solder bumps to provide electrical connection between the semiconductor wafer and the package substrate.

相較於傳統的打線接合(Wire Bond)技術，覆晶技術之特徵在於半導體晶片與封裝基板間的電性連接係透過焊錫凸塊而非一般之金線，而該種覆晶技術之優點在於其可提高封裝密度以降低封裝元件尺寸；同時，該種覆晶技術不需使用長度較長之金線，以降低阻抗，故可提高電性連接的性能。Compared with the conventional wire bonding technology, the flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is transmitted through the solder bumps instead of the general gold wires, and the chipping technique has the advantage that It can increase the packing density to reduce the size of the package components. At the same time, the flip chip technology does not need to use a long length of gold wire to reduce the impedance, thereby improving the performance of the electrical connection.

由於越來越多的產品設計趨向小型化，因此，覆晶技術亦朝向高I/O數、細間距之趨勢發展。然而，隨著防焊層開孔與導電凸塊間距(bump pitch)的縮小，利用印刷錫的方式製作導電凸塊係為業界解決低良率及高治具成本的手段之一。As more and more product designs tend to be miniaturized, flip chip technology is also moving toward high I/O counts and fine pitches. However, as the solder mask opening and the bump pitch are reduced, the use of printed tin to form conductive bumps is one of the means for the industry to solve the problem of low yield and high fixture cost.

請參閱第1A至1F圖，係說明一種習知的封裝基板製作電性連接結構之製法的示意圖；如第1A圖所示，係提 供一基板本體10，該基板本體10之至少一表面形成有複數電性接觸墊101，於該基板本體10的表面上形成有一防焊層11，該防焊層11中形成有複數開孔110以對應露出各該電性接觸墊101；如第1B圖所示，於該防焊層11上設有一網版13，且該網版13具有與該電性接觸墊101相對應之網孔130，以露出該電性接觸墊101，為避免受限於對位精度，故該網版13之網孔130均大於該防焊層11之開孔110；如第1C圖所示，該網孔130中塗佈有焊錫材料以形成焊接材料14；如第1D圖所示，移除該網版13以露出該焊接材料14；如第1E圖所示，該焊接材料14經廻焊以形成焊料球14’；如第1F圖所示，提供一半導體晶片15，且該半導體晶片15具有複數電極墊150，於該電極墊150上形成有焊料凸塊，令該焊料凸塊對應連接該焊料球14’，並經廻焊製程以形成焊球14”，令該半導體晶片15電性連接至該基板本體10，並於該防焊層11與半導體晶片15之間填入底充材料16，以加強該基板本體10與半導體晶片15之間的結合強度。Please refer to FIGS. 1A to 1F for a schematic diagram of a conventional method for fabricating an electrical connection structure of a package substrate; as shown in FIG. 1A, A plurality of electrical contact pads 101 are formed on at least one surface of the substrate body 10. A solder resist layer 11 is formed on the surface of the substrate body 10. The plurality of openings 110 are formed in the solder resist layer 11. Correspondingly exposing each of the electrical contact pads 101; as shown in FIG. 1B, a screen 13 is disposed on the solder resist layer 11, and the screen 13 has a mesh 130 corresponding to the electrical contact pads 101. In order to expose the electrical contact pad 101, in order to avoid being limited by the alignment accuracy, the mesh 130 of the screen 13 is larger than the opening 110 of the solder resist layer 11; as shown in FIG. 1C, the mesh 130 is coated with a solder material to form a solder material 14; as shown in FIG. 1D, the screen 13 is removed to expose the solder material 14; as shown in FIG. 1E, the solder material 14 is soldered to form solder a ball 14'; as shown in FIG. 1F, a semiconductor wafer 15 is provided, and the semiconductor wafer 15 has a plurality of electrode pads 150, and solder bumps are formed on the electrode pads 150, so that the solder bumps are connected to the solder balls. 14', and through a soldering process to form a solder ball 14", the semiconductor wafer 15 is electrically connected to the substrate 10, the semiconductor wafer 11 and in the solder resist layer 16 is filled between the underfill material 15, to enhance the bonding strength between the main body 15 of the substrate 10 and the semiconductor wafer.

惟，隨著防焊層11開孔110的孔徑及間距縮小，利用印刷形成焊料球14’的方式，受限於網版13製作的難度增加、成本上升與良率下降等問題，利用植球方式製作凸塊已成為覆晶基板朝向細線路間距的解決方案之一，但該防焊層11必須維持一定厚度，而該防焊層11開孔110的孔徑及間距縮小，深寬比(aspect ratio)越大，則焊料球14’之直徑就愈小，使該焊料球14’廻焊後，無法有 效填滿開孔110，且該基板本體10與半導體晶片15之間的離板間距(standoff)更小，導致該底充材料16分散不均勻，而不易填滿該基板本體10與半導體晶片15之間的離板間距，衍生品質可靠度等問題。However, as the aperture and the pitch of the opening 110 of the solder resist layer 11 are reduced, the manner in which the solder ball 14' is formed by printing is limited by the difficulty in the production of the screen 13, the increase in cost, and the decrease in yield. The method of forming bumps has become one of the solutions for the flip chip substrate toward the fine line pitch, but the solder resist layer 11 must maintain a certain thickness, and the aperture and pitch of the solder mask layer opening 110 are reduced, and the aspect ratio (aspect) The larger the ratio, the smaller the diameter of the solder ball 14', so that the solder ball 14' can not be soldered after soldering The opening 110 is filled, and the standoff between the substrate body 10 and the semiconductor wafer 15 is smaller, resulting in uneven dispersion of the underfill material 16 and not easily filling the substrate body 10 and the semiconductor wafer 15 . The problem of the distance between the board and the quality of the derivative.

請參閱第2A至2H圖，係說明另一種習知的封裝基板製作電性連接結構之製法的示意圖。Please refer to FIGS. 2A to 2H for explaining a schematic view of another conventional method for fabricating an electrical connection structure of a package substrate.

如第2A圖所示，係於一表面形成有複數電性接觸墊201之基板本體20，於該基板本體20上形成防焊層21，且於該防焊層21中形成複數開孔210以對應露出各該電性接觸墊201。As shown in FIG. 2A, a substrate body 20 having a plurality of electrical contact pads 201 is formed on a surface thereof, a solder resist layer 21 is formed on the substrate body 20, and a plurality of openings 210 are formed in the solder resist layer 21. Correspondingly, each of the electrical contact pads 201 is exposed.

如第2B圖所示，接著於該電性接觸墊201、防焊層21表面及開孔210之孔壁上形成第一導電層22a。As shown in FIG. 2B, a first conductive layer 22a is formed on the surface of the electrical contact pad 201, the solder resist layer 21, and the opening 210.

如第2C圖所示，於該第一導電層22a上形成第一阻層23a，且該第一阻層23a中形成有複數個第一開口230a，該第一開口230a之尺寸係大於該防焊層21之開孔210尺寸，以對應露出形成於該電性接觸墊201上之第一導電層22a。As shown in FIG. 2C, a first resist layer 23a is formed on the first conductive layer 22a, and a plurality of first openings 230a are formed in the first resist layer 23a. The size of the first opening 230a is greater than the The opening 210 of the solder layer 21 is sized to correspondingly expose the first conductive layer 22a formed on the electrical contact pad 201.

如第2D圖所示，接著藉由該第一導電層22a作為電鍍(Electroplating)製程之電流傳導路徑，以於該電性接觸墊201上形成第一銅柱24a。As shown in FIG. 2D, the first conductive layer 22a is then used as a current conduction path of an electroplating process to form a first copper pillar 24a on the electrical contact pad 201.

如第2E圖所示，移除該第一阻層23a及其所覆蓋之第一導電層22a，以露出該第一銅柱24a，且該第一銅柱24a係突出於該防焊層21之表面。As shown in FIG. 2E, the first resistive layer 23a and the first conductive layer 22a covered by the first resistive layer 23a are removed to expose the first copper pillar 24a, and the first copper pillar 24a protrudes from the solder resist layer 21. The surface.

如第2F圖所示，於該第一銅柱24a上形成表面處理 層25。Forming a surface treatment on the first copper pillar 24a as shown in FIG. 2F Layer 25.

如第2G圖所示，提供一具有複數電極墊260之半導體晶片26，各該電極墊260上具有焊料凸塊261，且該些第一銅柱24a對應各該焊料凸塊261。As shown in FIG. 2G, a semiconductor wafer 26 having a plurality of electrode pads 260 is provided, each of which has solder bumps 261 thereon, and the first copper pillars 24a correspond to the solder bumps 261.

如第2H圖所示，廻焊該焊料凸塊261及表面處理層25以形成焊料262，令該半導體晶片26藉由該焊料262包覆該第一銅柱24a，以電性連接至該基板本體20，且於該基板本體20與半導體晶片26之間注入底充材料27，以加強該基板本體20與半導體晶片26之間的結合強度。As shown in FIG. 2H, the solder bump 261 and the surface treatment layer 25 are soldered to form the solder 262, and the semiconductor wafer 26 is coated with the first copper pillar 24a by the solder 262 to be electrically connected to the substrate. The substrate 20 is filled with an underfill material 27 between the substrate body 20 and the semiconductor wafer 26 to enhance the bonding strength between the substrate body 20 and the semiconductor wafer 26.

惟，上述習知之製法，由於隨著半導體晶片26之電極墊260尺寸及間距變小，該電極墊260上的焊料凸塊261用量亦變少，該基板本體20之電性接觸墊201卻受限於製程能力，難以有效地縮小尺寸及間距，致使電性接觸墊201與電極墊260之尺寸相差愈大，該電極墊260上的焊料凸塊261與電性接觸墊201上的第一銅柱24a的尺寸亦相差更大，當廻焊該焊料凸塊261及第一銅柱24a上之表面處理層25時，常因焊料量不足，無法有效包覆第一銅柱24a，而產生應力不均勻，甚至造成連接界面的破裂等問題。However, in the above conventional method, since the size and pitch of the electrode pads 260 of the semiconductor wafer 26 become smaller, the amount of the solder bumps 261 on the electrode pads 260 is also less, and the electrical contact pads 201 of the substrate body 20 are affected by the above. Limited to the process capability, it is difficult to effectively reduce the size and spacing, so that the difference between the size of the electrical contact pad 201 and the electrode pad 260 is greater, the solder bumps 261 on the electrode pads 260 and the first copper on the electrical contact pads 201 The size of the pillars 24a is also different. When the solder bumps 261 and the surface treatment layer 25 on the first copper pillars 24a are soldered, the first copper pillars 24a cannot be effectively covered due to insufficient solder amount, and stress is generated. It is uneven, and even causes problems such as cracking of the connection interface.

因此，鑒於上述之問題，如何克服習知技術不易提供基板本體與半導體晶片之間較大的離板間距，且容易造成連接界面的應力分佈不均勻等問題，實已成目前亟欲解決的課題。Therefore, in view of the above problems, how to overcome the problem that the prior art is difficult to provide a large off-board spacing between the substrate body and the semiconductor wafer, and easily cause uneven stress distribution at the connection interface has become a problem to be solved at present. .

鑒於上述習知技術之缺點，本發明之主要目的係提供一種封裝基板及其製法，能提供高離板間距，形成細間距的基板電性連接結構，並避免後續封裝之底充材料填充不確實之缺失。In view of the above disadvantages of the prior art, the main object of the present invention is to provide a package substrate and a method for manufacturing the same, which can provide a high off-board pitch, form a fine pitch substrate electrical connection structure, and avoid the filling of the underfill material of the subsequent package. Missing.

為達上述目的及其他目的，本發明揭露一種封裝基板，係包括：基板本體，於至少一表面具有複數電性接觸墊，且該基板本體上設有防焊層，於該防焊層中設有複數開孔，以對應外露出各該電性接觸墊；第一銅柱，係設於該電性接觸墊上，且該第一銅柱凸出於該防焊層之表面；以及第二銅柱，係設於該第一銅柱上，且該第二銅柱之直徑小於該第一銅柱之直徑。To achieve the above and other objects, the present invention discloses a package substrate, comprising: a substrate body having a plurality of electrical contact pads on at least one surface, and a solder resist layer disposed on the substrate body, wherein the solder resist layer is disposed in the solder resist layer a plurality of openings for respectively exposing the respective electrical contact pads; a first copper pillar is disposed on the electrical contact pad, and the first copper pillar protrudes from a surface of the solder resist layer; and the second copper The column is disposed on the first copper pillar, and the diameter of the second copper pillar is smaller than the diameter of the first copper pillar.

依上述之封裝基板，復包括表面處理層，係設於該第一銅柱凸出於該防焊層之表面及該第二銅柱之表面上。According to the above package substrate, the surface treatment layer is further disposed on the surface of the first copper pillar protruding from the solder resist layer and the surface of the second copper pillar.

又依上述之封裝基板，復包括焊料凸塊，係設於該第二銅柱上。According to the above package substrate, the solder bump is further included on the second copper pillar.

依上述之結構，復包括焊料球，係設於該第二銅柱上。According to the above structure, the solder ball is further included on the second copper pillar.

又依上述之結構，復包括第一導電層，係設於該電性接觸墊與第一銅柱之間、以及該防焊層之開孔與第一銅柱之間，復包括第二導電層，係設於該第一銅柱及第二銅柱之間。According to the above structure, the first conductive layer is further disposed between the electrical contact pad and the first copper pillar, and between the opening of the solder resist layer and the first copper pillar, and includes a second conductive The layer is disposed between the first copper pillar and the second copper pillar.

本發明復提供一種封裝基板之製法，係包括：提供至少一表面形成有複數電性接觸墊之基板本體，且於該基板本體上形成防焊層，於該防焊層中形成有複數開孔，以對應外露出各該電性接觸墊；於該電性接觸墊與防焊層上電 鍍形成第一銅柱；以及於該第一銅柱上電鍍形成第二銅柱，其中，該第二銅柱之直徑係小於該第一銅柱之直徑。The invention provides a method for manufacturing a package substrate, comprising: providing a substrate body having at least one surface formed with a plurality of electrical contact pads, forming a solder resist layer on the substrate body, and forming a plurality of openings in the solder resist layer Correspondingly exposing each of the electrical contact pads; powering the electrical contact pads and the solder resist layer Forming a first copper pillar; and plating a second copper pillar on the first copper pillar, wherein the diameter of the second copper pillar is smaller than the diameter of the first copper pillar.

依上述之封裝基板製法，其中，該第一銅柱之製法，係包括：於該電性接觸墊、防焊層及其開孔之孔壁上形成第一導電層；於該第一導電層上形成第一阻層，該第一阻層形成有複數第一開口，以對應露出各該電性接觸墊上之第一導電層，且該第一開口之尺寸大於該防焊層之開孔之尺寸；於該第一開口中電鍍形成第一銅柱；以及移除該第一阻層及其所覆蓋之第一導電層，以露出該第一銅柱。According to the above method for manufacturing a package substrate, the first copper pillar is formed by: forming a first conductive layer on the electrical contact pad, the solder resist layer and the hole wall of the opening; and the first conductive layer Forming a first resistive layer, the first resistive layer is formed with a plurality of first openings to correspondingly expose the first conductive layer on each of the electrical contact pads, and the size of the first opening is larger than the opening of the solder resist layer Dimensing; forming a first copper pillar in the first opening; and removing the first resistive layer and the first conductive layer covered thereby to expose the first copper pillar.

依上述之製法，其中，該第二銅柱之製法，係包括：於該第一銅柱及防焊層上形成第二導電層；於該第二導電層上形成第二阻層，該第二阻層形成有複數第二開口，以對應露出該第一銅柱，且該第二開口之尺寸小於該第一銅柱之直徑；於該第二開口中電鍍形成第二銅柱；以及移除該第二阻層及其所覆蓋之第二導電層，以露出該第一銅柱及第二銅柱。According to the above method, the second copper pillar is formed by: forming a second conductive layer on the first copper pillar and the solder resist layer; forming a second resist layer on the second conductive layer, the first The second resist layer is formed with a plurality of second openings to correspondingly expose the first copper pillar, and the second opening has a size smaller than a diameter of the first copper pillar; a second copper pillar is electroplated in the second opening; and The second resistive layer and the second conductive layer covered by the second resistive layer are exposed to expose the first copper pillar and the second copper pillar.

依上所述，復包括於該第一銅柱及第二銅柱之表面形成表面處理層；該封裝基板亦可於該第二銅柱上電鍍形成焊料凸塊，或於該第二銅柱上植球形成焊料球。According to the above, a surface treatment layer is formed on the surface of the first copper pillar and the second copper pillar; the package substrate can also be plated on the second copper pillar to form a solder bump, or the second copper pillar The ball is implanted to form a solder ball.

本發明之封裝基板及其製法，主要係在基板本體之防焊層及電性接觸墊上電鍍形成該第一銅柱，該第一銅柱突出於該防焊層表面，又於該第一銅柱上電鍍形成第二銅柱，其中，該第二銅柱之直徑係小於該第一銅柱之直徑，藉由第一銅柱與第二銅柱可保持該半導體晶片與基板本 體之間的較大離板間距，以利於該底充材料填滿該半導體晶片與基板本體之間，而避免該底充材料分散不均勻，導致品質可靠度等問題，且當隨著晶片之電極墊尺寸及間距變小，該第二銅柱亦可易於隨之縮小，使該第二銅柱之尺寸較接近電極墊之尺寸，因此以焊料作連接時，其應力分佈會較為均勻，所以可靠度較高；再者，小直徑的第二銅柱經廻焊而為焊料所包覆時，即使各該電性接觸墊的間距縮小，焊料與焊料之間仍具有足夠距離，可免於焊料之間的橋接現象，故可利於形成細間距的基板電性連接結構。The package substrate of the present invention is mainly formed by electroplating the solder resist layer and the electrical contact pad of the substrate body to form the first copper pillar, the first copper pillar protruding from the surface of the solder resist layer, and the first copper Forming a second copper pillar on the pillar, wherein the diameter of the second copper pillar is smaller than the diameter of the first copper pillar, and the semiconductor wafer and the substrate can be maintained by the first copper pillar and the second copper pillar a large off-board spacing between the bodies to facilitate filling of the underfill material between the semiconductor wafer and the substrate body, thereby avoiding uneven dispersion of the underfill material, resulting in problems such as quality reliability, and when The size and spacing of the electrode pads are reduced, and the second copper pillar can be easily reduced, so that the size of the second copper pillar is closer to the size of the electrode pad. Therefore, when the solder is connected, the stress distribution is relatively uniform, so The reliability is higher; in addition, when the second copper pillar of small diameter is covered by soldering by soldering, even if the spacing of each of the electrical contact pads is reduced, the solder and the solder have sufficient distance between the solder and the solder. The bridging phenomenon between the solders can facilitate the formation of a fine pitch substrate electrical connection structure.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

請參閲第3A至3K圖，係為詳細説明本發明之電性接觸墊上形成第一銅柱及第二銅柱之實施例之剖面示意圖。Please refer to FIGS. 3A to 3K for a detailed cross-sectional view showing an embodiment in which the first copper pillar and the second copper pillar are formed on the electrical contact pad of the present invention.

如第3A圖所示，係於一表面形成有複數電性接觸墊201之基板本體20，於該基板本體20上形成有防焊層21，且於該防焊層21中形成複數開孔210以對應外露出各該電性接觸墊201；該基板本體20之內部結構型式繁多，惟乃業界所周知，且其非本案技術特徵，故於本發明之實施例中並未圖示，特此述明。As shown in FIG. 3A, a substrate body 20 having a plurality of electrical contact pads 201 is formed on a surface thereof. A solder resist layer 21 is formed on the substrate body 20, and a plurality of openings 210 are formed in the solder resist layer 21. The internal contact pads 201 are exposed in a corresponding manner; the internal structure of the substrate body 20 is various, but is well known in the industry, and is not a technical feature of the present invention. Therefore, it is not illustrated in the embodiment of the present invention. Bright.

如第3B圖所示，接著於該電性接觸墊201、防焊層21表面及開孔210之孔壁上形成第一導電層22a；該第一導電層22a主要作為後述電鍍金屬材料所需之電流傳導 路徑，其可由金屬或沉積數層金屬層所構成，如選自銅、錫、鎳、鉻、鈦等單層金屬、或銅－鉻或錫－鉛等多層金屬結構，或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導電高分子材料。As shown in FIG. 3B, a first conductive layer 22a is formed on the surface of the electrical contact pad 201, the surface of the solder resist 21, and the opening 210; the first conductive layer 22a is mainly used as a plating metal material to be described later. Current conduction a path which may be composed of a metal or a plurality of deposited metal layers, such as a single layer metal selected from the group consisting of copper, tin, nickel, chromium, titanium, or a multilayer metal structure such as copper-chromium or tin-lead, or may be used, for example, polyacetylene. , conductive polymer materials such as polyaniline or organic sulfur polymer.

如第3C圖所示，於該第一導電層22a上形成第一阻層23a，該第一阻層23a係為乾膜之光阻層(photoresist)，其係利用例如貼合等方式形成於該第一導電層22a表面，再藉由曝光、顯影等方式加以圖案化，使該第一阻層23a中形成有複數個第一開口230a，且各該第一開口230a大於該防焊層21之開孔210，以對應露出形成於該電性接觸墊201上之第一導電層22a。As shown in FIG. 3C, a first resist layer 23a is formed on the first conductive layer 22a, and the first resist layer 23a is a photoresist layer of a dry film, which is formed by, for example, bonding. The surface of the first conductive layer 22a is patterned by exposure, development, etc., so that a plurality of first openings 230a are formed in the first resist layer 23a, and each of the first openings 230a is larger than the solder resist layer 21. The opening 210 is formed to correspondingly expose the first conductive layer 22a formed on the electrical contact pad 201.

如第3D圖所示，藉由該第一導電層22a作為電鍍(electroplating)製程之電流傳導路徑，以於該電性接觸墊201上電鍍形成第一銅柱24a。As shown in FIG. 3D, the first conductive layer 22a is used as a current conduction path of an electroplating process to form a first copper pillar 24a on the electrical contact pad 201.

如第3E圖所示，移除該第一阻層23a及其所覆蓋之第一導電層22a，以露出該第一銅柱24a，且該第一銅柱24a係突出於該防焊層21之表面；其中，移除該第一阻層23a及第一導電層22a之製程係屬習知者，故於此不再為文贅述。As shown in FIG. 3E, the first resistive layer 23a and the first conductive layer 22a covered by the first resistive layer 23a are removed to expose the first copper pillar 24a, and the first copper pillar 24a protrudes from the solder resist layer 21. The process of removing the first resistive layer 23a and the first conductive layer 22a is a conventional one, and thus will not be described herein.

如第3F圖所示，於該防焊層21、第一銅柱24a上形成第二導電層22b。As shown in FIG. 3F, a second conductive layer 22b is formed on the solder resist layer 21 and the first copper pillar 24a.

如第3G圖所示，於該第二導電層22b上形成第二阻層23b，且於該第二阻層23b中形成有對應該第一銅柱24a之第二開口230b，以露出該第二導電層22b之部份表面， 且該第二開口230b小於該第一銅柱24a之外徑。As shown in FIG. 3G, a second resist layer 23b is formed on the second conductive layer 22b, and a second opening 230b corresponding to the first copper pillar 24a is formed in the second resist layer 23b to expose the first a part of the surface of the second conductive layer 22b, The second opening 230b is smaller than the outer diameter of the first copper post 24a.

如第3H圖所示，進行電鍍製程，藉由該第二導電層22b作為電鍍時之電流傳導路徑，以在該第二阻層23b之第二開口230b中的第一銅柱24a上電鍍形成第二銅柱24b。As shown in FIG. 3H, an electroplating process is performed, and the second conductive layer 22b is used as a current conduction path during electroplating to be plated on the first copper pillar 24a in the second opening 230b of the second resist layer 23b. The second copper post 24b.

如第3I圖所示，移除該第二阻層23b及其所覆蓋之第二導電層22b，以露出該第一銅柱24a及第二銅柱24b，且該第二銅柱24b之直徑係小於該第一銅柱24a之直徑；其中，移除該第二阻層23b及第二導電層22b之製程係屬習知者，故於此不再為文贅述。As shown in FIG. 3I, the second resistive layer 23b and the second conductive layer 22b covered thereon are removed to expose the first copper pillar 24a and the second copper pillar 24b, and the diameter of the second copper pillar 24b The method is smaller than the diameter of the first copper pillar 24a; wherein the process of removing the second resistive layer 23b and the second conductive layer 22b is a conventional one, and thus will not be described herein.

如第3J圖所示，於該第一銅柱24a外露之表面與第二銅柱24b之表面進行表面處理，以於該第一銅柱24a與第二銅柱24b上形成表面處理層25，亦可以電鍍方式於第二銅柱24b上形成焊料凸塊(圖式中未表示)，或以植球方式於第二銅柱24b上形成焊料球(圖式中未表示)。As shown in FIG. 3J, the exposed surface of the first copper pillar 24a and the surface of the second copper pillar 24b are surface-treated to form a surface treatment layer 25 on the first copper pillar 24a and the second copper pillar 24b. Solder bumps (not shown) may be formed on the second copper pillars 24b by electroplating, or solder balls may be formed on the second copper pillars 24b by ball implantation (not shown in the drawings).

如第3K圖所示，提供一具有複數電極墊260之半導體晶片26，各該電極墊260上具有焊料凸塊，且該些第一銅柱24a對應各該焊料凸塊，並進行廻焊製程，以形成焊料262，令該半導體晶片26藉由包覆在該第二銅柱24b上的焊料262以電性連接至該基板本體20，並於該基板本體20與半導體晶片26之間注入底充材料27，以加強該基板本體20與半導體晶片26之間的結合強度。由於該電性接觸墊201上形成有該第一銅柱24a及第二銅柱24b，且該第二銅柱24b直徑小於該第一銅柱24a直徑， 因此該焊料262能結合在該第一銅柱24a及第二銅柱24b上以電性連接至該半導體晶片26。As shown in FIG. 3K, a semiconductor wafer 26 having a plurality of electrode pads 260 is provided. Each of the electrode pads 260 has solder bumps thereon, and the first copper pillars 24a correspond to the solder bumps, and the soldering process is performed. The solder 262 is formed to electrically connect the semiconductor wafer 26 to the substrate body 20 by solder 262 coated on the second copper pillar 24b, and a bottom is injected between the substrate body 20 and the semiconductor wafer 26. The material 27 is filled to reinforce the bonding strength between the substrate body 20 and the semiconductor wafer 26. The first copper pillar 24a and the second copper pillar 24b are formed on the electrical contact pad 201, and the diameter of the second copper pillar 24b is smaller than the diameter of the first copper pillar 24a. Therefore, the solder 262 can be bonded to the first copper pillar 24a and the second copper pillar 24b to be electrically connected to the semiconductor wafer 26.

本發明復提供一種封裝基板，係包括：基板本體20，於至少一表面具有複數電性接觸墊201，且該基板本體20上形成有防焊層21，於該防焊層21中形成有複數開孔210，以對應外露出各該電性接觸墊201；第一銅柱24a，係形成於該電性接觸墊201上，且該第一銅柱24a並凸出於該防焊層21之表面；以及第二銅柱24b，係設於該第一銅柱24a上，且該第二銅柱24b之直徑小於該第一銅柱24a之直徑。The present invention further provides a package substrate, comprising: a substrate body 20 having a plurality of electrical contact pads 201 on at least one surface thereof, and a solder resist layer 21 formed on the substrate body 20, and a plurality of solder resist layers 21 are formed in the solder resist layer 21. The first copper pillar 24a is formed on the electrical contact pad 201, and the first copper pillar 24a protrudes from the solder resist layer 21, and the first copper pillar 24a is formed on the electrical contact pad 201. And a second copper pillar 24b is disposed on the first copper pillar 24a, and the diameter of the second copper pillar 24b is smaller than the diameter of the first copper pillar 24a.

依上述之結構，復包括有第一導電層22a，係形成於該電性接觸墊201與第一銅柱24a之間、以及防焊層21之開孔210與第一銅柱24a之間；復包括有第二導電層22b，係形成於該第一銅柱24a及第二銅柱24b之間。According to the above structure, the first conductive layer 22a is formed between the electrical contact pad 201 and the first copper pillar 24a, and between the opening 210 of the solder resist layer 21 and the first copper pillar 24a; The second conductive layer 22b is formed between the first copper pillar 24a and the second copper pillar 24b.

依上所述，復包括表面處理層25，係形成於該第一銅柱24a凸出於該防焊層21之表面及第二銅柱24b之表面上。According to the above, the surface treatment layer 25 is formed on the surface of the first copper pillar 24a protruding from the solder resist layer 21 and the surface of the second copper pillar 24b.

本發明之封裝基板及其製法，主要係在基板本體之防焊層及電性接觸墊上電鍍形成該第一銅柱，該第一銅柱突出於該防焊層表面，又於該第一銅柱上電鍍形成第二銅柱；其中，該第二銅柱之直徑係小於該第一銅柱之直徑，藉由該第一銅柱與第二銅柱以保持該半導體晶片與基板本體之間有較大之離板間距，以利於該底充材料填滿該半導體晶片與基板本體之間，而避免該底充材料分散不均 勻，影響品質可靠度等問題，且當隨著半導體晶片之電極墊尺寸及間距變小，該第二銅柱亦可易於隨之縮小，令該第二銅柱之尺寸較接近電極墊之尺寸，因此以焊料作連接時，其應力分佈會較為均勻，以提高可靠度；再者，小直徑的第二銅柱經廻焊而為焊料所包覆時，即使各該電性接觸墊的間距縮小，焊料與焊料之間仍具有足夠距離，可免於焊料之間的橋接現象，故可利於形成細間距的基板電性連接結構。The package substrate of the present invention is mainly formed by electroplating the solder resist layer and the electrical contact pad of the substrate body to form the first copper pillar, the first copper pillar protruding from the surface of the solder resist layer, and the first copper Forming a second copper pillar on the pillar; wherein the diameter of the second copper pillar is smaller than the diameter of the first copper pillar, and the first copper pillar and the second copper pillar are used to maintain the semiconductor wafer and the substrate body There is a large off-board spacing to facilitate the filling of the underfill material between the semiconductor wafer and the substrate body to avoid uneven dispersion of the underfill material Uniformity, affecting quality reliability and the like, and as the size and spacing of the electrode pads of the semiconductor wafer become smaller, the second copper pillar can be easily reduced, so that the size of the second copper pillar is closer to the size of the electrode pad Therefore, when solder is used for connection, the stress distribution is relatively uniform to improve reliability; further, when the second copper column of small diameter is covered by solder for soldering, even if the distance of each of the electrical contact pads is Reducing, there is still a sufficient distance between the solder and the solder to avoid the bridging phenomenon between the solders, so that the fine-pitch substrate electrical connection structure can be formed.

上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

10、20‧‧‧基板本體10, 20‧‧‧ substrate body

101、201‧‧‧電性接觸墊101, 201‧‧‧Electrical contact pads

11、21‧‧‧防焊層11, 21‧‧‧ solder mask

110、210‧‧‧開孔110, 210‧‧‧ openings

13‧‧‧網版13‧‧‧ Screen

130‧‧‧網孔130‧‧‧Mesh

14‧‧‧焊接材料14‧‧‧Welding materials

14’‧‧‧焊料球14'‧‧‧ solder balls

14”‧‧‧焊球14"‧‧‧ solder balls

15、26‧‧‧半導體晶片15, 26‧‧‧ semiconductor wafer

150、260‧‧‧電極墊150, 260‧‧‧ electrode pads

16、27‧‧‧底充材料16, 27‧‧‧ bottom material

22a‧‧‧第一導電層22a‧‧‧First conductive layer

22b‧‧‧第二導電層22b‧‧‧Second conductive layer

23a‧‧‧第一阻層23a‧‧‧First barrier layer

230a‧‧‧第一開口230a‧‧ first opening

23b‧‧‧第二阻層23b‧‧‧second barrier layer

230b‧‧‧第二開口230b‧‧‧second opening

24a‧‧‧第一銅柱24a‧‧‧First copper column

24b‧‧‧第二銅柱24b‧‧‧second copper column

25‧‧‧表面處理層25‧‧‧Surface treatment layer

261‧‧‧焊料凸塊261‧‧‧ solder bumps

262‧‧‧焊料262‧‧‧ solder

第1A至1F圖係為習知封裝基板之製法之剖面示意圖；第2A至2H圖係為習知封裝基板之另一製法之剖面示意圖；以及第3A至3K圖係為本發明封裝基板之製法之剖面示意圖。1A to 1F are schematic cross-sectional views showing a method of manufacturing a conventional package substrate; FIGS. 2A to 2H are schematic cross-sectional views showing another method of manufacturing a package substrate; and FIGS. 3A to 3K are diagrams showing a method of manufacturing a package substrate of the present invention; Schematic diagram of the section.

20‧‧‧基板本體20‧‧‧Substrate body

201‧‧‧電性接觸墊201‧‧‧Electrical contact pads

21‧‧‧防焊層21‧‧‧ solder mask

210‧‧‧開孔210‧‧‧Opening

22a‧‧‧第一導電層22a‧‧‧First conductive layer

22b‧‧‧第二導電層22b‧‧‧Second conductive layer

24a‧‧‧第一銅柱24a‧‧‧First copper column

24b‧‧‧第二銅柱24b‧‧‧second copper column

Claims (12)

一種封裝基板，係包括：基板本體，係於至少一表面具有複數電性接觸墊，且該基板本體上設有防焊層，於該防焊層中設有複數開孔，以對應外露出各該電性接觸墊；第一銅柱，係設於該電性接觸墊上，且該第一銅柱凸出於該防焊層之表面；以及第二銅柱，係設於該第一銅柱上，且該第二銅柱之直徑小於該第一銅柱之直徑。A package substrate includes: a substrate body having a plurality of electrical contact pads on at least one surface, and a solder resist layer disposed on the substrate body, wherein the solder resist layer is provided with a plurality of openings for correspondingly exposing each The first copper pillar is disposed on the electrical contact pad, and the first copper pillar protrudes from the surface of the solder resist layer; and the second copper pillar is disposed on the first copper pillar And the diameter of the second copper pillar is smaller than the diameter of the first copper pillar. 如申請專利範圍第1項之封裝基板，復包括第一導電層，係設於該電性接觸墊與第一銅柱之間、以及該防焊層之開孔與第一銅柱之間。The package substrate of claim 1, further comprising a first conductive layer disposed between the electrical contact pad and the first copper pillar and between the opening of the solder resist layer and the first copper pillar. 如申請專利範圍第1項之封裝基板，復包括表面處理層，係設於該第一銅柱外露出之表面及該第二銅柱之表面上。The package substrate of claim 1, further comprising a surface treatment layer disposed on a surface exposed outside the first copper pillar and on a surface of the second copper pillar. 如申請專利範圍第1項之封裝基板，復包括焊料凸塊，係設於該第二銅柱上。The package substrate of claim 1 is further comprising a solder bump disposed on the second copper pillar. 如申請專利範圍第1項之封裝基板，復包括焊料球，係設於該第二銅柱上。The package substrate of claim 1 is further comprising a solder ball disposed on the second copper pillar. 如申請專利範圍第1項之封裝基板，復包括第二導電層，係設於該第一銅柱與第二銅柱之間。The package substrate of claim 1, further comprising a second conductive layer disposed between the first copper pillar and the second copper pillar. 一種封裝基板之製法，係包括：提供至少一表面形成有複數電性接觸墊之基板本體，且於該基板本體上形成防焊層，於該防焊層中 形成有複數開孔，以對應外露出各該電性接觸墊；於該電性接觸墊與該防焊層上電鍍形成第一銅柱；以及於該第一銅柱上電鍍形成第二銅柱，且該第二銅柱之直徑係小於該第一銅柱之直徑。A method for manufacturing a package substrate, comprising: providing a substrate body having at least one surface formed with a plurality of electrical contact pads, and forming a solder resist layer on the substrate body, in the solder resist layer Forming a plurality of openings to correspondingly expose the respective electrical contact pads; forming a first copper pillar on the electrical contact pad and the solder resist layer; and plating a second copper pillar on the first copper pillar And the diameter of the second copper pillar is smaller than the diameter of the first copper pillar. 如申請專利範圍第7項之封裝基板製法，其中，該第一銅柱之製法，係包括：於該電性接觸墊、防焊層及其開孔之孔壁上形成第一導電層；於該第一導電層上形成第一阻層，該第一阻層形成有複數第一開口，以對應露出各該電性接觸墊上之第一導電層，且該第一開口大於該防焊層之開孔；於該第一開口中電鍍形成第一銅柱；以及移除該第一阻層及其所覆蓋之第一導電層，以露出該第一銅柱。The method for manufacturing a package substrate according to the seventh aspect of the invention, wherein the first copper pillar is formed by: forming a first conductive layer on the electrical contact pad, the solder resist layer and the opening wall of the opening; Forming a first resist layer on the first conductive layer, the first resistive layer is formed with a plurality of first openings to correspondingly expose the first conductive layer on each of the electrical contact pads, and the first opening is larger than the solder resist layer Opening a hole; forming a first copper pillar in the first opening; and removing the first resist layer and the first conductive layer covered thereby to expose the first copper pillar. 如申請專利範圍第7項之封裝基板製法，其中，該第二銅柱之製法，係包括：於該第一銅柱及該防焊層上形成第二導電層；於該第二導電層上形成第二阻層，該第二阻層形成有複數第二開口，以對應露出該第一銅柱，且該第二開口小於該第一銅柱之直徑；於該第二開口中電鍍形成第二銅柱；以及移除該第二阻層及其所覆蓋之第二導電層，以露出該第一銅柱及第二銅柱。The method for manufacturing a package substrate according to the seventh aspect of the invention, wherein the second copper pillar is formed by: forming a second conductive layer on the first copper pillar and the solder resist layer; and on the second conductive layer Forming a second resist layer, the second resistive layer is formed with a plurality of second openings to correspondingly expose the first copper pillar, and the second opening is smaller than a diameter of the first copper pillar; and forming a plating in the second opening a second copper pillar; and removing the second resistive layer and the second conductive layer covered thereby to expose the first copper pillar and the second copper pillar. 如申請專利範圍第7項之封裝基板製法，復包括於該第一銅柱外露之表面及第二銅柱之表面形成表面處理層。The method for manufacturing a package substrate according to claim 7 further comprises forming a surface treatment layer on the exposed surface of the first copper pillar and the surface of the second copper pillar. 如申請專利範圍第7項之封裝基板製法，復包括於該第二銅柱上電鍍形成焊料凸塊。The method for manufacturing a package substrate according to claim 7 is characterized in that the second copper pillar is electroplated to form a solder bump. 如申請專利範圍第7項之封裝基板製法，復包括於該第二銅柱上植球形成焊料球。For example, in the method of manufacturing a package substrate according to claim 7, the ball is further included on the second copper pillar to form a solder ball.
TW097144626A 2008-11-19 2008-11-19 Package substrate and fabrication method thereof TWI407538B (en)

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TW200828464A (en) * 2006-12-28 2008-07-01 Siliconware Precision Industries Co Ltd Semiconductor device having conductive bumps and fabrication methodthereof

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