TW201021182A - Package substrate and fabrication method thereof - Google Patents

Package substrate and fabrication method thereof Download PDF

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Publication number
TW201021182A
TW201021182A TW097144626A TW97144626A TW201021182A TW 201021182 A TW201021182 A TW 201021182A TW 097144626 A TW097144626 A TW 097144626A TW 97144626 A TW97144626 A TW 97144626A TW 201021182 A TW201021182 A TW 201021182A
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TW
Taiwan
Prior art keywords
copper pillar
copper
layer
solder
pillar
Prior art date
Application number
TW097144626A
Other languages
Chinese (zh)
Other versions
TWI407538B (en
Inventor
Ying-Chih Chan
Hung-Sheng Hu
Original Assignee
Phoenix Prec Technology Corp
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Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW097144626A priority Critical patent/TWI407538B/en
Publication of TW201021182A publication Critical patent/TW201021182A/en
Application granted granted Critical
Publication of TWI407538B publication Critical patent/TWI407538B/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a package substrate and a method of fabricating the same, comprising a substrate body having a plurality of electrical connecting pads formed on at least one surface thereof; a solder mask layer formed on the substrate body and with a plurality of openings for correspondingly exposing each of the connecting pads therefrom; a first copper pillar formed on each connecting pad and protruding from the solder mask layer; and a second copper pillar disposed on the first copper pillar and having a diameter smaller than that of the first copper pillar, such that a larger pitch can be provided between the semiconductor chip and the substrate by the first and second copper pillars, thereby facilitating formation of a fine-pitched package structure and avoiding the drawbacks of uneven stresses caused by poor underfilling in the subsequent packaging process.

Description

201021182 .凡、贫明說明： .【發明所屬之技術領域】 . 本發明係關於一種封裝基板及其製法，尤指一種封裝 *基板之電性接觸墊上形成有凸柱之結構及製法。 ,【先前技術】 * 在現行覆晶式（FliP chip)半導體封裝技術中，係於 半導體晶片上設有電極焊墊，並於該電極焊墊上形成焊錫 凸塊，且在一具有電性接觸墊之封裝基板上形成位於電性 ❿接觸墊表面之焊錫凸塊，俾藉由該焊錫凸塊及焊錫凸塊兩 者電性連接，以提供該半導體晶片與該封裝基板電性連 接。 相較於傳統的打線接合（Wire B〇nd)技術，覆晶技術 之特徵在於半導體晶片與封裝基板間的電性連接係透過 知錫凸塊而非般之金線，而该種覆晶技術之優點在於其 可提尚封裝密度以降低封裝元件尺寸；同時，該種覆晶技 術不需使用長度較長之金線，以降低阻抗，故可提高電性 參連接的性能。 由於越來越多的產品設計趨向小型化，因此，覆晶技 術亦朝向高I/〇數、細間距之趨勢發展。然而，隨著防焊 層開孔與導電凸塊間距（bump pitch)的縮小，利用印刷 錫的方式製作導電凸塊係為!業界解決低良率及高治具成 本的手段之一。 »月參閱第1A至1F圖，係說明一種習知的封裝基板製 作電性連接結構之製法的示意圖；如帛1A圖所示，係提 Π1005 5 201021182 2暴板本體…該基板本體iQ之至少—表面形成有複 ，數电性接觸墊1 〇 1 ’於該旯 Μ悝# ^基板本體10的表面上形成有一 ，防焊層11，該防焊層11中犯+ >、fc & θ 1中形成有複數開孔110以對應露 -出各該電性接觸墊101 ;如 弟1β圖所不’於該防焊層11 ,上设有一網版13，且咭 ^ ^ ^ 玄凋版13具有與該電性接觸墊101 !相對應之網孔1 30，以嚟山# & , 乂路出该電性接觸墊J 01，為避免受 限於對位精度，故該網版 105之網孔130均大於該防焊層 之開孔11G ’如第1C圖所示，該網孔130中塗佈有焊 ⑩錫材料以形成輝接材料14;如第1D圖所示，移除該網版 以露出該焊接材料14;如第1£圖所示，該焊接材料 Η經避焊以形成烊料球14，；如第ιρ圖所示，提供一半 導體晶4 15,且該半導體晶片15具有複數電極塾⑽， 於該電極墊150上形成有焊料凸塊，令該焊料凸塊對應連 接該焊料球14,，並經迴焊製程以形成焊球14,，，令該半 導體晶片15電性連接至該基板本體1G，並於該防焊層u 與半導體日B片15之間填人底充材料16，以加強該基板本 ®體10與半導體晶片15之間的結合強度。 准隨著防焊層11開孔11 0的孔徑及間距縮小，利 用印刷形成焊料球14’的方式，受限於網版13製作的難 度增加、成本上升與良率下降等問題，利用植球方式製作 凸塊已成為覆晶基板朝向!細線路間距的解決方案之一，但 該防焊層1 1必須維持一定厚度，而該防焊層1 1開孔1 1 〇 ，孔位及間距縮小’深寬比（aspect i0)越大，則烊 料球14之直徑就愈小，使該焊料球14,廻焊後，無法有 6 111005 201021182 •效填滿開孔U 0，且該基板本體1 〇與半導體晶片丨5之間 .的離板間距（Standoff)更小，導致該底充材料16分散 *不均勻，而不易填滿該基板本體1〇與半導體晶片15之間 ' 的離板間距，衍生品質可靠度等問題。 … 請參閱第2A至2H圖，係說明另一種習知的封裝基板 !製作電性連接結構之製法的示意圖。 又 如第2A圖所示，係於一表面形成有複數電性接觸墊 201之基板本體20，於該基板本體2〇上形成防焊層21， 籲且於該防焊層21中形成複數開孔21〇以對應露出各哕 性接觸墊201。 如第2B圖所示，接著於該電性接觸墊2〇1、防焊層 21表面及開孔210之孔壁上形成第一導電層22a。 如第2C圖所示，於該第一導電層22a上形成第一阻 層23a，且該第一阻層23a中形成有複數個第—開口 230a該第一開口 230a之尺寸係大於該防焊層21之開孔 210尺寸，以對應露出形成於該電性接觸墊2〇1上之— 導電層22a。 如第2D圖所示，接著藉由該第一導電層22a作為電 鍍（Electroplating)製程之電流傳導路徑，以於該電性 觸墊201上形成第一銅柱24a。 如第2E圖所示，丨移除該第一阻層2如及其所覆罢之 第-導電層22a’以露出該第一銅柱…，且該第一；柱 24a係突出於該防焊層21之表面。 如第2F圖所示’於該第—銅柱他上形成表面處理 111005 7 201021182 .層 25。 ，， 如第2G圖所示，提供一具有複數電極墊26〇之半導 .體晶片26,各該電極墊260上具有焊料凸塊261，且該些 '第一銅柱24a對應各該焊料凸塊261。 ， 如第2H圖所示，廻焊該焊料凸塊261及表面處理層 t 25以形★成焊料262 ’令該半導體晶片26藉由該焊料 包覆該第-銅柱24a，以電性連接至該基板本體2〇，且於 該基板本體2G與半導體晶片26之間注人底充材料2?， ❿以加強該基板本體20與半導體晶片26之間的結合強度。 惟，上述習知之製法，由於隨著半導體晶片託之電 極塾260尺寸及間距變小，該電極整26〇上的焊料凸塊 261用置亦變少’该基板本體2〇之電性接觸墊卻受 限於製程能力，難以有效地縮小尺寸及間距，致使電性接 觸墊2(U與電㈣26〇之尺寸相差愈大該電極塾· 上的焊料凸塊261與電性接觸塾2()1上的第一銅柱％ 的尺寸亦相差更大，當迴焊該焊料凸& 26i &第一銅柱 ®24a上之表面處理層25時’常因焊料量不無法有效 包覆第一銅柱地’而產生應力不均句，甚至造成連接界 面的破裂等問題。 因此，繁於上述之問題，如何克服 習知技術不易提供 基板本體與半導體晶片之間較大的離板間距，且容易造成 連接界面的應力分佈不均句等問題，實已成目前錢 的課題。 【發明内容】 Π1005 8 201021182 =述習知技術之缺點，本發明之主要目的係提供 •一種封裝基板及其製法，能提供高離板間距， .的基板電性連接結構，並避免後續封裝之底充材料填充不 -確實之缺失。 叮具兄小 …為達上述目的及其他目的’本發明揭露 係包括：基板本體，於至少—表面具有複數電性^ 有防焊層，於該防焊層中設有複數 Γ 電性= 電性接觸塾;第-銅柱，係設於 參該=接觸墊上，且該第—鋼柱凸出於該防痒層之表面； 以及第一銅柱’係設於該第一銅柱上，且該第二鋼柱之直 控小於該第一銅柱之直控。 依上述之封裝基板’復包括表面處理層，係設於該第 -銅柱凸出於該防焊層之表面及該第二銅柱之表面上。 =依上述之封裝基板’復包括焊料凸塊，係設於該第 .一銅柱上。 依上述之結構’復包括料球，係設於該第二銅柱上。 又依上述之結構’復包括第一導電層，係設於該電性 接觸墊與第一銅柱之間、以及該防焊層之開孔與第一銅柱 之間’復包括第二導電層，係設於該第一鋼柱及第二鋼柱 之間。 本廢明復提供-種封裝基板之製法，係包括：提 少一表面形成有複數電性接觸塾之基板本體，且於該基板 本體上形成防焊層’於該防焊層中形成有複數開孔，以對 應外露出各該電性接觸墊；於該電性接觸墊與防焊層上電 111005 9 201021182 •鐘形成第二銅柱，·以及於該第—銅柱上電㈣成第二銅 -柱，其中，該第二銅柱之直徑係小於該第一銅柱之直徑。 '依上述之封裝基板製法，其中，該第_銅柱之裳:， 係包括··於該電性接觸墊、防焊層及其開孔之孔壁上形成 …第-導電層;於該第一導電層上形成第一阻層，該第一阻 ，層形成有複數第一開口’以對應露出各該電性接觸墊上之 第-導電層，且該第-開口之尺寸大於該防谭層之開孔之 尺寸，於S亥第一開口中雷妒布#哲 ., 甲包鍍形成第一銅柱；以及移除該第 一阻層及其所覆蓋之第-導電層，以露出該第一銅柱。 :上二之製法’其中，該第二銅柱之製法，係包括： 2該第-銅柱及防焊層上形成第二導電層;於該第二導電 成第二阻層’該第二阻層形成有複數第二開口，以 柱'第一銅柱’且該第二開口之尺寸小於該第一銅 令第=於及1第二開口中電鐘形成第二銅柱；以及移除 及第二銅柱。 弟冑電層’以露出該第一銅柱 成表：復包括於該第一銅柱及第二銅柱之表面形 焊料凸塊，或於該第二鋼柱上植球形成=球 焊層2明之封裝基板及其Μ，主㈣在基板本體之防 ~層及電性接觸墊上電铲彡 < 防 出於該防炫爲本 該第一銅柱’該第一碑柱突 枝，其中，該銅柱上電鑛形成第二銅 藉由第-銅柱盥第糸小於該第一銅柱之直控， ”第一銅柱可保持該半導體晶片與基板本 ]]]〇05 10 201021182 -體之間的較大離板間距，以利於該底充材料填滿該半導體 .晶片與基板本體之間，而避免該底充材料分散不均句，導 .致品質可靠度等問題，且當隨著晶片之電極墊尺寸及間距 -變小，該第二銅柱亦可易於隨之縮小，使該第二銅柱之尺 «寸較接近電極墊之尺寸，因此以焊料作連接時，其應力分 ，佈會較為均勻，所以可靠度較高；再者，小直徑的第二= 柱經廻焊而為焊料所包覆時，即使各該電性接觸墊的間距 縮小，焊料與焊料之間仍具有足夠距離，可免於焊料之間 ❹的橋接現象，故可利於形成細間距的基板電性連接社 【實施方式】 ，口 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭 ^ 瞭解本發明之其他優點及功效。 ^易地 請參閱帛3Α13Κ®，係為詳細説明本發明之電 觸墊上形成第-銅柱及第二銅柱之實施例之剖面示意圖。 =3Α圖所示，係於一表面形成有複數電性接觸塾 之基板本體2〇,於該基板本體2〇上形成有防 且於該防焊層21中形成複數開孔210以對應外露出 ::3Β圖所示’接著於該電性接觸塾2〇ι: :二開孔21。之孔壁上形成第一導電層2 _ “層瓜主要作為後述電錢金屬材料所需之電流傳導 111005 11 201021182 路徑，其可由金屬或沉積數層金屬層所構成，如選自銅、 .錫、鎳、鉻、鈦等單層金屬、或銅-鉻或錫-鉛等多層金屬 * 結構，或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導 - 電高分子材料^ 、如第3C圖所示’於該第一導電層22a上形成第一阻 》層23a，該第一阻層23a係為乾膜之光阻層 (photoresist) ’其係利用例如貼合等方式形成於該第一 導電層22a表面’再藉由曝光、顯影等方式加以圖案化， ⑬使該第一阻層23a中形成有複數個第一開口 230a ’且各 該第一開口 230a大於該防焊層21之開孔210，以對應露 出形成於該電性接觸墊2〇1上之第一導電層22a。 如第3D圖所示’藉由該第一導電層22a作為電鑛 (electroplating)製程之電流傳導路徑，以於該電性接觸 墊201上電鍍形成第一銅柱24a。 如第3E圖所示，移除該第一阻層23a及其所覆蓋之 第一導電層22a，以露出該第一銅柱24a ,且該第一銅柱 ® 24a係突出於該防焊層21之表面；纟中，移除該第一阻 層23a及第一導電層22a之製程係屬習知者，故於此不再 為文贅述。 如第3F圖所示，於該防焊層2卜第一銅柱2乜上形 成第二導電層22b。 如第3G圖所示，於該第二導電層挪上形成第二阻 層2北一’且於該第二阻層23b中形成有對應該第-銅柱24a 之第一開口 230b，以露出該第二導電層挪之部份表面， 111005 12 201021182 •且該第f開口 23〇b小於該第一銅柱24a之外徑。 • 如苐3H圖所示，進行雷供制 # • 22b作為電鍵時之電流傳導:鑛…錯由該第二導電層 〇〇 U專導路控’以在該第二阻層23b之 '弟一開口 230b中的第—41=]知 24b〇 弟⑽主24a上電鍍形成第二銅柱 - 如第31圖所示，移除兮坌-成001_ 除該第一阻層23b及其所覆蓋之 θ 2b’以露出該第-銅柱24a及第二鋼柱24b， 二弟一銅柱24b之直#係小於該第—銅柱…之直徑； 豳其中’移除該第二阻層2% « 罾羽，^ 層及第一導電層22b之製程係屬 I知者，故於此不再為文贅述。 如第3 J圖所不，於該第一銅才主24a外露之表面與第 二銅柱24b之表面進行表面處理，以於該第一銅柱. 與第二銅柱24b上形成表面處理層25，亦可以電鑛方式 於第二銅柱24b上形成焊料凸塊（圖式中未表示），或以 植球方^於第二銅柱24b上形成焊料球（圖式中未表示）。 如第3K圖所示’提供一具有複數電極墊26〇之半導 ❹體“ 26,各該電極墊26〇上具有焊料凸塊，且該些第 一銅柱24a對應各該焊料凸塊，並進行料製程，以形成 知料262’令这半導體晶片26藉由包覆在該第二銅柱挪 上的焊料262以電性連接至該基板本體2〇，並於該基板 本體20與半導體晶片26之間注入底充材料27 ,以加強 該基板本體20與半導體晶片26之間的結合強度。由於該 电性接觸墊201上形成有該第一銅柱2切及第二銅柱 24b，且該第二銅柱24b直徑小於該第一銅柱直徑， 111005 13 201021182 •因此該焊料262能結合在該第一銅柱2乜及第二銅柱24b .上以電性連接至該半導體晶片26。 •、本發明復提供一種封裝基板，係包括：基板本體2〇， -於至少一表面具有複數電性接觸墊201，且該基板本體2〇 -上形成有防焊層2卜於該防焊層21中形成有複數開孔 • 210’以對應外露出各該電性接觸墊2〇ι ;第一銅柱Mg , 係形成於該電性接觸墊2〇1上，且該第一銅柱2牦並凸出 2該防焊層21之表面；以及第二銅柱_，係設於該第 ®銅柱24a上’且該第二銅柱24b之直徑小於該第一銅柱 24a之直徑。 依上述之結構，復包括有第一導電層22a，係形成於 該電性接觸塾201與第一銅柱24a之間、以及防焊層21 之開孔210與第一銅才主…之間；復包括有第二導電層 2訃，係形成於該第一鋼柱24a及第二銅柱2扑之間。 依上所述，復包括表面處理層25，係形成於該第一 銅柱24a凸心該防焊層21之表面及第二銅柱地之表 本發明之封裝基板及其製法’主要係在基板本體之防 卜層及電性接觸墊上電鍍形成該第一銅柱，該第一銅柱突 =於该防¥層表面，又於該第—銅柱上電㈣成第二銅 ―，其中，該第二銅柱之直徑係小於該第一銅柱之直徑， =該第-銅柱與第二銅柱以保持該半導體晶片與基板 之間有杈大之離板間距，以利於該底充材料填滿誃 〃 扳本肋之間，而避免該底充材料分散不均 】】】005 14 201021182 •勻’影響品質可靠度等問題，且當隨著半導體晶片之電極 ，整尺寸及間距變+，該帛二銅柱亦可易於隨之縮小，令該 -第二銅柱之尺寸較接近電極塾之尺寸，因此以焊料作連接 -時，其應力分佈會較為均勻，以提高可靠度；再者，小直 ，徑的第二銅柱經廻焊而為焊料所包覆時，即使各該電性接 f觸墊的間距縮小，焊料與焊料之間仍具有足夠距離，可免 於焊料之間的橋接現象，故可利於形成細間距的基板電性 連接結構。 ❹ 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與改 變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 【圖式簡單説明】 第1A至1F圖係為習知封裝基板之製法之剖面示意 圖； ~ ❹ 第2人至211圖係為習知封裝基板之另一製法之剖面示 意圖；以及 第3A至3K圖係為本發明封裝基板之製法之剖面示 圖。 ’、 【主要元件符號說明】. 10 ' 20 基板本體 101 ' 201 電性接觸墊 11、21 防焊層 111005 ]5 201021182 11 υ ' 乙 1 υ 開孔 13 網版 130 網孔 14 焊接材料 145 焊料球 14，， f 焊球 15、26 半導體晶片 150 、 260 電極塾 16、27 底充材料 22a 第一導電層 22b 第二導電層 23a 第一阻層 230a 第一開口 23b 第二阻層 230b 第二開口 24a 第一銅柱 φ 24b 第二銅柱 25 表面處理層 261 焊料凸塊 262 焊料201021182. Where the invention is poor: [Technical field to which the invention pertains] The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a structure and a method for forming a bump on an electrical contact pad of a package. [Prior Art] * In the current FliP chip semiconductor packaging technology, an electrode pad is disposed on a semiconductor wafer, and solder bumps are formed on the electrode pad, and an electrical contact pad is formed on the electrode pad. A solder bump on the surface of the electrical contact pad is formed on the package substrate, and is electrically connected to the solder bump and the solder bump to provide electrical connection between the semiconductor wafer and the package substrate. Compared with the conventional wire bonding technology, the flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is transmitted through the know tin bump instead of the gold wire, and the flip chip technology The advantage is that it can increase the package density to reduce the size of the package component; at the same time, the flip chip technology does not need to use a long length of gold wire to reduce the impedance, so the performance of the electrical connection can be improved. As more and more product designs tend to be miniaturized, flip chip technology is also moving toward a trend of high I/turns and fine pitch. However, as the solder mask opening and the bump pitch are reduced, the conductive bumps are made by printing tin. One of the means for the industry to solve the problem of low yield and high fixture cost. Referring to FIGS. 1A to 1F, there is shown a schematic diagram of a conventional method for fabricating an electrical connection structure of a package substrate; as shown in FIG. 1A, the slab 1005 5 201021182 2 slab body ... at least the substrate body iQ - the surface is formed with a plurality of electrical contact pads 1 〇 1 ' on the surface of the substrate body 10 is formed with a solder resist layer 11 in which the + >, fc & A plurality of openings 110 are formed in θ 1 to correspondingly expose the electrical contact pads 101; and the solder mask layer 11 is not provided on the solder mask layer 11, and a screen 13 is provided thereon, and 咭 ^ ^ ^ The plate 13 has a mesh 1 30 corresponding to the electrical contact pad 101!, and the electrical contact pad J 01 is taken out by the 嚟山# & 乂路, in order to avoid being limited by the alignment accuracy, the screen The mesh 130 of the 105 is larger than the opening 11G of the solder resist layer. As shown in FIG. 1C, the mesh 130 is coated with a solder material of 10 tin to form the solder material 14; as shown in FIG. 1D, Except the screen to expose the solder material 14; as shown in FIG. 1, the solder material is soldered to form a ball 14; as shown in FIG. The semiconductor wafer 15 has a plurality of electrodes 10 (10), solder bumps are formed on the electrode pads 150, the solder bumps are connected to the solder balls 14 , and are soldered to form solder balls 14 . The semiconductor wafer 15 is electrically connected to the substrate body 1G, and a bottom filling material 16 is filled between the solder resist layer u and the semiconductor day B sheet 15 to strengthen the substrate body 10 and the semiconductor wafer. The strength of the bond between 15. As the aperture and the pitch of the opening 11 of the solder resist layer 11 are reduced, the manner in which the solder ball 14' is formed by printing is limited by the difficulty in the production of the screen 13, the increase in cost, and the decrease in yield. The method of making bumps has become one of the solutions for the flip-chip substrate orientation; fine line pitch, but the solder resist layer 11 must maintain a certain thickness, and the solder resist layer 1 1 has a hole 1 1 〇, and the hole position and pitch are reduced. The larger the aspect ratio (aspect i0), the smaller the diameter of the ball 14 is, so that the solder ball 14 cannot be filled with the opening U 0 after the soldering, and the substrate body is filled. The distance between the 〇 and the semiconductor wafer 丨 5 is smaller, resulting in the dispersion of the underfill material * unevenness, and it is not easy to fill the gap between the substrate body 1 and the semiconductor wafer 15 Spacing, derived quality reliability and other issues. Referring to Figures 2A to 2H, another conventional package substrate will be described. A schematic diagram of a method of fabricating an electrical connection structure. Further, as shown in FIG. 2A, a substrate body 20 having a plurality of electrical contact pads 201 is formed on a surface thereof, and a solder resist layer 21 is formed on the substrate body 2, and a plurality of openings are formed in the solder resist layer 21. The holes 21 are correspondingly exposed to expose the respective contact pads 201. As shown in Fig. 2B, a first conductive layer 22a is formed on the surface of the electrical contact pad 2, the surface of the solder resist 21, and the opening 210. As shown in FIG. 2C, a first resist layer 23a is formed on the first conductive layer 22a, and a plurality of first openings 230a are formed in the first resist layer 23a. The first opening 230a is larger in size than the solder resist. The opening 210 of the layer 21 is sized to correspondingly expose the conductive layer 22a formed on the electrical contact pad 2〇1. As shown in Fig. 2D, the first conductive layer 22a is then used as a current conducting path for an electroplating process to form a first copper pillar 24a on the electrical contact pad 201. As shown in FIG. 2E, the first resistive layer 2 is removed, such as the first conductive layer 22a' thereof, to expose the first copper pillars, and the first pillars 24a protrude from the The surface of the solder layer 21. As shown in Fig. 2F, a surface treatment is formed on the first copper pillar 111005 7 201021182 . As shown in FIG. 2G, a semiconductor wafer 26 having a plurality of electrode pads 26A is provided, each of the electrode pads 260 having a solder bump 261 thereon, and the first copper pillars 24a correspond to the solder Bump 261. As shown in FIG. 2H, the solder bump 261 and the surface treatment layer t 25 are soldered to form the solder 262' so that the semiconductor wafer 26 is electrically covered by the solder to cover the first copper pillar 24a. To the substrate body 2, and between the substrate body 2G and the semiconductor wafer 26, a bottom filling material 2 is implanted to strengthen the bonding strength between the substrate body 20 and the semiconductor wafer 26. However, in the above conventional method, since the size and pitch of the electrode 260 of the semiconductor wafer holder become smaller, the solder bumps 261 on the electrode are less disposed. The electrical contact pads of the substrate body 2 However, it is limited by the process capability, and it is difficult to effectively reduce the size and spacing, so that the difference between the size of the electrical contact pad 2 (U and the electric (four) 26 愈 is larger. The solder bump 261 on the electrode 塾 · and the electrical contact 塾 2 () The size of the first copper pillar % on 1 is also larger, and when the solder bump & 26i & the first copper pillar® 24a is treated on the surface treatment layer 25, it is often impossible to effectively coat the surface due to the amount of solder. A copper column is used to cause stress unevenness, and even causes cracks in the connection interface. Therefore, it is difficult to provide a large off-board spacing between the substrate body and the semiconductor wafer by overcoming the above problems. And it is easy to cause problems such as uneven distribution of stress distribution at the interface, which has become a problem of current money. [Disclosed Summary] Π1005 8 201021182 = Disadvantages of the prior art, the main object of the present invention is to provide a package substrate and System of law , can provide high off-board spacing, the electrical connection structure of the substrate, and avoid the lack of filling of the underfill material of the subsequent package. The device is small... for the above purposes and other purposes, the present invention includes: The substrate body has a plurality of electrical solder mask layers on at least the surface, and the plurality of solder resists are electrically connected to the solder resist layer; the first copper pillar is disposed on the contact pad and The first steel column protrudes from the surface of the anti-itch layer; and the first copper column is disposed on the first copper column, and the direct control of the second steel column is smaller than the direct control of the first copper column. The package substrate according to the above includes a surface treatment layer, and the first copper pillar protrudes from the surface of the solder resist layer and the surface of the second copper pillar. The block is disposed on the first copper pillar. According to the above structure, the composite ball is disposed on the second copper pillar. The first conductive layer is further included in the structure Between the electrical contact pad and the first copper post, and between the opening of the solder resist layer and the first copper post The second conductive layer is disposed between the first steel column and the second steel column. The method for manufacturing the package substrate comprises: reducing a substrate on which a plurality of electrical contacts are formed on the surface Forming a solder resist layer on the substrate body; forming a plurality of openings in the solder resist layer to correspondingly expose the respective electrical contact pads; and electrically energizing the electrical contact pads and the solder resist layer 111005 9 201021182 • The clock forms a second copper pillar, and the second copper pillar is electrically charged (4) to the second copper pillar, wherein the diameter of the second copper pillar is smaller than the diameter of the first copper pillar. The package substrate manufacturing method, wherein the first copper pillar comprises: forming a first conductive layer on the electrical contact pad, the solder resist layer and the hole wall of the opening; and the first conductive layer Forming a first resist layer, the first resist, the layer is formed with a plurality of first openings 'to correspondingly expose the first conductive layer on each of the electrical contact pads, and the size of the first opening is larger than the opening of the anti-tank layer Dimensions, in the first opening of S Hai, Thunder cloth #哲., A bag plating to form the first copper column; and remove the first a resistive layer and a first conductive layer covered thereon to expose the first copper pillar. The method of manufacturing the second copper column includes: 2 forming a second conductive layer on the first copper pillar and the solder resist layer; and forming a second resistive layer on the second conductive layer The resist layer is formed with a plurality of second openings to the column 'first copper pillars' and the second opening has a size smaller than the first copper ring = the first electric gate of the second opening forms a second copper pillar; and the second copper pillar is removed And a second copper column. The electric layer of the first layer is formed by exposing the first copper pillar: a surface-shaped solder bump included in the first copper pillar and the second copper pillar, or a ball on the second steel pillar to form a ball solder layer 2, the package substrate and its crucible, the main (four) on the substrate body of the anti-layer and the electrical contact pad on the electric shovel 防 防 防 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The second pillar of the copper pillar is formed by the first copper pillar, and the first copper pillar can hold the semiconductor wafer and the substrate.]] 〇05 10 201021182 a large off-board spacing between the bodies, so that the underfill material fills the semiconductor. The wafer and the substrate body are prevented from dispersing the unevenness of the underfill material, leading to quality reliability, and the like. When the size and spacing of the electrode pads of the wafer become smaller, the second copper pillar can be easily reduced, so that the size of the second copper pillar is closer to the size of the electrode pad, so when solder is used as a connection, The stress is divided, the cloth will be more uniform, so the reliability is higher; in addition, the second diameter of the small column = the solder is soldered When coating, even if the pitch of each of the electrical contact pads is reduced, the solder and the solder have a sufficient distance between the solder to avoid the bridging phenomenon between the solders, so that the substrate can be formed with a fine pitch. The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can understand the other advantages and effects of the present invention as disclosed in the specification. ^See 帛3Α13Κ® for easy access. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A cross-sectional view of an embodiment in which a first copper pillar and a second copper pillar are formed on an electrical contact pad of the present invention is shown in Fig. 3, which is a substrate body 2 having a plurality of electrical contact pads formed on a surface thereof. A plurality of openings 210 are formed in the substrate body 2 to form a plurality of openings 210 in the solder resist layer 21 for corresponding external exposure: '3' is followed by the electrical contact 塾2〇ι: : two openings 21. Forming the first conductive layer 2 on the wall of the hole _ "The layer of melon is mainly used as a current conduction 111005 11 201021182 path required for the later-described money metal material, which may be composed of metal or a plurality of layers of metal, such as copper, tin, Nickel, chromium, a single-layer metal, or a multilayer metal* structure such as copper-chromium or tin-lead, or a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer can be used, as shown in Fig. 3C A first resist layer 23a is formed on the first conductive layer 22a, and the first resist layer 23a is a photoresist layer of a dry film. The photoresist layer is formed on the surface of the first conductive layer 22a by, for example, bonding. 'The patterning is performed by exposure, development, etc., 13 forming a plurality of first openings 230a' in the first resist layer 23a and each of the first openings 230a is larger than the opening 210 of the solder resist layer 21, Correspondingly, the first conductive layer 22a formed on the electrical contact pad 2〇1 is exposed. As shown in Fig. 3D, the first conductive layer 22a is used as a current conducting path of an electroplating process to form a first copper pillar 24a on the electrical contact pad 201. As shown in FIG. 3E, the first resistive layer 23a and the first conductive layer 22a covered by the first resistive layer 23a are removed to expose the first copper pillar 24a, and the first copper pillar® 24a protrudes from the solder resist layer. The process of removing the first resist layer 23a and the first conductive layer 22a is a well-known one, and therefore will not be described herein. As shown in Fig. 3F, a second conductive layer 22b is formed on the first copper pillar 2'' of the solder resist layer 2. As shown in FIG. 3G, a second resist layer 2 is formed on the second conductive layer, and a first opening 230b corresponding to the first copper pillar 24a is formed in the second resist layer 23b to expose The surface of the second conductive layer is moved, 111005 12 201021182 • and the fth opening 23〇b is smaller than the outer diameter of the first copper pillar 24a. • As shown in Fig. 3H, carry out the lightning supply # • 22b as the current conduction when the key: mine... wrong by the second conductive layer 〇〇U-guided road control 'in the second resistive layer 23b' The first copper pillar is electroplated on the main 24a of the opening 230b - as shown in Fig. 31, the first resist layer 23b is covered and covered by the first resist layer 23b. θ 2b' to expose the first copper pillar 24a and the second steel pillar 24b, the straight line of the second copper pillar 24b is smaller than the diameter of the first copper pillar; 豳 wherein the second resistive layer 2 is removed The processes of the % « 罾 feather, ^ layer and the first conductive layer 22b are known to those skilled in the art, and therefore will not be described herein. As shown in FIG. 3J, the exposed surface of the first copper main 24a and the surface of the second copper post 24b are surface-treated to form a surface treatment layer on the first copper pillar and the second copper pillar 24b. 25, it is also possible to form a solder bump on the second copper pillar 24b by electric ore method (not shown in the drawing), or to form a solder ball on the second copper pillar 24b by a ball-forming method (not shown in the drawing). As shown in FIG. 3K, 'a semi-conducting body having a plurality of electrode pads 26' is provided, each of which has solder bumps thereon, and the first copper posts 24a correspond to the solder bumps, And performing a material process to form a material 262' such that the semiconductor wafer 26 is electrically connected to the substrate body 2 by solder 262 coated on the second copper pillar, and the substrate body 20 and the semiconductor are A bottom filling material 27 is injected between the wafers 26 to strengthen the bonding strength between the substrate body 20 and the semiconductor wafer 26. Since the first copper pillar 2 is cut and the second copper pillar 24b is formed on the electrical contact pad 201, The diameter of the second copper pillar 24b is smaller than the diameter of the first copper pillar, 111005 13 201021182. Therefore, the solder 262 can be coupled to the first copper pillar 2 and the second copper pillar 24b to be electrically connected to the semiconductor wafer. 26. The present invention further provides a package substrate, comprising: a substrate body 2, having a plurality of electrical contact pads 201 on at least one surface, and a solder resist layer 2 is formed on the substrate body 2 A plurality of openings are formed in the solder resist layer 21 to correspond to the outer exposed portions. An electrical contact pad 2〇; a first copper pillar Mg is formed on the electrical contact pad 2〇1, and the first copper pillar 2 is protruded and protrudes from the surface of the solder resist layer 21; The copper pillar _ is disposed on the first copper pillar 24a' and the diameter of the second copper pillar 24b is smaller than the diameter of the first copper pillar 24a. According to the above structure, the first conductive layer 22a is included and formed. Between the electrical contact 塾 201 and the first copper pillar 24a, and between the opening 210 of the solder resist layer 21 and the first copper conductor, the second conductive layer 2 讣 is formed in the first Between the steel column 24a and the second copper column 2, as described above, the surface treatment layer 25 is formed on the surface of the first copper pillar 24a and the surface of the solder resist layer 21 and the second copper pillar The package substrate of the present invention and the method for manufacturing the same are mainly formed by electroplating the anti-bowl layer and the electrical contact pad of the substrate body to form the first copper pillar, and the first copper pillar protrusion is on the surface of the anti-layer layer, and The first copper pillar is powered (four) into a second copper, wherein the diameter of the second copper pillar is smaller than the diameter of the first copper pillar, and the first copper pillar and the second copper pillar are used to maintain the semiconductor There is a large separation distance between the wafer and the substrate, so that the underfill material fills the rib between the ribs and avoids uneven dispersion of the underfill material.]] 005 14 201021182 • The uniform quality is reliable Degree and the like, and when the size and pitch of the electrode of the semiconductor wafer are changed, the second copper pillar can be easily reduced, so that the size of the second copper pillar is closer to the size of the electrode crucible, so When the solder is connected, the stress distribution will be more uniform to improve the reliability; in addition, the second copper pillar of small straight and diameter is covered by solder after soldering, even if each of the electrical contacts f The pitch is reduced, and there is still a sufficient distance between the solder and the solder to avoid the bridging phenomenon between the solders, so that the fine pitch substrate electrical connection structure can be formed. The above embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and alterations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1F are schematic cross-sectional views showing a method of manufacturing a conventional package substrate; ~ ❹ 2nd to 211 are schematic cross-sectional views showing another method of manufacturing a package substrate; and 3A to 3K The figure is a cross-sectional view showing the method of manufacturing the package substrate of the present invention. ', [Description of main component symbols]. 10 ' 20 Substrate body 101 ' 201 Electrical contact pads 11, 21 Solder mask 111005 ] 5 201021182 11 υ ' B 1 υ Opening 13 Screen 130 Mesh 14 Soldering material 145 Solder Ball 14, f welding ball 15, 26 semiconductor wafer 150, 260 electrode 塾 16, 27 underfill material 22a first conductive layer 22b second conductive layer 23a first resistive layer 230a first opening 23b second resistive layer 230b second Opening 24a first copper pillar φ 24b second copper pillar 25 surface treatment layer 261 solder bump 262 solder

Claims (1)

201021182 .十、甲請專利範圍： .1 · 一種封裝基板，係包括： . 基板本體，係於至少-表面具有複數電性接觸 •塾，且該基板本體上設有防焊層，於該防焊層中設有 • 硬數開孔，以對應外露出各該電性接觸墊； ‘， 帛—銅柱，似於該電性接觸塾上，且該第一銅 柱凸出於該防焊層之表面；以及 第二銅柱H於該第—銅柱上，且該第二銅柱 ❸ 之直禮小於該第一銅柱之直徑。 2.如申請專利範圍第1項之封^基板，復包括第一導電 層，係設於該電性接觸塾與第一銅柱之間、以及該防 焊層之開孔與第一銅柱之間。 3. 如申請專利範圍第1項之封奘其 私^ 又對裝基板，復包括表面處理 主^ 路出之表面及該苐二銅柱之 表面上。 4.201021182 . X. A patent scope: .1 · A package substrate comprising: a substrate body having at least a surface having a plurality of electrical contacts, and a substrate having a solder resist layer thereon The soldering layer is provided with a hard opening to correspondingly expose the electrical contact pads; ', 帛-copper pillar, like the electrical contact ,, and the first copper pillar protrudes from the solder resist a surface of the layer; and a second copper pillar H on the first copper pillar, and the second copper pillar is less than the diameter of the first copper pillar. 2. The sealing substrate of claim 1, wherein the first conductive layer is disposed between the electrical contact and the first copper pillar, and the opening of the solder resist layer and the first copper pillar between. 3. If the application of the first paragraph of the patent scope is sealed, the surface of the main surface and the surface of the second copper column are included. 4. 如申請專利範圍第1項之封裝基板 塊，係設於該第二銅柱上。 復包括焊料凸 5. 6.The package substrate block of claim 1 is disposed on the second copper post. Complex solder bumps 5. 6. 2請專利範圍第1項之封裝基板，復包括焊料球， 係设於該第二銅柱上。 如申請專利範圍第1項之封奘 „ 裝基板，设包括第二導電 層，係設於該第一銅柱，第二鋼柱之間。 一種封裝基板之製法，係包括·· 本體 提供至少-表面形成有複數電性接觸墊之基板 ’且於該基板本體上形成防焊層，於該防焊層中 1Π005 】7 201021182 • 形成有複數開孔，以對應外露出各該電性接觸墊； • 於該電性接觸墊與該防焊層上電鍍形成第一銅 " 柱，以及 _ 於該第一銅柱上電鍍形成第二銅柱，且該第二銅 • 柱之直經係小於該第一銅柱之直徑。 8. 如申請專利範圍第7項之封裝基板製法，其中，該第 一銅柱之製法，係包括： ❹ 於該電性接觸墊、防焊層及其開孔之孔壁上形成 弟一導電層； 第導電層上形成第一阻層，該第一阻層形 成有複數第-開口，以對應露出各該電性接觸塾上之 第—導電層’且該第-開口大於該防焊層之開孔； 於該第—開口中電鍍形成第一銅柱；以及 移除該第一阻層及其所覆蓋之第一導電層，以露 出該第一銅柱。 9. ❹ 如申請專利範圍第7項之封裝基板製法，其中，該第 二銅柱之製法，係包括： /、 / 於該第一銅柱及該防焊層上形成第二導電層； 於該第二導電層上形成第二阻層該第二阻層形 成有複數第二開口，以對應露出該第—鋼柱，且該第 一開口小於該第一銅彳主之直徑； 於該第二開口中電鍍形成第二鋼柱；以及 移除該第二阻層及其所覆蓋之 出該第-銅柱及第二銅柱。 ^ 1Π005 18 201021182 .ΐϋ.如申請專利範圍第 ,帛-鋼柱外露之“Λ 復包括於該 , 理層。 面及第二銅柱之表面形成表面處 -1 1 .如申S青專利範圍第7 Τ5 第_如"予 封裝基板製法，復包括於咳 ， 弟一銅柱上電鍍形成焊料凸塊。 、該 v 12·如申請專利範圍第7項之封裝基板製法，復包 第二鋼柱上植球形成焊料球。 柃該 】】1005 192 The package substrate of the first aspect of the patent scope includes a solder ball and is disposed on the second copper pillar. For example, the packaged substrate of the first application of the patent scope includes a second conductive layer disposed between the first copper pillar and the second steel pillar. A method for manufacturing the package substrate includes: Forming a substrate with a plurality of electrical contact pads on the surface and forming a solder resist layer on the substrate body. In the solder resist layer, 1Π005 77 201021182 • a plurality of openings are formed to correspondingly expose the respective electrical contact pads • plating a first copper " column on the electrical contact pad and the solder resist layer, and plating a second copper pillar on the first copper pillar, and the straight line of the second copper pillar The method of manufacturing the package substrate according to the seventh aspect of the invention, wherein the method for manufacturing the first copper pillar comprises: 于 the electrical contact pad, the solder resist layer and the opening thereof Forming a conductive layer on the wall of the hole; forming a first resist layer on the conductive layer, the first resist layer is formed with a plurality of first openings to correspondingly expose the first conductive layer on each of the electrical contacts The first opening is larger than the opening of the solder resist layer; Forming a first copper pillar in the first opening; and removing the first resistive layer and the first conductive layer covered thereby to expose the first copper pillar. 9. ❹ as claimed in claim 7 The method for manufacturing a package substrate, wherein the second copper pillar is formed by: /, forming a second conductive layer on the first copper pillar and the solder resist layer; forming a second resist layer on the second conductive layer The second resistive layer is formed with a plurality of second openings to correspondingly expose the first steel pillar, and the first opening is smaller than a diameter of the first copper crucible; and a second steel pillar is electroplated in the second opening; Removing the second resist layer and covering the first copper pillar and the second copper pillar. ^ 1Π005 18 201021182 .ΐϋ. As claimed in the patent scope, the "帛-steel column exposed" is included in the The management layer. The surface of the surface and the surface of the second copper pillar is formed at a surface -1 1. As for the application of the method of encapsulating the substrate, the method of encapsulating the substrate is formed by electroplating to form a solder bump on the copper pillar. The v 12 · The method of manufacturing a package substrate according to claim 7 of the patent application, the ball is implanted on the second steel column to form a solder ball.柃 】】1005 19
TW097144626A 2008-11-19 2008-11-19 Package substrate and fabrication method thereof TWI407538B (en)

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TWI487444B (en) * 2013-05-07 2015-06-01 Unimicron Technology Corp Carrier substrate and manufacturing method thereof
US9491871B2 (en) 2013-05-07 2016-11-08 Unimicron Technology Corp. Carrier substrate
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CN115938949A (en) * 2021-08-12 2023-04-07 礼鼎半导体科技(深圳)有限公司 Carrier plate containing solder balls and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
US20060012055A1 (en) * 2004-07-15 2006-01-19 Foong Chee S Semiconductor package including rivet for bonding of lead posts
TWI343084B (en) * 2006-12-28 2011-06-01 Siliconware Precision Industries Co Ltd Semiconductor device having conductive bumps and fabrication methodthereof

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Publication number Priority date Publication date Assignee Title
TWI487444B (en) * 2013-05-07 2015-06-01 Unimicron Technology Corp Carrier substrate and manufacturing method thereof
US9247654B2 (en) 2013-05-07 2016-01-26 Unimicron Technology Corp. Carrier substrate and manufacturing method thereof
US9491871B2 (en) 2013-05-07 2016-11-08 Unimicron Technology Corp. Carrier substrate
CN104168706A (en) * 2013-05-17 2014-11-26 欣兴电子股份有限公司 Bearing substrate and manufacturing method thereof
CN104168706B (en) * 2013-05-17 2017-05-24 欣兴电子股份有限公司 Bearing substrate and manufacturing method thereof
EP3123506A4 (en) * 2014-03-28 2017-12-20 Intel Corporation Method and process for emib chip interconnections
CN115938949A (en) * 2021-08-12 2023-04-07 礼鼎半导体科技(深圳)有限公司 Carrier plate containing solder balls and manufacturing method thereof

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