M375291 五、新型說明： 【新型所屬之技術領域】 本創作係關於一種覆晶封裝結構，尤指一種適用於細 間距發展之覆晶封裝結構。 '” 5 【先前技術】 隨著半導體製程能力不斷向上提升，半導體晶片的功 能日益強大且趨於複雜化，同時半導體晶片的資料傳輸量 也不斷的增加，因此半導體晶片所須的接腳（pin)數也隨之 10 增加。 由於晶片技術不斷朝高頻、高接腳數發展，傳統打線 封裝（Wire Bonding)技術已經無法滿足電性上的要求，相較 於傳統打線封裝的技術，覆晶封裝是以晶片作用面藉由錫 金σ凸塊與基板電性連接之先進技術。另外，〖/ο接觸腳可以 15分佈在整個晶片的表面，大幅度提高晶片訊號輸入/輸出端 點的數量，同時縮短電流訊號傳輸的路徑，並且降低雜訊 的干擾、提高散熱能力以及縮減封裝體積。因此，覆晶封 裝技術已漸漸成為市場的主流技術。 S知的覆as封裝結構請參考圖1Α。此基板的表面具 20有複數個電性接觸墊11且具有一防焊層12，此防谭層12具 有複數開孔，以顯露出電性接觸塾1 1 ^同時，於此電性接 觸墊11表面利用電鍍或印刷的方式形成預焊錫 14(pre-S〇lder)。另一方面，晶月20之作用面上具有複數電 極塾21 ’且在電極墊21上具有一鈍化層22(Passivati〇n M375291M375291 V. New Description: [New Technology Field] This creation is about a flip chip package structure, especially a flip chip package structure suitable for fine pitch development. '" 5 [Prior Art] As the semiconductor process capability continues to increase, the functions of semiconductor wafers become increasingly powerful and complex, and the amount of data transferred from semiconductor wafers continues to increase, so the pins required for semiconductor wafers (pins) The number has also increased by 10. As the wafer technology continues to develop toward high frequency and high pin count, the traditional wire bonding technology (Wire Bonding) technology can not meet the electrical requirements, compared to the traditional wire bonding technology, flip chip The package is an advanced technology in which the surface of the wafer is electrically connected to the substrate by the gilt σ bumps. In addition, the contact pins 15 can be distributed over the surface of the wafer to greatly increase the number of input/output terminals of the chip signal. At the same time, the path of current signal transmission is shortened, noise interference is reduced, heat dissipation capability is reduced, and package size is reduced. Therefore, flip chip packaging technology has gradually become the mainstream technology in the market. Please refer to Figure 1 for the covered package structure of S. The surface of the substrate has a plurality of electrical contact pads 11 and has a solder resist layer 12 having a plurality of openings. In order to expose the electrical contact 塾1 1 ^, a pre-solder 14 is formed on the surface of the electrical contact pad 11 by electroplating or printing. On the other hand, the active surface of the crystal moon 20 has The plurality of electrodes 塾21' and having a passivation layer 22 on the electrode pad 21 (Passivati〇n M375291
layer),此鈍化層22具有複數開孔’以顯露出電極墊21。於 電極墊21表面經由電鍍形成預焊錫，再經迴谭而形成一球 形焊錫凸塊25(bump)»然後再藉由此焊錫凸塊25與預焊錫 14將晶片20與基板1〇進行電性連接。 5 晶片20與基板10連接後（圖未示），必須於晶片20與基 板10之間的空隙中填充底部膠材，並經由固化後達到固定 晶片及提升封裝結構可靠度之目的（圖未示）。 此種結構及製程雖可達到電性連接的目的，但是當欲 往細間距發展時便有其限制》請參閱圖1A，因為現今半導 10體高功能之需求’其晶片表面佈設之電極墊密度甚高接 置於其上之焊锡凸塊25球徑甚小’而對應接置之基板電性 接觸墊亦甚密’因為焊錫凸塊25球徑甚小，故晶片2〇及基 板10接置後間隙高度甚低，導致在填充底部膠材時，膠材 無法元全填滿於基板與晶片之間的空隙而產生孔洞，這將 15會導致產品發生爆板等嚴重的可靠度問題，同時，接點強 度亦因接點尺寸縮小而減小，導致接點強度不足以承受晶 片與基板間因熱膨脹係數（CTE)差異造成的應力（stress)， 而使該預焊錫14與電性接觸墊11之間產生接點（joint)脫 離、斷裂的現象。The passivation layer 22 has a plurality of openings ' to expose the electrode pads 21. A pre-solder is formed on the surface of the electrode pad 21 by electroplating, and then a ball-shaped solder bump 25 is formed by returning to the tantalum. Then, the wafer 20 and the substrate 1 are electrically connected by the solder bump 25 and the pre-solder 14 connection. 5 After the wafer 20 is connected to the substrate 10 (not shown), the bottom adhesive material must be filled in the gap between the wafer 20 and the substrate 10, and the cured wafer can be used to fix the wafer and improve the reliability of the package structure (not shown). ). Although such a structure and process can achieve the purpose of electrical connection, there is a limit when it is desired to develop to a fine pitch. Please refer to FIG. 1A, because the current semi-conductor 10 body high-function requirement 'the electrode pad on the surface of the wafer The solder bumps 25 on which the density is very high are very small, and the corresponding substrate electrical contact pads are also very dense. Because the solder bumps 25 have a small ball diameter, the wafers 2 and 10 are connected. The height of the gap after the placement is very low, so that when the bottom glue is filled, the glue cannot fill the gap between the substrate and the wafer to create a hole, which will cause serious reliability problems such as explosion of the product. At the same time, the contact strength is also reduced due to the shrinkage of the contact size, resulting in insufficient contact strength to withstand the stress caused by the difference in thermal expansion coefficient (CTE) between the wafer and the substrate, and the pre-solder 14 is in electrical contact with each other. A phenomenon occurs in which the joints are separated and broken between the mats 11.
2〇 有鑑於上述缺點’另發展有一種覆晶封裝結構，圖1B 所示。晶片20之電極墊21表面經由電鍍形成銅柱26,再藉 由此銅柱26與預焊錫14將晶片20與基板10進行電性連接。 雖然銅柱26可增加晶片20與基板10接置後間隙之高度，改 善底膠之充填品質，解決上述细間距應用之問題，但銅柱 5 M375291 26卻有應力較大之缺點’由於只有基㈣端具有預焊锡 14’而“㈣無料錫，#_26與預焊錫刚由回焊 而進行自我對位接合時，晶片端或基板端的界面常因益法 有效釋放應力而形成缺陷，導致可靠度不佳。 【新型内容】 本創作之-目的係在提供―種覆晶封裝結構俾能達 成細間距之半導體晶片封裝。 10 15 本創作之另-目的係在提供一種覆晶封裝結構，俾能 改善膠材之充填品質，減緩覆晶封装結構之熱應力，進而 提升覆晶封裝結構之可靠度。 為達成上述目的，本創作提供一種覆晶封裝結構包 =一基板本體，係具有—表面，該表面具有 觸塾；-半導體晶片，係具有一作用面，該作用面具有： 塊複Γ 一焊料塊，係設於電性接觸墊上;複數 第一㈣塊，係設於電極墊上；以及複數金屬柱係嗖於 第一焊料塊與第二焊料塊之間’以電性連接第—焊料塊盘 第=Γ’其中’該些金屬柱各別具有—第―柱體部^ 出：’凸出部之截面積係大於第一柱體部之截面積， i第;;柱體部之—端係與凸出部連接。在此，凸出部可與 第一卜料塊連接，而第—柱體部之另—端可與該些第 料，連接，據此，該凸出部可增加金屬柱與第_焊料塊之 固著力。 20 M375291 據此，本創作所提供之覆晶封裝結構中，該些金屬柱 可增加晶片與基板接置後間隙之高度，避免膠材無法完全 填滿於基板與晶片之間的空隙而產生孔洞，進而改善產品 發生爆板等嚴重的可靠度問題’故本創作所提供之覆晶封 5裝結構適用於細間距之半導體晶片封裝。此外，金屬柱兩 端分別接置有第一焊料塊及第二焊料塊，故可藉由自我對 位而緩和回焊時之應力，增加產品之可靠度。 於本創作之覆晶封裝結構中，該些金屬柱各別復可具 有一第二柱體部，其中，凸出部之截面積係大於第二柱體 10部之截面積，且第二柱體部之一端係與凸出部連接，而凸 出部係位於第一柱體部與第二柱體部之間。在此該凸出 部及第二柱體部可與該些第一焊料塊連接，而第一柱體部 之另一端可與該些第二焊料塊連接。 於本創作之覆晶封裝結構中，該凸出部可為一盤狀凸 15出部，其中，盤狀凸出部之形狀並無特殊限制，其舉例可 為圓形、橢圓形、矩形及多邊形之其中一者。 本創作之覆晶封裝結構復可包括一金屬墊層，其係設 於電極墊與第二焊料塊之間。 本創作之覆晶封裝結構復可包括一底膠、一封膠或一 20異方性導電膜於基板本體與半導體晶片之間。 於本創作之覆晶封裝結構中，基板本體之該表面上可 設有一保護層，其具有複數第一開孔，以顯露該些電性接 觸墊。 7 M375291 於本創作之覆晶封裝結構中，半導體晶片之作用面上 可設有一鈍化層（Passivation layer)，其具有複數第二 孔’以顯露該些電極塾。 —$ 於本創作之覆晶封裝結構中，該些金屬柱之材料可 5 銅、鎳、金或其組合。 一 本創作之覆晶封裝結構中，第一焊料塊及第二焊料塊 之材料可分別為錫、錫/鉛、錫/銅、錫/銀、錫/鋅、 锡/銦、錫/銀/銅或其組合。 綜上所述，於本創作中，由於半導體晶片與基板之間 10配置有金屬柱，因而可增加半導體晶片與基板之間的間隙 咼度，從而確保後續填充膠材製程能順利完成，故本創作 所it供之覆封裝結構適用於細間距之半導體晶片封穿。 另一方面，本創作藉由金屬柱而提高半導體晶片與基板之 間的間隙高度，於填充膠材時可得到較大的膠材厚度因 I5此，當半導體晶片的工作溫度上升時，可藉由膠材緩和半 導體晶片與基板之間所產生的熱應力。此外，由於金屬柱 兩端分別接置有第一焊料塊及第二焊料塊，故可藉由自我 對位而緩和回焊時之應力，增加產品之可靠度。 20【實施方式】 以下係藉由特定的具體實施例說明本創作之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本創作之其他優點與功效。本創作亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 M3752912〇 In view of the above disadvantages, another flip chip package structure has been developed, as shown in Fig. 1B. The surface of the electrode pad 21 of the wafer 20 is formed by electroplating a copper pillar 26, and the copper pillar 26 and the pre-solder 14 are used to electrically connect the wafer 20 to the substrate 10. Although the copper pillar 26 can increase the height of the gap between the wafer 20 and the substrate 10, improve the filling quality of the primer, and solve the above problem of fine pitch application, the copper pillar 5 M375291 26 has the disadvantage of large stress. (4) The terminal has pre-solder 14' and "(4) no material tin, #_26 and the pre-solder is just self-aligned by reflow, the interface of the wafer end or the substrate end often forms a defect due to the effective release of stress, resulting in reliability. [New content] The purpose of this creation is to provide a fine-pitch semiconductor chip package with a kind of flip-chip package structure. 10 15 Another purpose of this creation is to provide a flip chip package structure. Improve the filling quality of the rubber material, slow down the thermal stress of the flip chip package structure, and thereby improve the reliability of the flip chip package structure. To achieve the above object, the present invention provides a flip chip package structure = a substrate body having a surface. The surface has a contact; the semiconductor wafer has an active surface, the active surface having: a block of solder, a solder block, disposed on the electrical contact pad; a plurality of first (four) , the system is disposed on the electrode pad; and the plurality of metal pillars are between the first solder bump and the second solder bumps to electrically connect the first solder bumps to the first solder bumps, where the metal pillars have respective ―Cylinder part ^ Out: 'The cross-sectional area of the bulge is greater than the cross-sectional area of the first cylinder, i;; the end of the cylinder is connected to the bulge. Here, the bulge can be The first block is connected, and the other end of the first cylinder portion is connected with the first material, whereby the protruding portion can increase the fixing force of the metal post and the first solder block. 20 M375291 In the flip chip package structure provided by the present invention, the metal pillars can increase the height of the gap between the wafer and the substrate, and prevent the glue material from completely filling the gap between the substrate and the wafer to generate holes, thereby improving the product. A serious reliability problem such as a blasting plate occurs. Therefore, the flip-chip package 5 structure provided by the present invention is suitable for a fine pitch semiconductor chip package. Further, a first solder bump and a second solder bump are respectively disposed at two ends of the metal pillar. Therefore, the stress during reflow can be alleviated by self-alignment. The reliability of the product. In the flip chip package structure of the present invention, the metal columns respectively have a second column portion, wherein the cross-sectional area of the protrusion is larger than the cross-sectional area of the second column 10 And one end of the second cylindrical portion is connected to the protruding portion, and the protruding portion is located between the first cylindrical portion and the second cylindrical portion. Here, the protruding portion and the second cylindrical portion can be combined with The first solder bumps are connected, and the other end of the first pillar portion is connectable with the second solder bumps. In the flip chip package structure of the present invention, the protruding portion can be a disk-shaped convex 15 The shape of the disk-shaped protrusion is not particularly limited, and may be, for example, one of a circle, an ellipse, a rectangle, and a polygon. The flip chip package structure of the present invention may include a metal pad layer. The flip chip package structure of the present invention may comprise a primer, a glue or a 20-island conductive film between the substrate body and the semiconductor wafer. In the flip chip package structure of the present invention, the surface of the substrate body may be provided with a protective layer having a plurality of first openings to expose the electrical contact pads. 7 M375291 In the flip chip package structure of the present invention, a passivation layer may be disposed on the active surface of the semiconductor wafer, and has a plurality of second holes ' to expose the electrode pads. —$ In the flip chip package structure of the present invention, the materials of the metal pillars may be 5 copper, nickel, gold or a combination thereof. In a fabricated flip chip package structure, the materials of the first solder bump and the second solder bump may be tin, tin/lead, tin/copper, tin/silver, tin/zinc, tin/indium, tin/silver/ Copper or a combination thereof. In summary, in the present invention, since the metal pillar is disposed between the semiconductor wafer and the substrate 10, the gap between the semiconductor wafer and the substrate can be increased, thereby ensuring that the subsequent filling process can be successfully completed. The encapsulation structure provided by the foundry is suitable for fine-grained semiconductor wafer encapsulation. On the other hand, the present invention improves the gap height between the semiconductor wafer and the substrate by the metal pillar, and can obtain a larger thickness of the rubber material when filling the rubber material. When the operating temperature of the semiconductor wafer rises, the borrowing can be borrowed. The thermal stress generated between the semiconductor wafer and the substrate is moderated by the rubber. In addition, since the first solder bump and the second solder bump are respectively disposed at both ends of the metal post, the stress during reflow can be relaxed by self-alignment, thereby increasing the reliability of the product. [Embodiment] The following describes the implementation of the present invention by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention by the contents disclosed in the present specification. The creation may also be carried out or applied by other different embodiments, and the details in this specification are also M375291
可基於不同觀點與應用’在不悖離本創作之精神下進行各 種修飾與變更。 本創作之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本創作有關之元件，其所顯示之元件非為 5實際實施時之態樣’其實際實施時之元件數目、形狀等比 例為一選擇性之設計’且其元件佈局型態可能更複雜。 實施例1 > 請參考圖2A至2E’係為本實施例覆晶封裝結構之製作 10 流程剖視圖》 首先，如圖2A所示，提供一基板本體30，係具有一表 面30a，該表面30a具有複數電性接觸墊31，且該表面3〇a 上設有一保護層32，該保護層32可為感光性或非感光性之 介電材或綠漆〇該保護層32具有複數第一開孔32〇,以顯露 IS該些電性接觸塾31。接著，如圖2B所示，藉由電鑛或化學 鍍’形成預焊錫41’於該些電性接觸墊31上。 之後，如圏2C所示，藉由電鍍形成複數金屬柱42於預 焊錫41’上，其中，金屬柱42各別具有一第一柱體部421及 一凸出部422’凸出部422之截面積係大於第一柱艘部421 2〇之截面積，且第一柱體部421之一端係與凸出部422連接。 金屬柱42之材料可為銅、鎳、金或其組合，於本實施例中， 金屬柱42為銅柱。此外，於本實施例中，該凸出部422呈圓 盤狀。 接著，如圖2D所示，提供一半導體晶片5〇，其具有一 25作用面50a ’該作用面5〇a具有複數電極墊51，且電極墊51 9 M375291 上設有複數第二焊料塊43，據此，如圖2e所示，經由回焊 製程（reflow) ’利用覆晶方式，使半導體晶片5〇之第二焊料 塊43與基板本體30上之金屬柱42電性導接，其中，預焊錫 於回焊製程後形成半球狀之第一焊料塊41，且金屬柱42之 5凸出部422係與第一焊料塊41連接，以增加金屬柱42與第一 焊料塊41之固著力，而第一柱體部421之另一端係與第二焊 料塊43連接。在此，半導體晶片5〇之作用面5〇a上更設有一 鈍化層（Passivation layer)52，其具有複數第二開孔52〇，以 顯露該些電極墊51。最後，如圖2E所示’填充一底膠6〇於 該基板本體30與該半導體晶片5〇之間，以完成覆晶封裝。 或者，如圖2D’所示，金屬柱42亦可形成於半導體晶 片50之第二焊料塊43處，其中，第二焊料塊43係與金屬柱 42之第一柱體部421連接；接著，再利用覆晶方式，透過回 焊製程（reflow)’使接置於半導體晶片5〇上之金屬柱42與基 15板本體3〇上之預焊錫41，電性導接，以形成如圖2E所示之覆 晶封裝結構，其中，預焊錫於回焊製程後形成半球狀之第 一焊料塊41，而金屬柱42之凸出部422係與第一焊料塊“ 連接。 據此，如圖2E所示，本實施例提供一種覆晶封裝結 2〇構，其包括：一基板本體30,係具有一表面3〇a，該表面 具有複數電性接觸墊31，其中，該表面上3〇a更設有一保護 層32，其具有複數第一開孔32〇，以顯露該些電性接觸墊 31，一半導體晶片50，係具有一作用面5〇a，該作用面5〇& 具有複數電極墊51，其中，作用面5〇a上更設有—鈍化層 M375291Various modifications and changes can be made based on different perspectives and applications without departing from the spirit of the present invention. The drawings in the embodiments of the present invention are simplified schematic diagrams. However, these drawings only show the components related to this creation, and the components displayed are not the actual implementation of the aspect of 'the actual number of components, the shape and the like are a selective design' and its components The layout type can be more complicated. Embodiment 1 > Referring to Figures 2A to 2E', a cross-sectional view showing the fabrication of a flip chip package structure of the present embodiment. First, as shown in Fig. 2A, a substrate body 30 having a surface 30a having a surface 30a is provided. A plurality of electrical contact pads 31 are provided, and the surface 3〇a is provided with a protective layer 32, which may be a photosensitive or non-photosensitive dielectric material or a green paint. The protective layer 32 has a plurality of first openings. The holes 32 are exposed to expose the electrical contacts 31 of the IS. Next, as shown in Fig. 2B, a pre-solder 41' is formed on the electrical contact pads 31 by electroplating or chemical plating. Then, as shown in FIG. 2C, a plurality of metal pillars 42 are formed on the pre-solder 41' by electroplating, wherein the metal pillars 42 each have a first pillar portion 421 and a protruding portion 422' projecting portion 422. The cross-sectional area is larger than the cross-sectional area of the first column portion 421 2 , and one end of the first column portion 421 is connected to the protruding portion 422 . The material of the metal post 42 may be copper, nickel, gold or a combination thereof. In the present embodiment, the metal post 42 is a copper post. Further, in the present embodiment, the projection 422 has a disk shape. Next, as shown in FIG. 2D, a semiconductor wafer 5 is provided having a 25-acting surface 50a' having a plurality of electrode pads 51, and the electrode pads 51 9 M375291 are provided with a plurality of second solder bumps 43. According to this, as shown in FIG. 2e, the second solder bumps 43 of the semiconductor wafer 5 are electrically connected to the metal pillars 42 on the substrate body 30 by a reflow process. The pre-solder forms a hemispherical first solder bump 41 after the reflow process, and the 5 protrusions 422 of the metal post 42 are connected to the first solder bump 41 to increase the adhesion of the metal pillar 42 and the first solder bump 41. The other end of the first pillar portion 421 is connected to the second solder bump 43. Here, the active surface 5〇a of the semiconductor wafer 5 is further provided with a passivation layer 52 having a plurality of second openings 52A to expose the electrode pads 51. Finally, as shown in Fig. 2E, a primer 6 is filled between the substrate body 30 and the semiconductor wafer 5A to complete the flip chip package. Alternatively, as shown in FIG. 2D', the metal post 42 may be formed at the second solder bump 43 of the semiconductor wafer 50, wherein the second solder bump 43 is connected to the first pillar portion 421 of the metal post 42; Then, by using the flip chip method, the metal pillars 42 placed on the semiconductor wafer 5 and the pre-solder 41 on the base plate 3 of the base 15 are electrically connected through a reflow process to form a conductive pattern as shown in FIG. 2E. The flip chip package structure is characterized in that the pre-solder forms a hemispherical first solder bump 41 after the reflow process, and the protrusion 422 of the metal post 42 is "connected to the first solder bump. As shown in FIG. 2E, the present embodiment provides a flip-chip package structure comprising: a substrate body 30 having a surface 3〇a having a plurality of electrical contact pads 31, wherein the surface is 3〇 A further comprising a protective layer 32 having a plurality of first openings 32 〇 to expose the electrical contact pads 31, a semiconductor wafer 50 having an active surface 5〇a, the active surface 5〇& a plurality of electrode pads 51, wherein the active surface 5〇a is further provided with a passivation layer M375291
52，其具有複數第二開孔52〇，以顯露該些電極塾$ 1 ;複數 第一焊料塊41，係設於電性接觸墊31上：複數第二焊料塊 43，係設於電極墊51上；複數金屬柱42，係設於第一焊料 塊41與第二焊料塊43之間，以電性連接第一焊料塊與第 5二焊料塊43，其中，該些金屬柱42各別具有一第一柱體部 421及一凸出部422’凸出部422之載面積係大於第一柱體部 421之截面積，且第一柱體部421之一端係與凸出部422連 接，而凸出部422係與第一焊料41塊連接，第一柱體部421 ♦之另-端則與第二焊料塊43連接；以及一底膠6〇 ,係於基 10板本體50與半導體晶片3〇之間。 本實施例中’由於在半導體晶片5G與基板本想3〇之間 配置有金屬柱42,因而可增加半導體晶片5〇與基板本體％ 之間的間隙高度，從而確保後續填充膠材製程能順利完成。 另一方面，本實施例藉由金屬柱42而提高半導體晶片 15 50與基板本趙3〇之間的間隙高度，利於填充底祕，且當 半導體晶片50的工作溫度上升時，可藉由底膠6〇緩和半導 _ 趙晶片50與基板本趙30之間所產生的熱應力，此外，由於 .金屬柱42兩端分別接置有第一焊料塊41及第二焊料塊43 , 故可藉由自我對位而緩和回焊時之應力，增加產品之可靠 20度。 實施例2 請參考圖3,係為本創作另一較佳實施例之覆晶封裝結 構剖視@。本實施例之覆晶封裝結構大致與實施例丨相同， 准不同處在於，本實施例之覆晶封裝結構復包括一金屬墊 層53，係設於電極墊51與第二焊料塊43之間。 實施例3 10 吻麥芩闲nT、匈不剧作另一較佳實施例之覆晶封裝與 構d視圖》本實施例之覆晶封裝結構大致與實施例2相同 惟不同處在於，金屬柱42復具有一第二柱體部423，其中 凸出部422之截面積係大於第二柱體部423之截面積，且筹 二柱體部423之-端係與凸出部422連接，而凸出部422係仿 於第-柱體部421與第二柱體部423之間，據此，凸出部心 及第二柱體部423係與第__焊料塊41連接，而第一柱體苟 421之另一端係與第二焊料塊们連接。 上述實施例僅係為了方便說明而舉例而已，本 主張之權利範圍自應以申請專利範圍所述 於上述實施例。 重m 15 【圓式簡單說明】 圖1A係習知之覆晶封裝結構剖視圖。 20 請係習知之另—覆晶封裝結構剖視圖。 圖2A至2E係本創作—較佳實施例之覆晶 流程剖視圖。 Μ 封装結構之製作 圖3係本創作一較佳實施例之覆晶 圖4係本創作一較佳實施例之覆晶 封裝結構剖視圖 封裝結構剖視圖 【主要元件符號說明】 12 M375291 10 基板 12 防焊層 20 晶片 22, 52 純化層 26 銅柱 30a 表面 320 第一開孔 42 金屬柱 422 凸出部 43 第二焊料塊 50a 作用面 53 金屬塾層 11,31 電性接觸墊 14, 4Γ 預焊錫 21, 51 電極墊 25 焊錫凸塊 30 基板本體 32 保護層 41 第一焊料塊 421 第一柱體部 423 第二柱體部 50 半導體晶片 520 第二開孔 60 底膠 1352, which has a plurality of second openings 52A to expose the electrodes 塾$1; a plurality of first solder bumps 41 are disposed on the electrical contact pads 31: a plurality of second solder bumps 43 are disposed on the electrode pads The plurality of metal pillars 42 are disposed between the first solder bumps 41 and the second solder bumps 43 to electrically connect the first solder bumps and the fifth solder bumps 43. The metal pillars 42 are respectively different. The carrying area of the first cylindrical portion 421 and the protruding portion 422 ′ is greater than the cross-sectional area of the first cylindrical portion 421 , and one end of the first cylindrical portion 421 is connected to the protruding portion 422 . The protrusion 422 is connected to the first solder 41, the other end of the first pillar portion 421 ♦ is connected to the second solder bump 43; and a primer 6 is attached to the base 10 body 50 and The semiconductor wafer is between 3 turns. In the present embodiment, since the metal pillar 42 is disposed between the semiconductor wafer 5G and the substrate, the gap height between the semiconductor wafer 5 and the substrate body% can be increased, thereby ensuring a smooth process of the subsequent filling material. carry out. On the other hand, in this embodiment, the height of the gap between the semiconductor wafer 150 and the substrate is increased by the metal pillars 42 to facilitate the filling of the bottom secret, and when the operating temperature of the semiconductor wafer 50 rises, the bottom can be The rubber 6 〇 半 半 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ By self-alignment, the stress during reflow is alleviated, and the reliability of the product is increased by 20 degrees. Embodiment 2 Please refer to FIG. 3, which is a cross-sectional view of a flip chip package structure according to another preferred embodiment of the present invention. The flip chip package structure of the present embodiment is substantially the same as the embodiment, except that the flip chip package structure of the embodiment includes a metal pad layer 53 between the electrode pad 51 and the second solder bump 43. . Embodiment 3 10 The wafer flip-chip package and the structure of the flip-chip package of the present embodiment are substantially the same as those of the embodiment 2 except that the metal pillar is 42 has a second column portion 423, wherein the cross-sectional area of the protrusion 422 is larger than the cross-sectional area of the second column portion 423, and the end of the two-column portion 423 is connected to the protrusion 422. The protruding portion 422 is formed between the first cylindrical portion 421 and the second cylindrical portion 423, whereby the protruding portion core and the second cylindrical portion 423 are connected to the first_th solder block 41, and the first The other end of the cylinder 421 is connected to the second solder bumps. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is as described in the above-mentioned embodiments. Weight m 15 [Circular Simple Description] FIG. 1A is a cross-sectional view of a conventional flip chip package structure. 20 Please refer to the other part of the flip-chip package structure. 2A to 2E are cross-sectional views showing the flip chip process of the present invention as a preferred embodiment. 3 is a flip-chip view of a preferred embodiment of the present invention. FIG. 4 is a cross-sectional view of a flip-chip package structure of a preferred embodiment. [Main component symbol description] 12 M375291 10 substrate 12 solder resist Layer 20 wafer 22, 52 purification layer 26 copper pillar 30a surface 320 first opening 42 metal pillar 422 projection 43 second solder bump 50a active surface 53 metal germanium layer 11, 31 electrical contact pad 14, 4 Γ pre-solder 21 , 51 electrode pad 25 solder bump 30 substrate body 32 protective layer 41 first solder bump 421 first pillar portion 423 second pillar portion 50 semiconductor wafer 520 second opening 60 primer 13