TWI397164B - Chip package with connecting extension of tsv - Google Patents

Abstract

Disclosed is a chip package with connecting extension of TSV (Through Silicon Via), primarily comprising a substrate, a chip disposed on the substrate, a plurality of conductive fillers and an encapsulant encapsulating the chip. The substrate has a plurality of through holes vertically corresponding to and connecting to a plurality of TSVs through the chip. The conductive fillers are filled in the TSVs and the through holes and are further extruded from the bottom surface of the substrate to form as external bumps with hole-to-hole connection as a whole. Accordingly, conventionally wire-bonding and ball-placing steps can be skipped in manufacturing the chip package. Furthermore, the chip package has a reduced total height and a smaller dimension.

Description

Chip package structure with 矽 perforation extending

The present invention relates to a semiconductor device, and more particularly to a chip package structure in which a crucible via extends.

Under the miniaturization requirements of electronic products, the chip package structure for protecting semiconductor wafers and providing external circuit connections needs to conform to the trend of thinness and shortness. In the chip package structure, the electrical connection between the wafer and the substrate is generally performed by a wire bonding method, and the chip package structure is a medium for external bonding by using a solder ball. However, the wire has a certain arcing height so that the sealing body of the sealing wire needs to have a thick thickness, and it is difficult to reduce the overall package thickness and package size.

Referring to FIG. 1 , a conventional wafer bonding structure 100 for wire bonding includes a substrate 110 , a wafer 120 , a gel 140 , a plurality of bonding wires 170 , and a plurality of solder balls 180 . The substrate 110 has an upper surface 111, a lower surface 112, a plurality of plated through holes 113, a plurality of internal fingers 114, and a plurality of external pads 115. The inner connecting fingers 114 are formed on the outer surface of the upper surface 111. The outer connecting pads 115 are formed on the lower surface 112. The inner connecting fingers 114 are electrically connected to the through-holes 113. Some external pads 115. The plated through holes 113 are through holes for forming a metal layer on the wall of the hole, and are filled with a filler before the packaging process so as not to protrude from the upper surface 111 and the lower surface 112. In a die bonding step, the wafer 120 is disposed on the upper surface 111 of the substrate 110 and cannot cover the wafers 110. The internal finger 114. Generally, the wafer 120 is adhered to the upper surface 111 of the substrate 110 by adhesion of a die layer 150. In a wire bonding step, the bonding wires 170 are electrically connected to the plurality of pads 121 of the wafer 120 to the internal fingers 114 of the substrate 110 to achieve electrical properties between the wafer 120 and the substrate 110. interconnection. In a molding step, the encapsulant 140 is formed on the upper surface 111 of the substrate 110 and seals the wafer 120 and the bonding wires 170. In a ball implantation step, the solder balls 180 are disposed on the external pads 115 of the substrate 110 by a reflow method to serve as external terminals of the chip package structure 100.

In the above-described conventional chip package structure 100, the wafer 120 and the substrate 110 are electrically connected by the bonding wires 170. However, the bonding wires 170 must have a certain arcing height, so that the sealing body 140 needs to have a considerable thickness to avoid the problem of the exposed bonding wires 170, thereby causing the wafer package structure 100 to have a relatively thick thickness. Since the bonding wires 170 connect the pads 121 to the internal fingers 114, they must have a certain length and spacing to avoid the problem of punching during the molding process. The inscribed fingers 114 are located outside the wafer coverage area of the substrate 110 for the bonding wires 170 to be connected. Therefore, the size of the substrate 110 needs to be larger than the size of the wafer 120 to reserve the inscribed portions. Referring to the formation position of the 114, the size of the substrate 110 cannot be reduced, and thus the package size of the chip package structure 100 is difficult to be reduced. In addition, when the solder balls 180 are externally joined, the ball may be dropped due to the stress, resulting in low reliability of the product. drop.

In addition, an advanced wafer package structure has been proposed in which a wafer having a through silicon via (TSV) is disposed on a substrate, and a via is inserted through the wafer, mainly for use in a three-dimensional stack of wafers. In the bonding interface between the wafer and the substrate, the crucible perforation of the lowest layer wafer is an inner pad bonded to the substrate by soldering. Since the wafer is made of a semiconductor material and the substrate is made of an organic material, the difference in thermal expansion coefficient is caused by the difference in materials. Therefore, the stress concentrates on the bonding interface between the wafer and the substrate, resulting in breakage of the solder joint. In another method of combining a wafer and a substrate, a pin is first disposed on the substrate. When the wafer is placed on the substrate, the pin passes through the through hole of the wafer to achieve electrical contact, when one of the pins is not upright or When there is a phenomenon of bending, there will be a problem that the hole is inaccurate, so the process yield is very low. Moreover, poor electrical contact can cause problems with increased impedance and signal interruption.

In order to solve the above problems, the main object of the present invention is to provide a wafer package structure in which a perforated via extends and extends, and the conductive filler formed by liquid filling can simultaneously replace the conventionally formed wire bonding step in the wire bonding step. The formed solder balls do not have the problem that the solder joints are broken in the bonding interface between the wafer and the substrate, and the low-process yield of the hole misalignment caused by the pin-through holes of the pins passing through the wafer. In addition, the overall height of the chip package structure can be reduced and the package size can be reduced.

The object of the present invention and solving the technical problem thereof is to adopt the following technology The program to achieve. The invention discloses a wafer package structure in which a crucible is connected and extended, and mainly comprises a substrate, a wafer, a plurality of conductive fillers and a gel. The substrate has an upper surface, a lower surface, and a plurality of substrate vias. The wafer is disposed on the upper surface of the substrate, and the wafer has a plurality of turns and the through holes are longitudinally correspondingly communicated with the substrate through holes. The conductive filler is formed in the liquid filling manner in the through holes and the through holes of the substrate, and the conductive filler protrudes from the lower surface of the substrate to form a plurality of holes and the holes are integrally connected. External bumps. The encapsulation system is formed on the upper surface of the substrate to seal the wafer.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing wafer package structure, the conductive fillers may be thermosetting resins containing metal particles.

In the aforementioned wafer package construction, the conductive fillers may be formed by sintering a metal paste.

In the foregoing wafer package construction, the encapsulation system can cover the plurality of conductive portions of the wafer.

In the foregoing chip package structure, the ends of the conductive fillers may be formed into a plurality of bump portions larger than the turns of the turns.

In the foregoing wafer package construction, the liquid filling manner of the conductive fillers may include transfer molding.

In the foregoing chip package structure, a die bond layer may be further formed between the wafer and the substrate, and the substrate is provided with a plurality of A retaining ring on the upper surface surrounds the opening of the substrate through hole in the upper surface to block the adhesive layer from flowing into the substrate through holes.

In the foregoing chip package structure, the substrate may be provided with a plurality of bump sockets on the lower surface, which are surrounding the openings of the substrate through holes in the lower surface, and the external connections of the conductive fillers A bump is coupled to the bump holders.

In the foregoing chip package structure, an anisotropic conductive film may be further formed on the lower surface of the substrate and cover the external bumps.

In the foregoing chip package structure, the anisotropic conductive film may comprise a plurality of conductive particles of equal spherical diameter, wherein at least one of the conductive particles electrically contacts the external bumps to an external printed circuit board, wherein The electrically conductive conductive particles are partially embedded in the corresponding external bumps of the conductive filler.

In the aforementioned wafer package construction, the upper surface of the substrate may have an area close to the surface coverage area of the wafer.

It can be seen from the above technical solution that the chip package structure of the present invention has the following advantages and effects: First, the conductive filler formed by the liquid filling method has a specific connection relationship with the internal components of the package structure and can simultaneously replace Conventional welding wire and solder ball, so the wire bonding step and the ball placement step can be omitted to simplify the process.

Second, the conductive filler is used to penetrate the substrate and the wafer at the same time, and the hole-to-hole is integrally connected with the external bump, so the sealant does not need to remain above the arc height of the wafer, and the peripheral surface of the substrate does not need to be To preset the area of the inner finger, the overall height of the chip package structure can be reduced and the package size can be reduced.

3. The external bump formed by one end of the conductive filler can replace the conventional solder ball for the use of an anisotropic conductive paste during surface bonding (SMT), so that the conductive particles in the anisotropic conductive paste can be partially embedded. Attach the bumps.

Fourth, the material properties of the conductive filler, such as silver paste, are used to produce high fluidity and toughness to prevent rupture of the external bumps or holes.

5. The conductive filler is formed at the end of the surface of the wafer to be larger than the bump portion of the crucible, so that the conductive filler can be prevented from coming loose.

6. Formed by a conductive filler in a mold-sealing manner, the conductive filler can have a uniform and neat shape.

7. By the opening of the bump socket surrounding the substrate through hole on the lower surface of the substrate, the coverage area of the external bump on the lower surface of the substrate can be controlled and the bonding force of the external bump can be improved.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be More complicated.

According to an embodiment of the present invention, a wafer package structure in which a turn-by-hole is extended and extended is illustrated in a cross-sectional view of FIG. The chip package structure 200 mainly includes a substrate 210, a wafer 220, a plurality of conductive fillers 230, and a gel 240. The substrate 210 is illustrated in the schematic diagram of the upper surface of the substrate in FIG. 3 and the lower surface of the substrate in FIG. The substrate 210 has an upper surface 211, a lower surface 212, and a plurality of substrate vias 213. The substrate through holes 213 are formed by the upper surface 211 to the lower surface 212. The substrate through holes 213 may be through holes of the non-electrical connection function, that is, the substrate through holes 213 may be provided with an electroless metal layer. In this embodiment, the substrate through holes 213 can be formed by electric drilling or mechanical perforation. The substrate through holes 213 may be arranged in an array, in a peripheral arrangement, or in a single/multiple center line. Preferably, the upper surface 211 of the substrate 210 can have an area close to the surface coverage area of the wafer 220 to achieve a wafer size package without the need to reserve an internal finger around the upper surface of the conventional substrate.

As shown in FIG. 2, the wafer 220 is disposed on the upper surface 211 of the substrate 210. The wafer 220 has a plurality of turns 221, and the through holes 221 are longitudinally corresponding to the substrate through holes 213. Connected. The turns 221 are through the wafer 220. The turns 221 may have a metal layer or a pad extending through the die 220 to serve as an internal terminal of the die 220. And using the conductive filler 230 as the piercings connecting the wafers 220 The transmission path of the electrical signal of the hole 221 . Referring to FIG. 2 again, the wafer 220 is disposed on the substrate 210 such that the plurality of through holes 221 are aligned with the substrate through holes 213 to achieve longitudinal corresponding communication. The formation of the turns 221 can utilize existing helium perforation fabrication techniques such as TSV (Through Silicon Via) wafer bonding technology developed by IBM Corporation.

In this embodiment, the chip package structure 200 may further include a die bonding layer 250 for bonding the wafer 220 and the substrate 210. Referring to FIG. 2, the die layer 250 is formed between the wafer 220 and the substrate 210. Preferably, the substrate 210 is provided with a plurality of retaining rings 214 (shown in FIG. 3) located on the upper surface 211, which surround the openings of the substrate through holes 213 at the upper surface 211. The barrier layer 250 is blocked from flowing into the substrate vias 213. Regarding the method for forming the die layer 250, the die layer 250 may be formed on the substrate 210, and the wafer 220 may be pressed against the die layer 250. In another embodiment, the bonding layer 250 is formed by under filling, that is, the wafer 220 is first disposed on the substrate 210, and then a liquid adhesive is applied to form a filling. The die layer 250 between the wafer 220 and the substrate 210 is such that the wafer 220 is in tight contact with the substrate 210. When the adhesive layer 250 is formed by underfill, the adhesive layer 250 has high fluidity when uncured, so that the retaining rings 214 are pressed against the wafer 220 as a better technical means to effectively block The die layer 250 flows into the substrate vias 213. Preferably, the thickness of the retaining ring 214 is slightly higher than the substrate. The thickness of the solder resist layer on the upper surface 211 is 210 to function to block the die layer 250. In different embodiments, the substrate 210 may not have a solder resist layer to further enhance the blocking effect of the retaining rings 214 and enhance the adhesion between the wafer 220 and the substrate 210. In addition, the material of the retaining ring 214 may be a metal such as copper. The retaining ring 214 is a metal ring protruding from the surface of the substrate 210 and located in a region where the substrate 210 is used to set the wafer 220.

As shown in FIG. 2 , the conductive fillers 230 are formed in the liquid filling manner in the through holes 221 and the substrate through holes 213 . The conductive fillers 230 protrude from the substrate 210 . The surface 212 is formed to form a plurality of holes and the holes are integrally connected to the external bumps 231. As used herein, the term "hole-to-hole integral connection" means that each of the conductive fillers 230 is connected to the corresponding ridges 221 and the substrate vias 213 in a portion where the corresponding external bumps 231 are integrally connected. . In other words, the external bumps 231 are protruding portions of the conductive fillers 230, and the integrally connected root portions can be embedded through the substrate 210 and the wafer 220 to form an external terminal that is not shaken or detached. It is known that solder balls soldered on the surface of the substrate have an unpredictable effect.

Preferably, the conductive filler 230 is a thermosetting resin containing metal particles, such as silver paste, which has high fluidity and toughness to prevent breakage of the external bumps 231 or holes. In another embodiment, the conductive fillers 230 may be formed by sintering a metal paste, such as a copper paste or a solder paste.

The liquid filling manner of the conductive filler 230 may include molding, liquid spotting or hole filling for capillary phenomenon, wherein the sealing method is preferred. Referring to FIG. 5D, the mold 10 can be utilized during the molding process to make the conductive fillers 230 have a uniform and neat shape. The coverage area of the pedestal bumps 231 on the lower surface 212 of the substrate 210 can be larger than the cross-sectional area of the conductive filler 230 in the substrate vias 213 to increase the external connection of the external bumps 231. Contact area.

Since the conductive filler 230 is used to electrically connect the wafer 220 and the substrate 210 and provide external bonding as the wafer package structure 200, the solder wire and the solder ball can be replaced at the same time, and the conventional wire bonding step can be omitted. Steps with the ball planting to simplify the process.

Referring to FIG. 2, the substrate 210 is preferably provided with a plurality of bump holders 215 located on the lower surface 212, which surround the opening of the substrate through holes 213 at the lower surface 212. The plurality of external bumps 231 of the conductive filler 230 are coupled to the bump receptacles 215. The bump receptacles 215 have the external bumps 231 for controlling the conductive fillers 230 on the substrate. The coverage area of the lower surface 212 of the 210 can enhance the bonding force of the external bumps 231. The external bumps 231 can completely cover the bump sockets 215. More specifically, the size of the bump sockets 215 is slightly larger than the size of the retaining rings 214. Referring to FIG. 4, in the embodiment, the shape of the bump holders 215 may be a rectangle having an opening. In addition, the substrate 210 further has a plurality of dummy pads 216. The lower surface 212 of the substrate 210 is disposed on the lower surface 212 to increase the heat dissipation effect, but may not have the function of signal transmission. Specifically, the dummy pads 216 are arranged on opposite sides or the periphery of the substrate 210.

Referring to FIG. 2, the encapsulant 240 is formed on the upper surface 211 of the substrate 210 to seal the wafer 220. The encapsulant 240 provides proper package protection to prevent electrical shorts and dust contamination. Referring to FIG. 2 again, the encapsulant 240 can cover the plurality of ends 232 of the conductive package 230 to form a single-chip package. Preferably, the end portions 232 of the conductive fillers 230 are formed into a plurality of bump portions larger than the plurality of the through holes 221 to prevent the conductive filler 230 from being loosened. Referring to FIG. 2, in the present embodiment, each of the conductive fillers 230 is formed into a cross-sectional shape such as a "work" shape to prevent falling off or displacement.

As can be seen from the above, the electrically conductive filler 230 is used to fill the longitudinally corresponding and communicating the plurality of through holes 221 and the substrate through holes 213, so that the electrical signals of the wafer 220 can be transmitted to the substrate 210. The external bumps 231 can simultaneously replace the solder wires formed in the wire bonding step and the solder balls formed in the ball bonding step, and there is no problem that the solder joints in the bonding interface between the wafer and the substrate are broken. And conventionally, the perforation of the pin through the wafer causes the hole to be misaligned with low process yield. In addition, the conductive filler 230 is used to simultaneously penetrate the substrate 210 and the wafer 220 to form a hole-to-hole connection. The external bumps 231 need not be retained beyond the arcing height of the wafer, and the peripheral surface of the substrate does not need to be preset within the surface of the substrate, so that the overall height of the chip package structure 200 can be reduced. And shrink the package size.

In this embodiment, as shown in FIG. 5H , the chip package structure 200 may further include an anisotropic conductive film 260 formed on the lower surface 212 of the substrate 210 and covering the external bumps 231 . The external bumps 231 protrude from the lower surface 212 of the substrate 210 to facilitate the contact of the anisotropic conductive film 260. The anisotropic conductive film 260 may include a plurality of conductive particles 261 of equal spherical diameter, wherein at least one of the conductive particles 261A electrically contacts the plurality of connection pads 21 of the external bumps 231 to an external printed circuit board 20. The electrically contacting conductive particles 261A are partially embedded in the corresponding external bumps 231 of the conductive fillers 230, so that the electrical contact is more reliable. When the chip package structure 200 is bonded to the external printed circuit board 20, the chip package structure 200 is pressed down to the anisotropic conductive film 260, and the external bumps 231 of the conductive fillers 230 are pressed. The at least one conductive particle 261A is electrically connected to the external printed circuit board 20, and the remaining conductive particles 261 are separated by a non-conductive colloidal region, which does not cause an electrical short circuit. . The external bumps 231 formed by one end of the conductive filler 230 can replace the conventional solder balls for use in surface bonding (SMT), so that the anisotropic conductive paste 260 is used. The conductive particles 261A may be partially embedded in the external bumps 231, and The chip package structure 200 is combined with the external printed circuit board 20, and the method can also be applied to a mobile phone, a memory card, and a memory module.

The present invention further illustrates the method of fabricating the wafer package structure 200 to demonstrate the efficacy of the present invention. Please refer to the cross-sectional views of the components in Figures 5A to 5E.

First, please refer to FIG. 5A to provide the wafer 220. The wafer 220 has a plurality of turns 221, and the formation of the turns 221 can be performed by ion-reactive etching or laser drilling. Next, as shown in FIG. 5B, the substrate 210 is provided to carry the wafer 220. The substrate 210 has a plurality of substrate through holes 213 extending through the upper surface 211 to the lower surface 212. The wafer 220 is adhered to the upper surface 211 of the substrate 210 in such a manner that the turns 221 are aligned with the substrate through holes 213. Referring to FIG. 5B, a die layer 250 is partially coated on the upper surface 211 of the substrate 210 and does not cover the substrate vias 213. In this embodiment, the substrate 210 further includes a plurality of retaining rings 214 and a plurality of bump retainers 215. The retaining rings 214 are located on the upper surface 211 and surround the substrate through holes 213 on the upper surface. The protrusions 211 are located at the lower surface 212 and surround the opening of the substrate through holes 213 at the lower surface 212. Then, as shown in FIG. 5C, the puncturing holes 221 are longitudinally correspondingly connected to the substrate through holes 213, and the blocking layer 214 blocks the viscous layer 250 from flowing into the holes. The substrate via 213 avoids the problem of the adhesive layer 250 overflowing. Preferably, the thickness of the retaining ring 214 is slightly higher than the substrate. The thickness of the solder mask of 210 is used to function as a stopper.

Thereafter, referring to FIG. 5D, the mold 10 is provided and the substrate 210 on which the wafer 220 has been carried is placed on the lower mold 10, wherein the lower surface 212 of the substrate 210 faces the lower mold 10. The lower mold 10 has a positioning groove 11 and a plurality of pockets 12 formed in the positioning groove 11 , wherein the depth of the holes 12 is greater than the depth of the positioning groove 11 . The positioning slot 11 is configured to receive the substrate 210, and the size of the positioning slot 11 is substantially equal to the size of the substrate 210 to avoid displacement of the substrate 210. The recesses 12 are aligned with the substrate through holes 213 , and the recesses 12 are larger than the cross-sectional areas of the substrate through holes 213 for forming the external bumps 231 . Then, as shown in FIG. 5E, the conductive fillers 230 may be filled in the through-holes 221 and the substrate vias 213 by using a molding method, and the recesses 12 of the lower mold 10 are used. The top-down conductive filler 230 is formed to form a plurality of contiguous bumps 231 having a uniform and uniform shape. After the external bumps 231 are formed, the conductive fillers 230 are baked and cured, so that the wafers 220 are electrically connected to the substrate 210. In this embodiment, the conductive filler 230 further has a plurality of ends 232 exposed on the wafer 220 and larger than the turns 221 . Therefore, the conductive bumps 230 can be prevented from being loosened by the external bumps 231 and the end portions 232.

Referring to FIG. 5F, the encapsulant 240 is formed on the upper surface 211 of the substrate 210, and the ends of the wafer 220 and the conductive filler 230 are sealed to form a single-chip package structure. Next, referring to FIG. 5G, an anisotropic conductive film 260 is attached to an external printed circuit board 20 and covers a plurality of connection pads 21 of the external printed circuit board 20. The anisotropic conductive film 260 includes a plurality of conductive particles 261 of equal spherical diameter. Finally, referring to FIG. 5H, the chip package structure 200 is pressed to the external printed circuit board 20, and the at least one conductive particle 261A of the anisotropic conductive film 260 is electrically contacted with the external bumps. 231 to the connection pads 21 to electrically interconnect the chip package structure 200 and the external printed circuit board 20.

Therefore, as can be seen from the above manufacturing method, the conventional wire bonding step and the ball implantation step can be omitted, and the entire wafer packaging process can be completed by performing the marking step and the cutting step after the molding step. The invention can replace the conventional wire-drawing step and the ball-planting step with a step of filling the holes, and there is no problem of conventional punching.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

10‧‧‧ Lower mold

11‧‧‧ positioning slot

12‧‧‧ recess

20‧‧‧External printed circuit board

21‧‧‧Connecting mat

100‧‧‧ Chip package construction

110‧‧‧Substrate

111‧‧‧Upper surface

112‧‧‧ lower surface

113‧‧‧ plated through holes

114‧‧‧Internal finger

115‧‧‧External mat

120‧‧‧ wafer

121‧‧‧ solder pads

140‧‧‧ Sealant

150‧‧‧Mack layer

170‧‧‧welding line

180‧‧‧ solder balls

200‧‧‧ 矽 矽 连通 continuous extending chip package structure

210‧‧‧Substrate

211‧‧‧ upper surface

212‧‧‧ lower surface

213‧‧‧Substrate vias

214‧‧‧ retaining ring

215‧‧‧Bump bearing

216‧‧‧Void pad

220‧‧‧ wafer

221‧‧‧矽Perforated

230‧‧‧Electrical filler

231‧‧‧External bumps

232‧‧‧End

240‧‧‧ Sealant

250‧‧‧Mack layer

260‧‧‧ anisotropic conductive film

261‧‧‧Electrical particles

261A‧‧‧Electrical particles

Figure 1: Schematic cross-sectional view of a conventional wafer package structure.

2 is a cross-sectional view showing a wafer package structure in which a crucible is perforated and extended according to an embodiment of the present invention.

Figure 3 is a schematic illustration of the upper surface of a substrate in a wafer package construction in accordance with an embodiment of the present invention.

4 is a schematic view of a lower surface of a substrate of a wafer package structure in accordance with an embodiment of the present invention.

5A and 5H are schematic cross-sectional views of components in a process in accordance with an embodiment of the present invention, and a cross-sectional view of the wafer package structure bonded to an external printed circuit board.

200‧‧‧ 矽 矽 连通 continuous extending chip package structure

210‧‧‧Substrate

211‧‧‧ upper surface

212‧‧‧ lower surface

213‧‧‧Substrate vias

214‧‧‧ retaining ring

215‧‧‧Bump bearing

216‧‧‧Void pad

220‧‧‧ wafer

221‧‧‧矽Perforated

230‧‧‧Electrical filler

231‧‧‧External bumps

232‧‧‧End

240‧‧‧ Sealant

250‧‧‧Mack layer

Claims (14)

A wafer package structure in which a perforated via extends and extends, comprising: a substrate having an upper surface, a lower surface, and a plurality of substrate vias; and a wafer disposed on the upper surface of the substrate, the wafer having a plurality of turns The plurality of conductive fillers are vertically connected to the substrate through holes, and the plurality of conductive fillers are formed in the liquid filling manner in the through holes and the through holes of the substrate, and the conductive fillers are more prominent Forming a plurality of holes on the lower surface of the substrate to integrally connect the external bumps, wherein the conductive filler is a thermosetting resin containing metal particles; and a gel is formed on the substrate The upper surface to seal the wafer. The wafer package structure of claim 1, wherein the encapsulation system further covers the conductive fillers at a plurality of ends of the wafer. The chip package structure of claim 2, wherein the end portions of the conductive filler are formed into a plurality of bump portions larger than the plurality of turns. The wafer package structure of claim 1, wherein the conductive filling material is filled in a liquid-filled manner. The chip package structure of claim 1, further comprising a die bonding layer formed between the wafer and the substrate, and And the substrate is provided with a plurality of retaining rings on the upper surface, which surround the openings of the substrate through holes in the upper surface for blocking the flow of the adhesive layer into the substrate through holes. The chip package structure of claim 1, wherein the substrate is provided with a plurality of bump sockets on the lower surface, and the openings of the substrate through holes are formed in the lower surface. The circumscribing bumps of the conductive filler are bonded to the bump holders. The wafer package structure of claim 1, further comprising an anisotropic conductive film formed on the lower surface of the substrate and covering the external bumps. The wafer package structure of claim 7, wherein the anisotropic conductive film comprises a plurality of conductive particles of equal spherical diameter, wherein at least one of the conductive particles electrically contacts the external bumps to an external portion. The printed circuit board, wherein the electrically contactive conductive particles are partially embedded in corresponding corresponding bumps of the conductive filler. The wafer package structure of claim 1, wherein the upper surface of the substrate has an area close to a surface coverage area of the wafer. A chip package structure in which a perforated via extends and extends, comprising a substrate, a wafer disposed on the substrate, and a plurality of external bumps protruding from the substrate, wherein the external bumps are made of conductive filler Forming and penetrating the substrate and the wafer to Forming a plurality of exposed portions of the wafer, the chip package structure further comprising a die bond layer formed between the wafer and the substrate, and the substrate is provided with a plurality of retaining rings on the upper surface And surrounding the opening of the substrate through holes in the upper surface for blocking the flow of the adhesive layer into the substrate through holes. The wafer package structure of claim 10, further comprising a glue formed on the substrate to provide a surface of the wafer to seal the wafer and cover the ends. A wafer package structure in which a perforated via extends and extends, comprising: a substrate having an upper surface, a lower surface, and a plurality of substrate vias; and a wafer disposed on the upper surface of the substrate, the wafer having a plurality of turns The plurality of conductive fillers are vertically connected to the substrate through holes, and the plurality of conductive fillers are formed in the liquid filling manner in the through holes and the through holes of the substrate, and the conductive fillers are more prominent Forming a plurality of holes to form a plurality of externally connected bumps on the lower surface of the substrate; and forming a colloid on the upper surface of the substrate to seal the wafer; wherein the substrate is provided with a plurality of The bump holders on the lower surface surround the openings of the substrate through holes in the lower surface, and the external bumps of the conductive fillers are bonded to the bump holders. The wafer package structure of claim 11, further comprising an anisotropic conductive film formed on the lower surface of the substrate and covering the external bumps. The wafer package structure of claim 13, wherein the anisotropic conductive film comprises a plurality of conductive particles of equal spherical diameter, wherein at least one of the conductive particles electrically contacts the external bumps to an external portion. The printed circuit board, wherein the electrically contactive conductive particles are partially embedded in corresponding corresponding bumps of the conductive filler.