TW201017855A - Chip package with connecting extension of TSV - Google Patents

Chip package with connecting extension of TSV Download PDF

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Publication number
TW201017855A
TW201017855A TW097141868A TW97141868A TW201017855A TW 201017855 A TW201017855 A TW 201017855A TW 097141868 A TW097141868 A TW 097141868A TW 97141868 A TW97141868 A TW 97141868A TW 201017855 A TW201017855 A TW 201017855A
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Taiwan
Prior art keywords
substrate
wafer
package structure
holes
conductive
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TW097141868A
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Chinese (zh)
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TWI397164B (en
Inventor
Chi-Hung Chiou
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Powertech Technology Inc
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Priority to TW097141868A priority Critical patent/TWI397164B/en
Publication of TW201017855A publication Critical patent/TW201017855A/en
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Publication of TWI397164B publication Critical patent/TWI397164B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

Disclosed is a chip package with connecting extension of TSV (Through Silicon Via), primarily comprising a substrate, a chip disposed on the substrate, a plurality of conductive fillers and an encapsulant encapsulating the chip. The substrate has a plurality of through holes vertically corresponding to and connecting to a plurality of TSVs through the chip. The conductive fillers are filled in the TSVs and the through holes and are further extruded from the bottom surface of the substrate to form as external bumps with hole-to-hole connection as a whole. Accordingly, conventionally wire-bonding and ball-placing steps can be skipped in manufacturing the chip package. Furthermore, the chip package has a reduced total height and a smaller dimension.

Description

201017855 九、發明說明： 【發明所屬之技術領域1 本發明係有關於半導體贳置姓 M褒置特別係有關於一種矽 穿孔連通延伸之晶片封裝構造。 【先前技術】 在電子產品的微小化要求下’用以保護半導體晶片 並提供外部電路連接的晶片封襄構造需要符合輕薄短 小的發展趨勢。在晶片封裝構诰 τ发稱乂中，晶片與基板之間 的電性連接方式通常係採用打線方式，晶片封裝構造 則係藉由銲球作為對外接合之媒介n㈣具有 -定的打線孤高，使得㈣銲線之封㈣需具有較厚 的厚度，而難以降低整體的封裝厚度與封裝尺寸。 請參閱第1圖所示，一箱習知一站土 裡$知打線連接之晶片封裝 暑 構造100,主要包含一基板110、—晶片12〇、一封膠 體140、複數個銲線170以及複數個銲球18〇。該基板 110係具有一上表面111、一下表面112、複數個鍵通 孔11 3、複數個内接指丨丨4以及複數個外接墊1〗5。該 些内接指114係形成於該上表面π!之周邊，該些外 接墊115係形成於該下表面112,其中該些内接指u4 係藉由該些艘通孔113電性連接至該些外接塾115。該 些鍍通孔113係為在孔壁形成金屬層之貫通孔，並在 封裝過程之前便以填充物填滿以不突出於該上表面 1 1 1與該下表面1 1 2。在一黏晶步驟中，該晶片1 2 0係 設置於該基板110之該上表面111並且不可覆蓋該些 5 201017855 内接指114。通常該晶片120係利用一黏晶層150之 黏貼使其背面黏設於該基板11〇之該上表面111。在一 打線步驟中，該些銲線170係電性連接該晶片120之 複數個銲墊121至該基板110之該些内接指114,以達 到該晶片1 20與該基板1 1 0之間的電性互連。在一模 封步驟中，該封膠體140係形成於該基板110之該上 表面111，並密封該晶片120與該些銲線17〇〇在一植 球步驟中，利用迴焊方式使該些銲球180係設置於該 基板110之該些外接墊115，以作為該晶片封裝構造 100之對外端子。 在上述習知的晶片封裝構造100中，該晶片120與 該基板110係藉由該些銲線170進行電性連接。然而， 該些銲線170必須具有一定的打線弧高，使得該封膠 體140需具有相當的厚度才可避免銲線17〇外露之問201017855 IX. Description of the Invention: [Technical Field 1 of the Invention] The present invention relates to a semiconductor package, and is particularly related to a wafer package structure in which a perforated via extends. [Prior Art] Under the miniaturization of electronic products, a wafer package structure for protecting a semiconductor wafer and providing an external circuit connection needs to conform to a trend of being thin and short. In the chip package structure, the electrical connection between the wafer and the substrate is usually a wire bonding method, and the chip package structure has a fixed wire height by using the solder ball as a medium for external bonding. (4) The seal of the wire (4) needs to have a thick thickness, and it is difficult to reduce the overall package thickness and package size. Referring to FIG. 1 , a box of conventionally-packed soil-packaged summer structure 100 includes a substrate 110, a wafer 12, a gel 140, a plurality of bonding wires 170, and a plurality of 18 solder balls. The substrate 110 has an upper surface 111, a lower surface 112, a plurality of keyholes 11 3, a plurality of inscribed fingers 4, and a plurality of external pads 1 and 5. The inner connecting fingers 114 are formed on the outer surface π!, and the outer connecting pads 115 are formed on the lower surface 112. The inner connecting fingers u4 are electrically connected to the through holes 113. The external ports 115. The plated through holes 113 are through holes for forming a metal layer on the wall of the hole, and are filled with a filler before the packaging process so as not to protrude from the upper surface 1 1 1 and the lower surface 1 1 2 . In a die bonding step, the wafer 120 is disposed on the upper surface 111 of the substrate 110 and cannot cover the 5 201017855 internal fingers 114. Generally, the wafer 120 is adhered to the upper surface 111 of the substrate 11 by adhesion of a die layer 150. In a wire bonding step, the bonding wires 170 are electrically connected to the plurality of pads 121 of the wafer 120 to the internal fingers 114 of the substrate 110 to reach between the wafer 1 20 and the substrate 110 . Electrical interconnection. In a molding step, the encapsulant 140 is formed on the upper surface 111 of the substrate 110, and seals the wafer 120 and the bonding wires 17 in a ball implantation step, and the reflowing method is used to Solder balls 180 are disposed on the external pads 115 of the substrate 110 to serve as external terminals of the chip package structure 100. In the above-described conventional wafer package structure 100, the wafer 120 and the substrate 110 are electrically connected by the bonding wires 170. However, the bonding wires 170 must have a certain arcing height, so that the sealing body 140 needs to have a considerable thickness to avoid the exposure of the bonding wires 17〇.

題’因而造成該晶片封裝構造1〇〇具有較厚的厚度。 由於該些銲線170係連接該些銲墊121至該些内接指 11 4，故必須具有一定的長度與間距，以避免在模封的 過程中產生沖線的問題。並且該些内接指i 14位於該 基板no之晶片覆蓋區之外，以供該些銲線17〇連接 所以該基板11〇之尺寸需較大於該晶片12〇之尺寸 以供預留該些内接指114之形成位置，故無法縮小 基板110之尺寸，因而導致該晶片封裝構造100之 裝尺寸難以縮小。此外，當該些銲球i80對外接合時 會因為應力的產生而導致掉球，造成產品的可靠度 201017855 落。 另，有人提出一種先進的晶片封裝構造，具有矽 孔（Through SiliC0I1 via, TSV)之晶片設置於基板上 秒穿孔貫穿晶片，主要是運用在晶片的立體堆疊。 晶片與基板之結合界面中，最低層晶片的矽穿孔是 用焊料接合到基板的内接墊，由於晶片為半導體 質’而基板為有機材質，兩者材質不同導致存在有 . 膨服係數的差異，故應力會集中在晶片與基板之結 界面’導致烊料接合點的斷裂。在另一種晶片與基 之結合方式中，先在基板上設置插針，當晶片放置 基板上時，插針穿過晶片的矽穿孔達到電性連觸， 其中一插針不為直立或有彎斜現象時，會有孔對不 的問題’故製程良率甚低。並且，電性接觸不佳會 15且抗増加與訊號中斷的問題。 【發明内容】 ® 為了解決上述之問題，本發明之主要目的係在於 供一種矽穿孔速通延伸之晶片封裝構造，以液態填 方式形成之導電填充材能同時取代習知在打線步驟 成之銲線與在填球步驟形成之銲球，也不會有習知 穿孔在晶片與基板之結合界面中焊料接合•點斷裂的 題以及習知以揷針穿過晶片的矽穿孔造成扎對不準 低製程良率。此外，並能降低晶片封裝構造之整體 度與縮小封裝尺寸。 本發明的目的及解決其技術問題是採用以下技 穿 5 在 利 材 熱 合 板 於 當 準 有 提 充 形 矽 問 的 高 術 7 201017855 方案來實現的。本發明揭示一種矽穿孔連通延伸之晶 片封裝構造，主要包含一基板、一晶片、複數個導電 填充材以及一封膠趙。該基板係具有一上表面、一下 表面以及複數個基板通孔。該晶片係設置於該基板之 該上表面，該晶片係具有複數個矽穿孔，該些矽穿孔 與該些基板通孔係為縱向對應連通。該些導電填充材 係以液態填充方式形成於該些矽穿孔與該些基板通孔 中，該些導電填充材更突出於該基板之該下表面，以 形成為複數個孔對孔一體連接之外接凸塊。該封膠體 係形成於該基板之該上表面，以密封該晶片。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在前述晶片封裴構造中，該些導電填充材係可為内 含金屬粒子的熱固性樹脂。 在前述晶片封裝構造中，該些導電填充材係可由金 屬膏燒結成形。 在前述晶片封裝構造中，該封膠體係可更覆蓋該些 導電填充材外露在該晶片之複數個端部。 在前述晶片封裝構造中，該些導電填充材之該些端 部係可形成為複數個大於該些矽穿孔之凸塊部。 在前述晶片封裝構造中，該些導電填充材之液態填 充方式係可包含模封（transfer molding)。 在前述晶片封裝構造中，可另包含一黏晶層，係形 成於該晶片與該基板之間，並且該基板係設有複數個 8 201017855 位在續上表面之播環，其係環繞該些基板通孔在該 表面之開口，用以阻擔該黏晶層流入該些基板通孔 在前述晶片封裝構造中’該基板係可設有複數個 在該下表面之凸塊承座，其係環繞該些基板通孔在 下表面之開口，該些導電填充材之該些外接凸塊係 合於該些凸塊承座。 在前述晶片封裝構造中，可另包含一異方性導電 Φ 祺，係形成於該基板之該下表面並覆蓋該些外接凸场 在前述晶片封裝構造中，該異方性導電膠膜係可 含複數個等球徑的導電顆粒，其中至少一導電顆粒 電性接觸該些外接凸塊至一外部印刷電路板，其中 述電性接觸之導電顆粒係局部嵌陷於該些導電填充 之對應外接凸塊内。 在前述晶片封裝構造中，該基板之該上表面係可 有一接近該晶片之表面覆蓋區之面積。 © 由以上技術方案可以看出，本發明之矽穿孔連通 伸之晶片封裝構造’具有以下優點與功效·· 一、 以液態填充方式形成之導電填充材與封裝構造 部元件具有特定的連接關係能同時取代習知之 線與鲜球’故可省略打線步驟與植球步驟，以 化製程。 二、 利用導電填充材同時貫穿基板與晶片並形成孔 孔一體連接之外接凸塊，故封膠體不需要保留 過晶片的打線弧高，並且基板之上表面周邊不 上 〇 位 該 結 膠 ϊ ° 包 係 所 材 具 延 内 銲 簡 對 超 需 9 201017855 要預設内指指的區域，故可降低晶片封裝構造之 整體高度以及縮小封裝尺寸。 三、 由導電填充材的一端形成之外接凸塊可取代習知 銲球，以供在表面接合（SMT)時使用異方性導電 膠，使得異方性導電膠内的導電粒子可局部嵌埋 在外接凸塊。 四、 利用導電填充材的材料特性，例如銀膠，產生高 流動性並具有韌性，以防止外接凸塊或孔内斷裂。 翁 五、 藉由導電填充材在晶片表面之端部形成為大於矽 穿孔之凸塊部，可防止該些導電填充材的鬆脫。 六、 藉由導電填充材以模封方式形成，能使導電填充 材之外接凸塊具有一致且整齊的形狀。 七、 藉由凸塊承座環繞基板通孔在基板下表面之開 口 ，能控制外接凸塊在基板下表面之覆蓋面積並 可增進外接凸塊的結合力。 ^ 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然 應注意的是，該些圖示均為簡化之示意圖，僅以示意 方法來說明本發明之基本架構或實施方法，故僅顯示 與本案有關之元件與組合關係，圖中所顯示之元件並 非以實際實施之數目、形狀、尺寸做等比例繪製，某 些尺寸比例與其他相關尺寸比例或已誇張或是簡化處 理，以提供更清楚的描述。實際實施之數目、形狀及 尺寸比例為一種選置性之設計，詳細之元件佈局可能 10 201017855 更為複雜。 依據.本發明之一具體實施例，一種妙穿孔連通 延伸 之晶片封裝構造舉例說明於第2圖之截面示意圖。該 晶片封裝構造200主要包含一基板21〇、一晶片22〇 複數個導電填充材230以及一封膠體24〇。該基板 舉例說明於第3圖之基板上表面示意圖以及第4圖之 基板下表面示意圖。該基板210係具有一上表面211、 一下表面212以及複數個基板通孔213。該些基板通 ^ 孔213係由該上表面211貫穿至該下表面212，該些 基板通孔2 1 3係可為無電性連接功能的貫穿孔，即該 些基板通孔213内可以無電鍍金屬層。在本實施例 中’該些基板通孔213係可以雷射鑽孔或機械穿孔等 方式形成。該些基板通孔2 1 3係可為陣列排列、周邊 排列或是單/多排中心線排列。較佳地，該基板2 1 0之 該上表面211係可具有一接近該晶片220之表面覆蓋 ❹ 區之面積，以達成晶片尺寸封裝，而不需要預留在習 知基板上表面周圍的内接指。 請參閱第2圖所示，該晶片220係設置於該基板 210之該上表面211，該晶片220係具有複數個矽穿孔 22 1，該些矽穿孔22 1與該些基板通孔2 1 3係為縱向對 應連通。該些矽穿孔221係貫穿該晶片220，該些矽 穿孔221内可具有金屬層或其中一開口更貫穿該晶片 220之銲墊，以作為該晶片220之内部端子。炎利用 該些導電填充材230作為連接該晶片220之該些矽穿 11 201017855 . 孔221之電氣訊號之傳遞通路。請再參閱第2圖所示， 該晶片220係以該些矽穿孔221對準於該些基板通孔 2 13之方式設置於該基板210上，以達到縱向對應連 通。該些矽穿孔221之形成可利用既有的矽穿孔製造 技術，例如由IBM公司開發的 TSV(Through Silicon Via)晶片連接技術。 在本實施例中，該晶片封裝構造2 00可另包含一黏 晶層250，其係黏接該晶片220與該基板210。請參閱 第2圖所示，該黏晶層250係形成於該晶片220與該 基板210之間。並且較佳地，該基板210係設有複數 個位在該上表面211之擋環2 14(如第3圖所示），其係 環繞該些基板通孔2 1 3在該上表面2 11之開口，用以 阻擋該黏晶層250流入該些基板通孔213。關於該黏 晶層250之形成方法，可先將該黏晶層250形成於該 基板210上，再使該晶片220壓合於該黏晶層250。 Q 在另一實施例中，該黏晶層2 5 0的形成係採用底部填 充（under Hlling)的方式，即先設置該晶片220在該基 板2 1 0上，再點塗液態黏著膠，以形成填滿在該晶片 220與該基板210之間的黏晶層250 ’使得該晶片220 與該基板210為緊密接合。當該黏晶層250係以底部 填充形成時，該黏晶層 250在未固化時具有高流動 性，故該些擋環214壓觸至該晶片220為一較佳的技 術手段，以有效阻擂該黏晶層2 5 0流入該些基板通孔 213。較佳地，該些擋環214的厚度係可略高於該基板 12 201017855 210在該上表面211之防焊層的厚度，以發揮阻擋該 黏晶層250之作用。在不同實施例中’該基板係 可不具有防焊層’以進一步提升該些擋環214的擒膠 效果並可加強該晶片220與該基板210之間之黏著 力。此外，該些檔環214之材質可為金屬’如銅。該 些擋環214係可為該基板210表面突出之金屬環’並 位於該基板210用以設置該晶片220的區域内° 請參閱第2圖所示’該些導電填充材230係以液態 ^ 填充方式形成於該些矽穿孔221與該些基板通孔213 中，該些導電填充材230更突出於該基板210之該下 表面212，以形成為複數個孔對孔一體連接之外接凸 塊2 3 1。在此所述的「孔對孔一體連接」係指每一導 電填充材230在一體連接對應外接凸塊231的部位是 更連接填充入縱向對應的該些矽穿孔221與該些基板 通孔213。換言之，該些外接凸塊231係為該些導電 Q 填充材230之突出部位，其一體連接之根部更可嵌埋 貫穿該基板210與該晶片220，形成為不可動搖或脫 落的外接端子，為習知焊接在基板表面的銲球所不可 預期的作用。 較佳地，該些導電填充材230係可為内含金屬粒子 的熱固性樹脂，例如銀膠，產生高流動性並具有韌性， 以防止該些外接凸塊23 1或孔内斷裂》在另一實施例 中，該些導電填充材230係可由金屬膏燒結成形，例 如銅膏或錫膏。 13 201017855 該些導電填充材230之液態填充方式係可包含模 封、液態點注或為毛細現象的孔填充’其中以模封方 式為較佳。請參閱第5D圖所示，在模封過程中可利用 一下模具10以使該些導電填充材230之外接凸塊231 具有一致且整齊的形狀。該些外接凸塊23丨在該基板 210之該下表面212的覆蓋面積係可大於該導電填充 材23 0在該些基板通孔213内的截面積，以增加該些 _ 外接凸塊23 1對外電性連接的接觸面積。 由於該些導電填充材230係用以電性連接該晶片 220與該基板210並提供作為該晶片封裝構造200之 對外接合，故能同時取代習知之銲線與銲球，可省略 習知打線步驟與植球步驟，以簡化製程。 請參閱第2圖所示，較佳地，該基板210係可設有 複數個位在該下表面212之凸塊承座215，其係環繞 該些基板通孔213在該下表面212之開口，該些導電 ^ 填充材230之該些外接凸塊23 1係結合於該些凸塊承 座215，該些凸塊承座215具有控制該些導電填充材 23 0之該些外接凸塊23 1在該基板210之該下表面212 之覆蓋面積並可增進該些外接凸塊231的結合力°其 中該些外接凸塊 23 1係可完全覆蓋該些凸塊承座 215。更具體而言’該些凸塊承座215之尺寸係稍大於 該些擔環214之尺寸。請參閱第4圖所示’在本實施 例中，該些凸塊承座215之形狀係可為具有開孔之矩 形。此外，該基板210更具有複數個虛置墊216’係 14 201017855 设置於該基板210之該下表面212並顯露於 212’以增加散熱效果’但可不具有訊號傳遗 具體而言’該些虛置墊2丨6係排列於該基板 相對侧邊或周邊》 請參閱第2圖所示，該封膠體24〇係形成 210之該上表面211’以密封該晶片22〇。該刻 係提供適當的封裝保護，以防止電性短路 鲁 染。請再參閱第2圖所示，該封膠體240係 該些導電填充材230外露在該晶片220之複 232’以形成單晶片封裝之結構。較佳地，該 充材230之該些端部232係可形成為複數個 梦穿孔221之凸塊部，可防止該些導電填充 鬆脫。請參閱第2圖所示，在本實施例中， 填充材230係形成為一如「工」字形之截面 防止脫落或位移。 Q 由上述可知，利用該些導電填充材230填 應且連通之該些矽穿孔221與該些基板通孔 構，使該晶片220之電氣訊號能傳遞至突出 210之該些外接凸塊23 1，能同時取代習知在 形成之銲線與在植球步驟形成之銲球，也不 矽穿孔在晶片與基板之結合界面中焊料接合 問題以及習知以插針穿過晶片的矽穿孔造成 的低製程良率。此外，利用該些導電填充材 貫穿該基板210與該晶片220並形成孔對孔 該下表面 的作用。 2 1 0之兩 於該基板 膠體240 與塵埃污 可更覆蓋 數個端部 些導電填 大於該些 材230的 每一導電 形狀，以 入縱向對 213的結 於該基板 打線步驟 會有習知 點斷裂的 孔對不準 230同時 一體連接 15 201017855 之該些外接凸塊231，故該封膠體240不需要保留超 過晶片的打線弧高，並且基板之上表面周邊不需要預 設内指指的區域，故可降低該晶片封裝構造200之整 體高度以及縮小鉗裝尺寸。 在本實施例中，如第5H圖所示，該晶片封裝構造 2 00可另包含一異方性導電膠膜260,係形成於該基板 210之該下表面212並覆蓋該些外接凸塊231。該些外 接凸塊23 1係突出於該基板210之該下表面212，有 φ 助於該異方性導電膠膜260接觸。該異方性導電膠膜 260係可包含複數個等球徑的導電顆粒26卜其中至少 一導電顆粒26 1A係電性接觸該些外接凸塊231至一外 部印刷電路板2〇之複數個連接墊21，其中所述電性 接觸之導電顆粒26 1A係局部嵌陷於該些導電填充材 230之對應外接凸塊231内，使得電性接觸更為確實。 當該晶片封裝構造200與該外部印刷電路板2〇接合 G 時’該晶片封裝構造200會下壓至該異方性導電膠膜 260’而該些導電填充材23〇之該些外接凸塊231會壓 到至夕 導電顆粒261A，因而使該晶片封裝構造200 、 部印刷電路板20電性導通，其餘的該些導電顆 粒261會由非導電性的膠體區隔開來，不會導致電性 田該些導電填充材23 0的一端形成之該些外接 凸塊231可取代習知銲球，以供在表面接合（SMT)時使 性導電膠260，使得該異方性導電膠260内 的導雷姑7The problem 'causes the wafer package structure 1 to have a thicker thickness. Since the bonding wires 170 are connected to the pads 121 to the inscribed fingers 11, they must have a certain length and spacing to avoid the problem of punching during the molding process. And the internal fingers i 14 are located outside the wafer coverage area of the substrate no for the connection of the bonding wires 17 so that the size of the substrate 11 is larger than the size of the wafer 12 to reserve the Since the position of the internal finger 114 is formed, the size of the substrate 110 cannot be reduced, which makes it difficult to reduce the size of the package structure 100. In addition, when the solder balls i80 are externally joined, the ball will be dropped due to the stress, resulting in product reliability 201017855. In addition, an advanced chip package structure has been proposed in which a wafer having a Thorough SiliC0I1 via (TSV) is placed on a substrate. The second hole is inserted through the wafer, and is mainly applied to a three-dimensional stack of the wafer. In the bonding interface between the wafer and the substrate, the germanium perforation of the lowest layer wafer is soldered to the inner pad of the substrate. Since the wafer is a semiconductor material and the substrate is made of an organic material, the difference between the two materials results in a difference in the expansion coefficient. Therefore, the stress will concentrate on the junction interface between the wafer and the substrate 'causing the breakage of the junction of the material. In another method of combining a wafer with a substrate, a pin is first disposed on the substrate. When the wafer is placed on the substrate, the pin passes through the through hole of the wafer to achieve electrical contact, wherein one of the pins is not upright or curved. When the phenomenon is oblique, there will be a problem that the hole is not right, so the process yield is very low. Moreover, poor electrical contact will be a problem of resistance and signal interruption. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a wafer package structure with a 矽-perforation and a fast-passing extension. The conductive filler formed by liquid filling can simultaneously replace the soldering in the wire bonding step. The wire and the solder ball formed in the ball filling step, there is no known problem that the solder joints in the bonding interface between the wafer and the substrate are broken, and the conventional piercing of the pin through the wafer causes the misalignment. Low process yield. In addition, it can reduce the overall integrity of the package structure and reduce the package size. The object of the present invention and the technical problem thereof are solved by the following technique 5 in the case of a heat sealing plate for a high-tech 7 201017855 solution. The invention discloses a wafer package structure in which a crucible is connected and extended, and mainly comprises a substrate, a wafer, a plurality of conductive fillers and a glue. The substrate has an upper surface, a lower surface, and a plurality of substrate vias. The wafer is disposed on the upper surface of the substrate, and the wafer has a plurality of turns and the through holes are longitudinally correspondingly communicated with the substrate through holes. The conductive filler is formed in the liquid filling manner in the through holes and the through holes of the substrate, and the conductive filler protrudes from the lower surface of the substrate to form a plurality of holes and the holes are integrally connected. External bumps. The encapsulant is formed on the upper surface of the substrate to seal the wafer. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the above wafer sealing structure, the conductive fillers may be thermosetting resins containing metal particles. In the aforementioned wafer package construction, the conductive fillers may be formed by sintering of a metal paste. In the aforementioned wafer package construction, the encapsulation system may cover the plurality of conductive pastes at a plurality of ends of the wafer. In the foregoing chip package structure, the ends of the conductive fillers may be formed into a plurality of bump portions larger than the turns of the turns. In the foregoing wafer package construction, the liquid filling of the conductive fillers may include transfer molding. In the foregoing chip package structure, a die bond layer may be further formed between the wafer and the substrate, and the substrate is provided with a plurality of 8 201017855 broadcast rings on the continuous surface, which surround the An opening of the substrate via hole at the surface for blocking the flow of the die layer into the substrate via hole in the chip package structure. The substrate may be provided with a plurality of bump holders on the lower surface. Surrounding the opening of the substrate through holes in the lower surface, the external bumps of the conductive fillers are coupled to the bump holders. In the foregoing chip package structure, an anisotropic conductive Φ 祺 may be further formed on the lower surface of the substrate and cover the external lands in the chip package structure, and the anisotropic conductive film may be And a plurality of conductive particles having a plurality of equal spherical diameters, wherein at least one of the conductive particles electrically contacts the external bumps to an external printed circuit board, wherein the electrically conductive conductive particles are partially embedded in the corresponding external convex portions of the conductive fills Within the block. In the foregoing wafer package construction, the upper surface of the substrate may have an area close to the surface coverage area of the wafer. It can be seen from the above technical solution that the wafer package structure of the present invention has the following advantages and effects: 1. The conductive filler formed by liquid filling has a specific connection relationship with the package structure component. Instead of the line of the custom and the fresh ball, the wire step and the ball-planting step can be omitted to make the process. Second, the conductive filler is used to simultaneously penetrate the substrate and the wafer and form the holes to integrally connect the bumps. Therefore, the sealing body does not need to retain the arcing height of the wafer, and the periphery of the upper surface of the substrate is not clamped. The package is made of the inner soldering strip. The ultra-need. 9 201017855 The area of the inner finger is preset, so the overall height of the chip package structure can be reduced and the package size can be reduced. 3. The external bump formed by one end of the conductive filler can replace the conventional solder ball for the use of an anisotropic conductive paste in surface bonding (SMT), so that the conductive particles in the anisotropic conductive paste can be partially embedded. Attach the bumps. Fourth, the material properties of the conductive filler, such as silver paste, are used to produce high flow and toughness to prevent rupture of the external bumps or holes. The utility model can prevent the conductive filler from being loosened by forming the bump portion of the surface of the wafer at the end of the surface of the wafer to be larger than the perforation of the conductive filler. 6. Formed by means of a conductive filler, the conductive filler can have a uniform and neat shape. 7. The opening of the bump through the substrate through hole on the lower surface of the substrate can control the coverage area of the external bump on the lower surface of the substrate and improve the bonding force of the external bump. [Embodiment] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to one embodiment of the present invention, a wafer package structure in which a well-perforated via extends is illustrated in a cross-sectional view of FIG. The chip package structure 200 mainly includes a substrate 21, a wafer 22, a plurality of conductive fillers 230, and a gel 24 〇. The substrate is exemplified in the schematic diagram of the upper surface of the substrate in Fig. 3 and the lower surface of the substrate in Fig. 4. The substrate 210 has an upper surface 211, a lower surface 212, and a plurality of substrate vias 213. The substrate through holes 213 are penetrated from the upper surface 211 to the lower surface 212. The substrate through holes 213 can be through holes of a non-electrical connection function, that is, the substrate through holes 213 can be electroless. Metal layer. In the present embodiment, the substrate through holes 213 may be formed by laser drilling or mechanical perforation. The substrate through holes 2 1 3 may be arranged in an array, in a peripheral arrangement, or in a single/multiple center line arrangement. Preferably, the upper surface 211 of the substrate 210 has an area close to the surface of the wafer 220 to achieve a wafer size package without being reserved in the periphery of the upper surface of the conventional substrate. Fingers. As shown in FIG. 2, the wafer 220 is disposed on the upper surface 211 of the substrate 210. The wafer 220 has a plurality of turns 2211, and the through holes 22 1 and the substrate through holes 2 1 3 It is connected in portrait orientation. The turns 221 are through the die 220. The vias 221 may have a metal layer or a pad extending through the die 220 to serve as an internal terminal of the die 220. The conductive filler 230 is used as a transmission path for connecting the electrical signals of the holes 221 to the wafers 220. Referring to FIG. 2 again, the wafer 220 is disposed on the substrate 210 in such a manner that the turns 221 are aligned with the substrate through holes 213 to achieve vertical corresponding communication. The formation of the turns 221 can utilize existing helium perforation fabrication techniques such as TSV (Through Silicon Via) wafer bonding technology developed by IBM Corporation. In this embodiment, the chip package structure 200 may further include an adhesive layer 250 for bonding the wafer 220 and the substrate 210. Referring to FIG. 2, the die layer 250 is formed between the wafer 220 and the substrate 210. And preferably, the substrate 210 is provided with a plurality of retaining rings 2 14 (shown in FIG. 3) located on the upper surface 211, which surround the substrate through holes 2 1 3 on the upper surface 2 11 The opening is configured to block the adhesion layer 250 from flowing into the substrate through holes 213. For the method of forming the adhesion layer 250, the adhesion layer 250 may be formed on the substrate 210, and the wafer 220 may be pressed against the adhesion layer 250. In another embodiment, the formation of the die layer 250 is performed by an under-filling method, that is, the wafer 220 is first disposed on the substrate 210, and then the liquid adhesive is applied. Forming a die layer 250' filled between the wafer 220 and the substrate 210 causes the wafer 220 to be in close contact with the substrate 210. When the viscous layer 250 is formed by underfill, the viscous layer 250 has high fluidity when uncured, so that the retaining ring 214 is pressed against the wafer 220 as a better technical means to effectively block The viscous layer 250 flows into the substrate vias 213. Preferably, the thickness of the retaining ring 214 is slightly higher than the thickness of the solder resist layer of the substrate 12 201017855 210 on the upper surface 211 to function to block the die layer 250. In various embodiments, the substrate may have no solder resist layer to further enhance the silicone effect of the retaining ring 214 and enhance the adhesion between the wafer 220 and the substrate 210. In addition, the material of the retaining ring 214 may be a metal such as copper. The retaining ring 214 can be a metal ring that protrudes from the surface of the substrate 210 and is located in the area where the substrate 210 is used to set the wafer 220. Please refer to FIG. 2, the conductive fillers 230 are in a liquid state ^ A filling method is formed in the plurality of through holes 221 and the substrate through holes 213. The conductive filling members 230 protrude from the lower surface 212 of the substrate 210 to form a plurality of holes and holes for integrally connecting the external bumps. 2 3 1. As used herein, the term "hole-to-hole integral connection" means that each of the conductive fillers 230 is connected to the corresponding ridges 221 and the substrate vias 213 in a portion where the corresponding external bumps 231 are integrally connected. . In other words, the external bumps 231 are protruding portions of the conductive Q fillers 230, and the integrally connected root portions are embedded in the substrate 210 and the wafer 220 to form an external terminal that is not shaken or detached. It is conventional to have an unpredictable effect of solder balls soldered on the surface of the substrate. Preferably, the conductive filler 230 is a thermosetting resin containing metal particles, such as silver paste, which has high fluidity and toughness to prevent the external bumps 23 1 or fractures in the holes. In an embodiment, the conductive fillers 230 may be formed by sintering a metal paste, such as a copper paste or a solder paste. 13 201017855 The liquid filling manner of the conductive filler 230 may include molding, liquid spotting or pore filling for capillary phenomenon, wherein the molding method is preferred. Referring to Figure 5D, the mold 10 can be utilized during the molding process to provide the conductive filler 230 with a uniform and tidy shape. The coverage area of the pedestal bumps 23 on the lower surface 212 of the substrate 210 may be larger than the cross-sectional area of the conductive fillers 230 in the substrate vias 213 to increase the _ external bumps 23 1 Contact area for external electrical connection. Since the conductive filler 230 is used to electrically connect the wafer 220 and the substrate 210 and provide external bonding as the wafer package structure 200, the solder wire and the solder ball can be replaced at the same time, and the conventional wire bonding step can be omitted. Steps with the ball planting to simplify the process. Referring to FIG. 2, the substrate 210 is preferably provided with a plurality of bump holders 215 located on the lower surface 212, which surround the opening of the substrate through holes 213 at the lower surface 212. The plurality of external bumps 23 1 of the conductive filler 230 are coupled to the bump receptacles 215 , and the bump receptacles 215 have the external bumps 23 for controlling the conductive fillers 230 . The coverage area of the lower surface 212 of the substrate 210 can improve the bonding force of the external bumps 231. The external bumps 23 1 can completely cover the bump holders 215. More specifically, the size of the bump receptacles 215 is slightly larger than the dimensions of the stretchers 214. Referring to Fig. 4, in the present embodiment, the shape of the bump holders 215 may be a rectangular shape having an opening. In addition, the substrate 210 further has a plurality of dummy pads 216 ′ system 14 201017855 disposed on the lower surface 212 of the substrate 210 and exposed at 212 ′ to increase the heat dissipation effect, but may not have a signal transmission, specifically The pads 2丨6 are arranged on opposite sides or the periphery of the substrate. Referring to FIG. 2, the encapsulant 24 is formed on the upper surface 211' of the 210 to seal the wafer 22'. This is to provide proper package protection to prevent electrical shorting. Referring to FIG. 2 again, the encapsulant 240 is formed by exposing the conductive filler 230 to the 232' of the wafer 220 to form a single-chip package. Preferably, the end portions 232 of the filler 230 are formed as a plurality of bump portions 221 of the dream perforations 221 to prevent the conductive filling from coming loose. Referring to Fig. 2, in the present embodiment, the filler 230 is formed into a cross section such as a "work" shape to prevent detachment or displacement. As can be seen from the above, the puncturing holes 221 and the substrate via holes are filled and connected by the conductive filler 230, so that the electrical signals of the wafer 220 can be transmitted to the external bumps 23 of the protrusions 210. It can simultaneously replace the conventionally formed soldering wire and the solder ball formed in the ball-forming step, nor the problem of solder joint in the bonding interface between the wafer and the substrate, and the conventional piercing of the pin through the wafer. Low process yield. In addition, the conductive filler is used to penetrate the substrate 210 and the wafer 220 to form a hole to the lower surface of the hole. 2 1 0 2 may be covered by the substrate colloid 240 and the dust stain to cover a plurality of conductive fillings each of the conductive shapes of the plurality of materials 230, so that the step of joining the longitudinal pair 213 to the substrate is known. The hole-breaking hole pair 230 does not simultaneously connect the external bumps 231 of 15 201017855, so the seal body 240 does not need to remain above the arcing height of the wafer, and the peripheral surface of the substrate does not need to be preset. The area can reduce the overall height of the chip package structure 200 and reduce the size of the package. In this embodiment, as shown in FIG. 5H, the chip package structure 200 may further include an anisotropic conductive film 260 formed on the lower surface 212 of the substrate 210 and covering the external bumps 231. . The external bumps 23 1 protrude from the lower surface 212 of the substrate 210, and φ facilitates contact of the anisotropic conductive film 260. The anisotropic conductive film 260 may comprise a plurality of conductive particles 26 of equal spherical diameter, wherein at least one of the conductive particles 26 1A electrically contacts the plurality of connections of the external bumps 231 to an external printed circuit board 2 The pad 21, wherein the electrically contacted conductive particles 26 1A are partially embedded in the corresponding external bumps 231 of the conductive fillers 230, so that the electrical contact is more reliable. When the chip package structure 200 is bonded to the external printed circuit board 2, the chip package structure 200 is pressed down to the anisotropic conductive film 260', and the conductive fillers 23 are surrounded by the external bumps. 231 will be pressed to the conductive particles 261A, so that the chip package structure 200, the portion of the printed circuit board 20 is electrically connected, and the remaining conductive particles 261 will be separated by a non-conductive colloidal region, which will not cause electricity. The external bumps 231 formed by one end of the conductive fillers 230 can replace the conventional solder balls for enabling the conductive adhesive 260 during surface bonding (SMT), so that the anisotropic conductive adhesive 260 is Guide

子261A可局部欲埋在該些外接凸塊231，I 16 201017855 .使該晶片封裝構造200與該外部印刷電路板2〇結 此方式亦可運用在手機、記憶卡以及記憶體模組 本發明進一步說明該晶片封裝構造2〇〇之製 法，以彰顯本案的功效。請參閱第5八至5E圖之 截面示意圖。 首先’請參閱第5A圖所示，提供該晶片22〇 晶片220係具有複數個矽穿孔221，該些妙穿孔 的形成可採用離子反應蝕刻或是雷射鑽孔等技術 著，請參閱第5B圖所示，提供該基板21〇，用以 該晶片220’該基板210係具有複數個貫穿該上 211至該下表面212之基板通孔213。該晶片220 該些矽穿孔221對準於該些基板通孔213之方式 於該基板210之該上表面211。請再參閱第5B 示’一黏晶層250係局部塗佈在該基板21〇之該 面211且不覆蓋該些基板通孔213。在本實施例 〇 該基板210更設有複數個擋環214以及複數個凸 座215’該些擋環214係位在該上表面211並環 些基板通孔213在該上表面211之開口，該些凸 座215係位在該下表面212並環繞該些基板通孔 在該下表面212之開口。接著，請參閱第5C圖所 在黏晶時’該些矽穿孔22 1可縱向對應連通至該 板通孔213,並可藉由該些擋環214阻擋該黏晶層 流入該些基板通孔213’以避免該黏晶層250溢 問題。較佳地’該些擋環2 14的厚度係略高於該 合， 〇 造方 元件 。該 22 1 。接 承載 表面 係以 黏貼 圖所 上表 中， 塊承 繞該 塊承 213 示， 些基 250 膠之 基板 17 201017855 210之防焊層的厚度，以發揮擋膠之作用。 之後，請參閱第5D圖所示’提供一下模具1〇並將 已承載有該晶片220之基板210置放於該下模具1〇， 其中該基板210之該下表面212係朝向該下模具1〇。 該下模具1〇係具有一定位槽Π及複數個形成於該定 位槽11内之凹穴12，其中該些凹六12的深度係大於 該定位槽11的深度。該定位槽11係用以容置該基板 210，且該定位槽11之尺寸係概等於該基板210之尺 寸，以避免該基板210位移。該些凹穴12係對準該些 基板通孔213，且該些凹穴12之尺寸係大於該些基板 通孔213的截面積，用以形成該些外接凸塊231。接 著，請參閱第5Ε圖所示，可利用模封方式填入該些導 電填充材23 0於該些矽穿孔22 1與該些基板通孔213, 同時利用該下模具10之該些凹穴12承接該些由上而 下的導電填充材230，以形成複數個具有一致且整齊 形狀的外接凸塊231。在形成該些外接凸塊231之後， 烘烤固化該些導電填充材230，使得該晶片220與該 基板210上下導通結合。在本實施例中，該些導電填 充材23 0更具有複數個外露在該晶片220且大於該些 矽穿孔22 1之端部232。因此，藉由該些外接凸塊231 與該些端部232可防止該些導電填充材230的鬆脫。 請參閱第5F圖所示，形成該封膠體240於該基板 210之該上表面211，並密封該晶片220與該些導電填 充材230之該些端部232，以形成單晶片封裝之結構。 260 260The sub-261A can be partially buried in the external bumps 231, I 16 201017855. The chip package structure 200 and the external printed circuit board 2 can also be used in the mobile phone, the memory card and the memory module. The method of manufacturing the chip package structure is further described to demonstrate the efficacy of the present invention. See section 5-8 to 5E for a cross-sectional view. First, please refer to FIG. 5A, the wafer 22 is provided with a plurality of turns 221, and the formation of the holes can be performed by ion-reactive etching or laser drilling, see section 5B. As shown, the substrate 21 is provided for the wafer 220' to have a plurality of substrate vias 213 extending through the upper 211 to the lower surface 212. The wafers 220 are aligned with the substrate vias 213 in the manner of the upper surface 211 of the substrate 210. Referring to FIG. 5B, a layer of the adhesive layer 250 is partially applied to the surface 211 of the substrate 21 and does not cover the substrate vias 213. In this embodiment, the substrate 210 is further provided with a plurality of retaining rings 214 and a plurality of protruding seats 215 ′. The retaining rings 214 are fastened to the upper surface 211 and surround the opening of the substrate through holes 213 at the upper surface 211 . The protrusions 215 are located on the lower surface 212 and surround the opening of the substrate through holes at the lower surface 212. Then, the 矽 22 22 22 22 ' ' ' ' ' ' ' ' ' 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 213 'to avoid the problem of the sticky layer 250 overflow. Preferably, the thickness of the retaining ring 2 14 is slightly higher than the thickness of the retaining element. The 22 1 . The load bearing surface is attached to the upper surface of the block, and the block is wrapped around the block 213 to show the thickness of the solder resist layer of the base substrate 25 201017855 210 to play the role of the rubber stopper. After that, please refer to FIG. 5D to provide a mold 1 and place the substrate 210 on which the wafer 220 has been carried in the lower mold 1 , wherein the lower surface 212 of the substrate 210 faces the lower mold 1 Hey. The lower mold 1 has a positioning groove and a plurality of pockets 12 formed in the positioning groove 11, wherein the depth of the recesses 6 is greater than the depth of the positioning groove 11. The positioning slot 11 is for receiving the substrate 210, and the positioning slot 11 is substantially equal in size to the substrate 210 to avoid displacement of the substrate 210. The recesses 12 are aligned with the substrate through holes 213, and the recesses 12 are larger than the cross-sectional areas of the substrate through holes 213 for forming the external bumps 231. Then, as shown in FIG. 5 , the conductive fillers 23 0 can be filled into the through holes 22 1 and the substrate through holes 213 by using a molding method, and the recesses of the lower mold 10 are utilized. 12 receives the top-down conductive filler 230 to form a plurality of contiguous bumps 231 having a uniform and uniform shape. After the external bumps 231 are formed, the conductive fillers 230 are baked and cured, so that the wafers 220 are electrically connected to the substrate 210. In this embodiment, the conductive fillers 230 have a plurality of ends 232 exposed on the wafer 220 and larger than the turns 2211. Therefore, the conductive bumps 230 can be prevented from being loosened by the external bumps 231 and the end portions 232. Referring to FIG. 5F, the encapsulant 240 is formed on the upper surface 211 of the substrate 210, and the ends of the wafer 220 and the conductive fillers 230 are sealed to form a single-chip package structure. 260 260

201017855 接著’ S青參閱第5G圖所示，將一異方性導電膠膜 貼覆在一外部印刷電路板2〇上’並覆蓋該外部印 路板20之複數個連接墊21。該異方性導電膠膜 係包含複數個等球徑的導電顆粒26丨。最後，請 第5H圖所示，壓合該晶片封裝構造2〇〇至該外部 電路板20,並藉由該異方性導電膠膜26〇之至少 電顆粒26 1A電性接觸該些外接凸塊231至該些連 2 1，以達到該晶片封裝構造2〇〇與該外部印刷電 20之電性互連。 因此，由以上的製造方法可知，可以省略習矢 線步驟與植球步驟，在模封步驟之後再進行標裔 與切割步驟即可完成整個晶片封裳製帛。本發明 -膠填孔之步驟取代習知打線步驟與植球步驟， 會有習知沖線的問題。 以上所述，僅是本發明的較佳實施例而已，立 本發明作任何形式上的限制，雖然本發明已以輕 施例揭露如上，然而並非用以限定本發明，任作 本項技術者’在不脫離本發明之技術範圍内1 任何簡單修改、等效性轡 注變化與修飾，均仍屬於才 的技術範圍内。 、$ 【圖式簡單說明】 第1圖：習知晶片封裝播 衮構造之截面示意圖。 第2圖：依據本發明一且擁奋 具體實施例的一種矽穿 延伸之晶片封裝播 屐構造之截面示意圖。 刷電 260 參閱 印刷 一導 接墊 路板 之打 步驟 能以 亦不 非對 佳實 熟悉 作的 發明 連通 19 201017855 第3圖：依據本發明之一具體實施例的晶片封裝構造 的基板上表面示意圖。 第4圖：依據本發明之一具體實施例的晶片封裝構造 的基板下表面示意圖。 第5A與5H圖：依據本發明之一具鱧實施例的晶片封 裝構造在製程中元件的截面示意圖以及該晶 片封裝構造接合至外部印刷電路板之截面示 意圖。 【主要元件符號說明】 10 下模具 11 定位槽 12 凹穴 20 外部印刷電路板 21 連接墊 100 晶片封裝構造 110 基板 111 上表面 112 下表面 113 鍍通孔 114 内接指 115 外接墊 120 晶片 121 銲墊 140 封膠體 150 黏晶層 170 銲線 180 銲球 200 矽穿孔連通延伸之晶片封裝構造 210 基板 211 上表面 212 下表面 213 基板通孔 214 擋環 215 凸塊承座 216 虛置墊 220 晶片 221 矽穿孔 230 導電填充材 231 外接凸塊 232 端部 240 封膠體 250 黏晶層 260 異方性導電膠膜 261 導電顆粒 20 201017855 261A導電顆粒 ❹201017855 Next, as shown in FIG. 5G, an anisotropic conductive film is attached to an external printed circuit board 2' and covers a plurality of connection pads 21 of the external printed circuit board 20. The anisotropic conductive film comprises a plurality of conductive particles 26 of equal spherical diameter. Finally, as shown in FIG. 5H, the chip package structure 2 is pressed to the external circuit board 20, and at least the electrical particles 26 1A of the anisotropic conductive film 26 are electrically contacted with the external bumps. Block 231 to the connections 2 1 to achieve electrical interconnection of the chip package structure 2 and the external printed circuit 20. Therefore, as is apparent from the above manufacturing method, the imaginary step and the ball placing step can be omitted, and the entire wafer sealing process can be completed by performing the labeling and cutting steps after the molding step. In the present invention, the step of filling the holes replaces the conventional wire-drawing step and the ball-planting step, and there is a problem of conventional punching. The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above. However, the present invention has been disclosed by way of example, and is not intended to limit the present invention. 'Any simple modification, equivalent change, and modification within the technical scope of the present invention are still within the technical scope of the present invention. , $ [Simple description of the diagram] Figure 1: Schematic diagram of the conventional wafer package broadcast structure. Figure 2 is a cross-sectional view showing a cross-sectionally stretched wafer package broadcast structure in accordance with the present invention. Brushing 260 Referring to the steps of printing a conductive pad, the invention can be connected to the invention that is not familiar to the invention. 19 201017855 FIG. 3 is a schematic diagram of the upper surface of the substrate of the wafer package structure according to an embodiment of the present invention. . Figure 4 is a schematic view of the lower surface of a substrate in accordance with a wafer package structure in accordance with an embodiment of the present invention. 5A and 5H are views showing a cross-sectional view of an element in a process and a cross-sectional view of the wafer package structure bonded to an external printed circuit board in accordance with an embodiment of the present invention. [Main component symbol description] 10 Lower mold 11 Positioning groove 12 Pocket 20 External printed circuit board 21 Connection pad 100 Chip package structure 110 Substrate 111 Upper surface 112 Lower surface 113 Plated through hole 114 Internal finger 115 External pad 120 Wafer 121 Solder Pad 140 Sealant 150 Bonding layer 170 Bonding wire 180 Solder ball 200 矽 Perforation extending extending chip package structure 210 Substrate 211 Upper surface 212 Lower surface 213 Substrate via 214 Retaining ring 215 Bump bearing 216 Faux pad 220 Wafer 221矽Perforation 230 Conductive filler 231 External bump 232 End 240 Sealant 250 Bonded layer 260 Anisotropic conductive film 261 Conductive particles 20 201017855 261A Conductive particles❹

21twenty one

Claims (1)

201017855 十、申請專利範圍： 1、一種矽穿孔連通延伸之晶片封裝構造包含： 基板，係具有一上表面、一下表面以及複數個基 板通孔； —晶片，係設置於該基板之該上表面，該晶片係具 有複數個矽穿孔，該些矽穿孔與該些基板通孔係為 縱向對應連通；201017855 X. Patent application scope: 1. A wafer package structure in which a crucible is connected and extended includes: a substrate having an upper surface, a lower surface, and a plurality of substrate via holes; and a wafer disposed on the upper surface of the substrate, The wafer has a plurality of turns of perforations, and the through holes are in longitudinal correspondence with the through holes of the substrate; 複數個導電填充材，係以液態填充方式形成於該些 石夕穿孔與該些基板通孔中’該些導電填充材更突出 於該基板之該下表面成為複數個孔對孔一體 連接之外接凸塊；以及 2、 —封膠體’係形成於該基板 晶片。 之該上表面 以密封該a plurality of conductive fillers are formed in the liquid-filled manner in the through-holes and the through-holes of the substrate. The conductive fillers protrude from the lower surface of the substrate to form a plurality of holes and are integrally connected to the holes. a bump; and 2, an encapsulant is formed on the substrate wafer. The upper surface to seal the 如申請專利範圍第1項所述之 中該些導電填充材係為内含金 脂0 晶片封裝構造，其 屬粒子的熱固性樹 思之晶片封裝構造，其 中該些導電填充材係由金屬膏繞結成形。 述之晶片封裝構造’其 端部係形成為複數個大 22 5、 201017855 6、 如申請專利範圍第1項所述之晶#封裝構造’ ' 中該些導電填充材之液態填充方式孫包含模封^ n ，fj 7、 如申請專利範圍第J項所述之晶片封裝構造 包含一黏晶層，係形成於該晶片與該基板之間’ 且該基板係設有複數個位在該上表面之擋環’， 環繞該些基板通孔在該上表面之開口 ’用以陴释 黏晶層流入該些基板通孔。As described in the first paragraph of the patent application, the conductive filler is a gold-filled 0 wafer package structure, which belongs to a chip thermosetting chip package structure, wherein the conductive filler is wound by a metal paste. The knot is formed. The wafer package structure described in the 'the end portion is formed into a plurality of large 22 5, 201017855 6 , as described in the patent application scope 1 of the crystal # package construction ' ' in the liquid filling method of the conductive filler material The chip package structure of claim J includes a die bond layer formed between the wafer and the substrate and the substrate is provided with a plurality of bits on the upper surface. The retaining ring' surrounds the opening of the substrate through hole at the upper surface to relieve the flow of the adhesive layer into the substrate through holes. 8、 如申請專利範圍第1項所述之晶片封裝構造’ ' 中該基板係設有複數個位在該下表面之凸塊承 座’其係環繞該些基板通孔在該下表面之開口’ 些導電填充材之該些外接凸塊係結合於該些凸槐 承座。 9、 如申請專利範圍第1項所述之晶片封裝構造，另 包含一異方性導電膠膜，係形成於該基板之該下表 面並覆蓋該些外接凸塊。 10、 如申請專利範圍第9項所述之晶片封裝構造，其 中該異方性導電膠膜係包含複數個等球徑的導電 顆粒’其中至少一導電顆粒係電性接觸該些外接凸 塊至一外部印刷電路板’其中所述電性接觸之導電 顆粒係局部欲陷於該些導電填充材之對應外接凸 塊内。 H、如申請專利範圍第1項所述之晶片封裝構造，其 中該基板之該上表面係具有一接近該晶片之表面 覆蓋區之面積。 23 201017855 1 2、一種矽穿孔連通延伸之晶片封裝構造，主 一基板、一設於該基板上之晶片以及複數個 該基板下之外接凸塊，其特徵在於，該些外 係由導電填充材所形成並貫穿該基板與該J 形成複數個外露在該晶片之端部。 1 3、如申請專利範圍第1 2項所述之晶片封裝 另包含有一封膠體，係形成於該基板設有該 一表面，以密封該晶片並覆蓋該些端部。 要包含 突出於 接凸塊 I片’以 構造， 晶片之 248. The wafer package structure of claim 1, wherein the substrate is provided with a plurality of bump receptacles on the lower surface that surround the substrate vias at the lower surface. The lenticular bumps of the conductive filler are bonded to the tenon sockets. 9. The wafer package structure of claim 1, further comprising an anisotropic conductive film formed on the lower surface of the substrate and covering the external bumps. 10. The wafer package structure of claim 9, wherein the anisotropic conductive film comprises a plurality of conductive particles of equal spherical diameter, wherein at least one of the conductive particles electrically contacts the external bumps to An external printed circuit board in which the electrically conductive conductive particles are locally trapped in corresponding embossed bumps of the conductive filler. The wafer package structure of claim 1, wherein the upper surface of the substrate has an area close to a surface coverage area of the wafer. 23 201017855 1 2. A chip package structure in which a perforated via extends and extends, a main substrate, a wafer disposed on the substrate, and a plurality of external bumps under the substrate, wherein the external portions are made of conductive filler A plurality of portions formed and penetrated through the substrate and the J are exposed at the end of the wafer. The wafer package of claim 12, further comprising a gel formed on the substrate to seal the wafer and cover the ends. To include the protrusions of the bumps I to construct, the chip 24
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TWI453420B (en) * 2013-01-11 2014-09-21 Mpi Corp Perforated plate
TWI482240B (en) * 2011-12-19 2015-04-21 Nat Univ Tsing Hua A method for fabricating interconnects in through-semiconductor-via
TWI496268B (en) * 2010-08-31 2015-08-11 Micron Technology Inc Buffer die in stacks of memory dies and methods
US9470715B2 (en) 2013-01-11 2016-10-18 Mpi Corporation Probe head
TWI741331B (en) * 2019-06-13 2021-10-01 南亞科技股份有限公司 Semiconductor structure and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
WO2006124597A2 (en) * 2005-05-12 2006-11-23 Foster Ron B Infinitely stackable interconnect device and method
US8586465B2 (en) * 2007-06-07 2013-11-19 United Test And Assembly Center Ltd Through silicon via dies and packages
KR100871381B1 (en) * 2007-06-20 2008-12-02 주식회사 하이닉스반도체 Through silicon via chip stack package

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Publication number Priority date Publication date Assignee Title
TWI496268B (en) * 2010-08-31 2015-08-11 Micron Technology Inc Buffer die in stacks of memory dies and methods
US9691444B2 (en) 2010-08-31 2017-06-27 Micron Technology, Inc. Buffer die in stacks of memory dies and methods
TWI482240B (en) * 2011-12-19 2015-04-21 Nat Univ Tsing Hua A method for fabricating interconnects in through-semiconductor-via
TWI453420B (en) * 2013-01-11 2014-09-21 Mpi Corp Perforated plate
US9470715B2 (en) 2013-01-11 2016-10-18 Mpi Corporation Probe head
TWI741331B (en) * 2019-06-13 2021-10-01 南亞科技股份有限公司 Semiconductor structure and method of manufacturing the same
US11183443B2 (en) 2019-06-13 2021-11-23 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same
US11721610B2 (en) 2019-06-13 2023-08-08 Nanya Technology Corporation Method for manufacturing semiconductor structure same

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