KR20050119414A - Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same - Google Patents

Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same Download PDF

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Publication number
KR20050119414A
KR20050119414A KR1020040044496A KR20040044496A KR20050119414A KR 20050119414 A KR20050119414 A KR 20050119414A KR 1020040044496 A KR1020040044496 A KR 1020040044496A KR 20040044496 A KR20040044496 A KR 20040044496A KR 20050119414 A KR20050119414 A KR 20050119414A
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South Korea
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semiconductor chip
package substrate
package
edge
adhesive layer
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KR1020040044496A
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Korean (ko)
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이택훈
김길백
정용진
장환영
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삼성전자주식회사
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Priority to KR1020040044496A priority Critical patent/KR20050119414A/en
Publication of KR20050119414A publication Critical patent/KR20050119414A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

2개의 에지 패드형 반도체 칩을 포함하는 스택 패키지 및 그 제조방법에 대하여 개시한다. 본 발명의 일 실시예에 따른 스택 패키지는 패키지용 기판, 제1 및 제2 반도체 칩, 제1 및 제2 접착제층, 다수의 본딩 와이어 및 봉지용 수지를 포함하는데, 패키지용 기판은 그것을 관통하는 한 쌍의 윈도우 채널이 서로 평행하게 양측 가장자리에 형성되어 있으며, 밑면에는 다수의 연결 패드 및 다수의 접속 패드를 구비한다. 그리고, 패키지용 기판의 상면에는 제1 접착제층, 제1 반도체 칩, 제2 접착제층 및 제2 반도체 칩이 순차적으로 접착되어 있다. 또한, 본딩 와이어가 윈도우 채널을 통하여 패키지용 기판과 제1 및 제2 반도체 칩을 전기적으로 연결하도록 구성되어 있다.A stack package including two edge pad type semiconductor chips and a method of manufacturing the same are described. A stack package according to an embodiment of the present invention includes a substrate for a package, first and second semiconductor chips, first and second adhesive layers, a plurality of bonding wires, and a resin for encapsulation, wherein the package substrate passes through A pair of window channels are formed at both edges in parallel with each other, and the bottom surface includes a plurality of connection pads and a plurality of connection pads. The first adhesive layer, the first semiconductor chip, the second adhesive layer, and the second semiconductor chip are sequentially bonded to the upper surface of the package substrate. In addition, the bonding wire is configured to electrically connect the package substrate and the first and second semiconductor chips through the window channel.

Description

에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법{Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same}Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same

본 발명은 반도체 패키지에 대한 것으로, 특히 2개의 에지 패드형 반도체 칩을 적층한 반도체 패키지 및 그 제조방법에 대한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which two edge pad type semiconductor chips are stacked and a manufacturing method thereof.

최근 반도체 패키지 분야에서는 각종의 반도체 칩을 적층함으로써, 고집적 및 다기능의 스택 패키지를 제조하려는 추세가 나타나고 있다. 스택 패키지의 일 예로서, 멀티 칩 패키지(Multi Chip Package, MCP), 듀얼 덴시티 패키지(Dual Density Package, DDP) 등이 있다.Recently, in the semiconductor package field, there is a trend to manufacture a highly integrated and multifunctional stack package by stacking various semiconductor chips. An example of a stack package includes a multi chip package (MCP), a dual density package (DDP), and the like.

도 1에는 종래 기술에 따른 2개의 에지 패드형 반도체 칩을 포함하는 스택 패키지(100)의 일 예가 도시되어 있다. 도 1을 참조하면, 스택 패키지(100)는 인쇄회로기판(Printed Circuit Board, PCB, 110) 상에 제1 반도체 칩(130)과 제2 반도체 칩(150)이 적층되어 있으며, 제1 및 제2 반도체 칩(130, 150)의 부착을 위하여 제1 접착제층(120) 및 제2 접착제층(140)을 사용한다. 그리고, 제1 및 제2 반도체 칩(130, 150)은 각각 본딩 와이어(132, 152)에 의하여 PCB 기판(110)과 전기적으로 연결되며, 제1 및 제2 반도체 칩(130, 150)과 제1 및 제2 본딩 와이어(132, 152)는 봉지용 수지(160)에 의하여 둘러쌓여 있다. 또한, PCB 기판(110)의 하부에는 다수의 솔더 볼(170)이 어레이되어 있다. 1 shows an example of a stack package 100 including two edge pad type semiconductor chips according to the prior art. Referring to FIG. 1, in the stack package 100, a first semiconductor chip 130 and a second semiconductor chip 150 are stacked on a printed circuit board (PCB) 110. 2 The first adhesive layer 120 and the second adhesive layer 140 are used to attach the semiconductor chips 130 and 150. In addition, the first and second semiconductor chips 130 and 150 are electrically connected to the PCB substrate 110 by bonding wires 132 and 152, respectively. The first and second bonding wires 132 and 152 are surrounded by the encapsulating resin 160. In addition, a plurality of solder balls 170 are arranged under the PCB substrate 110.

그런데, 종래의 스택 패키지(100)를 제조하기 위해서는 제1 접착제층(120)을 사용하여 제1 반도체 칩(130)을 패키지용 기판(110) 상에 부착한 다음에, 제1 본딩 와이어(132)를 연결한다. 그리고, 그 제1 반도체 칩(130) 상에 제2 반도체 칩(150)을 부착시킨다. 이 경우, 제2 반도체 칩(150)의 부착 과정에서 제1 본딩 와이어(132)에 손상을 초래할 수 있을 뿐만이 아니라 제2 접착제층(140)을 도포하기가 용이하지 않은 문제점이 있다. 또한, 제1 및 제2 본딩 와이어(132, 152)의 볼 넥(ball neck) 부근이 쉽게 끊기기 때문에, 와이어 본딩 공정에서 상대적으로 난이도가 높은 리버스 본딩(reverse bonding)을 해야하는 어려움이 있다.However, in order to manufacture the conventional stack package 100, the first semiconductor chip 130 is attached onto the package substrate 110 using the first adhesive layer 120 and then the first bonding wire 132. ). The second semiconductor chip 150 is attached to the first semiconductor chip 130. In this case, not only the first bonding wire 132 may be damaged in the process of attaching the second semiconductor chip 150, but there is a problem in that it is not easy to apply the second adhesive layer 140. In addition, since the vicinity of the ball neck of the first and second bonding wires 132 and 152 is easily broken, there is a difficulty in performing reverse bonding having a relatively high difficulty in the wire bonding process.

그리고 종래의 스택 패키지(100)는 제2 본딩 와이어(152)의 높이로 인하여 패키지의 높이를 낮게 하는데 한계가 있다. 뿐만이 아니라, 패키지의 두께가 얇아지는 추세에서 봉지용 수지(160)의 상면을 너무 낮게 만들면, 제1 및 제2 본딩 와이어(132, 152)에 의하여 갭(gap)이 충분히 확보되지 못할 수가 있다. 그 결과, 제1 및 제2 본딩 와이어(132, 152)에 의하여 봉지용 수지(160)의 흐름이 간섭을 받아서, 그 내부에 보이드 등이 유발되는 문제점이 있다.And the conventional stack package 100 has a limit to lower the height of the package due to the height of the second bonding wire 152. In addition, if the top surface of the encapsulating resin 160 is made too low in a trend that the thickness of the package becomes thin, the gap may not be sufficiently secured by the first and second bonding wires 132 and 152. As a result, the flow of the encapsulating resin 160 is interrupted by the first and second bonding wires 132 and 152, thereby causing voids or the like.

본 발명이 이루고자 하는 기술적 과제는 본딩 와이어에 손상이 생기는 것을 방지할 수 있고, 봉지용 수지 내부에 보이드가 유발되는 것을 방지할 수 있는 스택 패키지 및 그 제조방법을 제공하는데 있다.The technical problem to be achieved by the present invention is to provide a stack package and a method of manufacturing the same, which can prevent the bonding wire from being damaged and prevent the voids from occurring in the sealing resin.

본 발명이 이루고자 하는 다른 기술적 과제는 패키지의 두께를 보다 얇게 만들 수 있을 뿐만이 아니라 반도체 칩과 패키지용 기판의 접착성을 향상시킬 수 있는 스택 패키지 및 그 제조방법을 제공하는데 있다.Another technical problem to be achieved by the present invention is to provide a stack package and a method of manufacturing the same, which can not only make the thickness of the package thinner but also improve the adhesion between the semiconductor chip and the package substrate.

상기한 기술적 과제들을 달성하기 위한 본 발명에 따른 스택 패키지는 2개의 에지 패드형 반도체 칩을 보더 온 칩(Board On Chip, BOC) 타입으로 적층한 멀티 칩 패키지이다. 본 발명의 일 실시예에 의하면, 스택 패키지는 패키지용 기판, 다수의 솔더 볼, 제1 접착제층, 제1 반도체 칩, 제2 접착제층, 제2 반도체 칩, 다수의 본딩 와이어 및 봉지용 수지를 포함한다. 상기 패키지용 기판은 장방형으로서, 상기 패키지용 기판을 관통하는 한 쌍의 윈도우 채널이 서로 평행하게 양측 가장자리에 형성되어 있으며, 상기 한 쌍의 윈도우 채널에 인접한 상기 패키지용 기판의 밑면에 형성되어 있는 다수의 연결 패드 및 상기 패키지용 기판의 밑면에 어레이되어 있는 다수의 접속 패드를 구비하고 있다. 그리고, 상기 다수의 솔더 볼은 상기 다수의 접속 패드 상에 부착되어 있다. 그리고, 상기 제1 접착제층은 상기 한 쌍의 윈도우 채널 사이의 상기 패키지용 기판 상면에 도포되어 있다. 그리고, 상기 제1 반도체 칩은 다수의 제1 에지 패드가 아래를 향하도록 상기 제1 접착제층 상에 부착되어 있다. 그리고, 상기 제2 접착제층은 상기 제1 반도체 칩의 상기 에지 패드 형성면의 반대쪽 면 상에 도포되어 있다. 그리고, 상기 제2 반도체 칩은 다수의 제2 에지 패드가 아래를 향하도록 상기 제2 접착제층 상에 부착되어 있다. 그리고, 상기 다수의 본딩 와이어는 상기 다수의 제1 에지 패드 및 상기 다수의 제2 에지 패드 각각을 상기 다수의 연결 패드 각각과 전기적으로 연결한다. 그리고, 상기 봉지용 수지는 상기 윈도우 채널을 충진하며 상기 제1 반도체 칩 및 상기 제2 반도체 칩을 둘러싸도록 형성되어 있다.A stack package according to the present invention for achieving the above technical problem is a multi-chip package in which two edge pad type semiconductor chips are stacked in a board on chip (BOC) type. According to an embodiment of the present invention, a stack package includes a substrate for a package, a plurality of solder balls, a first adhesive layer, a first semiconductor chip, a second adhesive layer, a second semiconductor chip, a plurality of bonding wires, and a resin for encapsulation. Include. The package substrate is rectangular, and a pair of window channels penetrating the package substrate are formed at both edges in parallel to each other, and a plurality of window channels formed on the bottom surface of the package substrate adjacent to the pair of window channels. Connection pads and a plurality of connection pads arranged on the bottom surface of the package substrate. The plurality of solder balls are attached onto the plurality of connection pads. The first adhesive layer is applied to the upper surface of the package substrate between the pair of window channels. The first semiconductor chip is attached on the first adhesive layer such that the plurality of first edge pads face downward. The second adhesive layer is applied on the surface opposite to the edge pad forming surface of the first semiconductor chip. The second semiconductor chip is attached on the second adhesive layer such that a plurality of second edge pads face downward. The plurality of bonding wires electrically connect each of the plurality of first edge pads and the plurality of second edge pads with each of the plurality of connection pads. The encapsulating resin is formed to fill the window channel and surround the first semiconductor chip and the second semiconductor chip.

상기한 본 발명의 일 실시예에 따른 스택 패키지의 제조방법은 먼저, 장방형 패키지용 기판으로서, 상기 패키지용 기판을 관통하는 한 쌍의 윈도우 채널이 서로 평행하게 양측 가장자리에 형성되어 있으며, 상기 한 쌍의 윈도우 채널에 인접한 상기 패키지용 기판의 밑면에 형성되어 있는 다수의 연결 패드 및 상기 패키지용 기판의 밑면에 어레이되어 있는 다수의 접속 패드를 구비한 패키지용 기판을 준비한다. 그리고, 상기 한 쌍의 윈도우 채널 사이의 상기 패키지용 기판 상에 제1 접착제층을 도포한다. 그리고, 다수의 제1 에지 패드가 아래를 향하도록 상기 제1 접착제층 상에 제1 반도체 칩을 부착한다. 그리고, 상기 제1 반도체 칩의 상기 에지 패드 형성면의 반대쪽 면 상에 제2 접착제층을 도포한다. 그리고, 다수의 제2 에지 패드가 아래를 향하도록 상기 제2 접착제층 상에 제2 반도체 칩을 부착한다. 그리고, 상기 다수의 제1 에지 패드 및 상기 다수의 제2 에지 패드 각각을 상기 다수의 연결 패드 각각과 전기적으로 연결하도록 와이어 본딩한다. 그리고, 상기 윈도우 채널을 충진하며 상기 제1 반도체 칩 및 상기 제2 반도체 칩을 둘러싸도록 봉지용 수지를 윈도우 몰딩하고, 마지막으로 상기 다수의 접속 패드 상에 다수의 솔더 볼을 형성한다.In the method of manufacturing a stack package according to the embodiment of the present invention, first, as a rectangular package substrate, a pair of window channels passing through the package substrate are formed at both edges in parallel to each other, and the pair A substrate for a package having a plurality of connection pads formed on the bottom surface of the package substrate adjacent to the window channel and a plurality of connection pads arranged on the bottom surface of the package substrate is prepared. Then, a first adhesive layer is coated on the package substrate between the pair of window channels. Then, a first semiconductor chip is attached onto the first adhesive layer so that the plurality of first edge pads face downward. Then, a second adhesive layer is applied on the surface opposite to the edge pad forming surface of the first semiconductor chip. Then, a second semiconductor chip is attached onto the second adhesive layer so that the plurality of second edge pads face downward. The plurality of first edge pads and the plurality of second edge pads are wire-bonded to electrically connect with each of the plurality of connection pads. The encapsulating resin is window molded to fill the window channel and surround the first semiconductor chip and the second semiconductor chip, and finally, a plurality of solder balls are formed on the plurality of connection pads.

기타 실시예들의 구체적인 사항들은 상세한 설명 및 도면들에 포함되어 있다.Specific details of other embodiments are included in the detailed description and the drawings.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세하게 설명하기로 한다. 그러나, 본 발명은 여기서 설명되어지는 실시예들에 한정되지 않고 다른 형태로 구체화될 수 있다. 오히려 여기서 소개되는 실시예들은 본 발명의 기술적 사상이 철저하고 완전하게 개시될 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위하여 예시적으로 제공되어지는 것들이다. 도면에 있어서, 층의 두께 및/또는 영역들의 크기 등은 명확성을 기하기 위하여 과장되어진 것이다. 명세서 전체에 걸쳐서 동일한 참조 번호는 동일한 구성요소를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided by way of example so that the technical spirit of the present invention can be thoroughly and completely disclosed, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thickness of layers and / or the size of regions are exaggerated for clarity. Like numbers refer to like elements throughout.

도 2a에는 본 발명에 따른 스택 패키지(200, 도 7의 참조)에 포함되어 있는 패키지용 기판(210)에 대한 개략적인 평면도가 도시되어 있고, 도 2b에는 도 2a의 XX'라인을 따라 절취한 개략적인 단면도가 도시되어 있다. 본 발명에 따른 스택 패키지를 제조하기 위해서는 먼저 도시된 것과 같은 패키지용 기판(210)을 준비한다.FIG. 2A is a schematic plan view of a package substrate 210 included in a stack package 200 (see FIG. 7) according to the present invention, and FIG. 2B is cut along the line XX ′ of FIG. 2A. A schematic cross section is shown. In order to manufacture the stack package according to the present invention, a package substrate 210 as shown in the drawing is first prepared.

도 2a 및 도 2b를 참조하면, 장방형의 패키지용 기판(210)은 인쇄회로기판, FR4 기판 또는 폴리이미드 기판일 수 있는데, 본 실시예에서는 인쇄회로기판인 경우에 대해서 설명한다. 패키지용 기판(210)의 내부에는 다수의 배선이 형성되어 있다. 그리고, 패키지용 기판(210)의 중앙부에는 반도체 칩이 부착될 칩 영역이 한정되어 있으며, 한 쌍의 윈도우 채널(212)이 상기 패키지용 기판(210)을 관통하도록 서로 나란하게 형성되어 있다. 윈도우 채널(212)은 본딩 와이어가 통과하는 통로로서의 역할을 한다.2A and 2B, the rectangular package substrate 210 may be a printed circuit board, an FR4 substrate, or a polyimide substrate. In this embodiment, a case of a printed circuit board will be described. A plurality of wires are formed in the package substrate 210. In addition, a chip region to which a semiconductor chip is attached is defined at a central portion of the package substrate 210, and a pair of window channels 212 are formed to be parallel to each other so as to pass through the package substrate 210. The window channel 212 serves as a passage through which the bonding wire passes.

그리고, 패키지용 기판(210)의 밑면에는 다수의 연결 패드(214) 및 다수의 접속 패드(216)가 구비되어 있다. 다수의 연결 패드(214)는 본딩 와이어와 연결되는 도전 패드로서, 윈도우 채널(212)에 인접한 곳에 양쪽으로 위치한다. 그리고, 다수의 접속 패드(216)는 솔더 볼이 접착될 도전 패드로서, 패키지용 기판(210)의 전면에 어레이되어 있다.In addition, a plurality of connection pads 214 and a plurality of connection pads 216 are provided on the bottom surface of the package substrate 210. The plurality of connection pads 214 are conductive pads connected to the bonding wires and are positioned at both sides adjacent to the window channel 212. In addition, the plurality of connection pads 216 are conductive pads to which solder balls are bonded, and are arranged on the entire surface of the package substrate 210.

도 3을 참조하면, 먼저 패키지용 기판(210)의 상면에 제1 접착제층(220)을 도포한다. 제1 접착제층(220)은 도 2a의 칩 영역 내부에 도포한다. 제1 접착제층(220)은 절연성 접착제로서 이 분야의 통상적인 접착용 물질을 사용하여 형성한다. 그리고, 제1 접착제층(220) 상에 제1 반도체 칩(230)을 부착한다. 제1 반도체 칩(230)은 에지 패드형으로서, 다수의 제1 본딩 패드(234)가 제1 반도체 칩의 가장자리에 배열되어 있다. 제1 반도체 칩(230)은 제1 본딩 패드(234)가 형성되어 있는 면이 패키지용 기판(210)을 향하도록 플립 칩 방식으로 부착한다. Referring to FIG. 3, first, the first adhesive layer 220 is coated on the upper surface of the package substrate 210. The first adhesive layer 220 is applied inside the chip region of FIG. 2A. The first adhesive layer 220 is formed using an adhesive material conventional in the art as an insulating adhesive. The first semiconductor chip 230 is attached to the first adhesive layer 220. The first semiconductor chip 230 is an edge pad type, and a plurality of first bonding pads 234 are arranged at the edge of the first semiconductor chip. The first semiconductor chip 230 is attached in a flip chip manner so that the surface on which the first bonding pad 234 is formed faces the package substrate 210.

도 4를 참조하면, 제1 반도체 칩(230)의 뒷면에 제2 접착제층(240)을 도포한다. 제2 접착제층(240)은 제1 접착제층(220)과 동일한 물질로 형성하는 것이 바람직하지만, 다른 절연성 접착 물질을 사용하여 형성할 수도 있다. 그리고, 제2 접착제층(240) 상에 제2 반도체 칩(250)을 부착한다. 제2 반도체 칩(250)은 제1 반도체 칩(230)과 동일하게 에지 패드형으로서, 다수의 제2 본딩 패드(254)가 제2 반도체 칩의 가장자리에 배열되어 잇다. 그러나, 제2 반도체 칩(250)은 제 1 반도체 칩(230)과 동일한 종류의 반도체 칩일 필요는 없다. 오히려, 본 발명은 크기 및 특성이 서로 다른 2개의 반도체 칩을 적층하는 스택 패키지에 더욱 적합하다. 제2 반도체 칩(250)도 제2 본딩 패드(254)가 형성되어 있는 면이 패키지용 기판(210)을 향하도록 플립 칩 방식으로 부착한다.Referring to FIG. 4, a second adhesive layer 240 is coated on the back side of the first semiconductor chip 230. The second adhesive layer 240 is preferably formed of the same material as the first adhesive layer 220, but may be formed using another insulating adhesive material. The second semiconductor chip 250 is attached onto the second adhesive layer 240. The second semiconductor chip 250 is an edge pad type like the first semiconductor chip 230, and a plurality of second bonding pads 254 are arranged at the edge of the second semiconductor chip. However, the second semiconductor chip 250 need not be the same kind of semiconductor chip as the first semiconductor chip 230. Rather, the present invention is more suitable for a stack package in which two semiconductor chips having different sizes and characteristics are stacked. The second semiconductor chip 250 is also attached in a flip chip manner so that the surface on which the second bonding pad 254 is formed faces the package substrate 210.

도 5를 참조하면, 다수의 제1 및 제2 본딩 패드(234, 254)와 다수의 연결 패드(214)를 전기적으로 연결하는 와이어 본딩 공정을 실시한다. 상기 와이어 본딩 공정은, BOC 패키지 제조 공정에서 사용하는 와이어 본딩 공정을 사용하면, 용이하게 실시할 수 있다. 와이어 본딩 공정은 금(Au) 등의 도전성 금속을 사용하는데, 그 결과 다수의 패키지용 기판(210)의 윈도우 채널(212)을 관통하는 본딩 와이어(232, 253)가 만들어진다. 본 실시예에서는, 본딩 와이어(232, 253) 형성 공정을 제2 반도체 칩(250)의 부착 공정 후에 실시하기 때문에, 종래와 같은 제2 반도체 칩의 부착 과정에서 생길 수 있는 본딩 와이어의 손상을 방지할 수가 있다. 그리고, 본딩 와이어(232, 252)가 윈도우 채널을 관통하기 때문에 전체 패키지의 두께를 낮출 수가 있다. Referring to FIG. 5, a wire bonding process for electrically connecting a plurality of first and second bonding pads 234 and 254 and a plurality of connection pads 214 is performed. The wire bonding step can be easily performed using a wire bonding step used in a BOC package manufacturing step. The wire bonding process uses a conductive metal such as gold (Au), and as a result, bonding wires 232 and 253 are formed through the window channels 212 of the plurality of package substrates 210. In the present embodiment, the bonding wires 232 and 253 are formed after the second semiconductor chip 250 is attached, thereby preventing damage to the bonding wires that may occur during the attachment process of the second semiconductor chip. You can do it. Since the bonding wires 232 and 252 pass through the window channel, the thickness of the entire package can be reduced.

도 6을 참조하면, 상기 결과물에 대하여 몰딩 공정을 실시한다. 몰딩 공정은 에폭시 수지 등의 봉지용 수지(260)를 사용하여, 반도체 칩 및 본딩 와이어를 봉지하는 공정이다. 몰딩 공정에서는 패키지용 기판(210)의 1쌍의 윈도우 채널(212)을 통하여 윈도우 몰딩법으로 수행한다. 도 6을 참조하면 알 수 있는 바와 같이, 본 실시예에서는 본딩 와이어(232, 252)가 봉지용 수지(260)의 상면 높이까지는 위치하지 않기 때문에, 종래와 같은 보이드 발생 등의 문제가 생기지 않는다. Referring to FIG. 6, a molding process is performed on the resultant product. A molding process is a process of sealing a semiconductor chip and a bonding wire using resin 260 for sealing, such as an epoxy resin. In the molding process, the window molding method is performed through the pair of window channels 212 of the package substrate 210. As can be seen with reference to FIG. 6, in this embodiment, since the bonding wires 232 and 252 are not located up to the upper surface height of the sealing resin 260, there is no problem such as generation of voids as in the prior art.

그리고, 봉지용 수지(260)는 패키지용 기판(210)과 제1 및 제2 반도체 칩(230, 250) 사이의 빈 공간에도 메워져 있다. 그 결과, 봉지용 수지(260)는 종래보다 패키지용 기판(210)과 제1 및 제2 반도체 칩(230, 250)과 더 큰 면적에서 접촉을 하게 되며, 봉지용 수지(260)에 의하여 제1 및 제2 반도체 칩(230, 250)의 접합력은 향상된다. 따라서, 본 실시예에 의하면 패키지의 신뢰도가 증가한다.The encapsulating resin 260 is also filled in the empty space between the package substrate 210 and the first and second semiconductor chips 230 and 250. As a result, the encapsulating resin 260 is in contact with the package substrate 210 and the first and second semiconductor chips 230 and 250 in a larger area than before, and the encapsulating resin 260 is formed by the encapsulating resin 260. Bonding force of the first and second semiconductor chips 230 and 250 is improved. Therefore, according to this embodiment, the reliability of the package is increased.

도 7을 참조하면, 이 분야의 통상적인 공정을 사용하여 접속 패드(216) 상에 다수의 솔더 볼(270)을 형성한다. 패키지용 기판(210)이 PCB가 아닌 폴리이미드 기판인 경우에는 상기 솔더 볼(27) 제조 공정은 불필요할 수도 있다. 솔더 볼(270)을 형성하고 나면, 도 7에 도시된 것과 같은 스택 패키지(200)가 완성된다.Referring to FIG. 7, a plurality of solder balls 270 are formed on the connection pads 216 using conventional processes in the art. When the package substrate 210 is a polyimide substrate instead of a PCB, the solder ball 27 manufacturing process may be unnecessary. After the solder balls 270 are formed, the stack package 200 as shown in FIG. 7 is completed.

본 발명에 의하면, 반도체 칩을 모두 접착시킨 다음에 와이어 본딩 공정을 실시하기 때문에 본딩 와이어에 손상이 생기는 것을 방지할 수 있다. 그리고, 본딩 와이어가 제2 반도체 칩보다 더 높이는 위치하지 않기 때문에, 몰딩 공정에서 봉지용 수지가 원활하게 흘러서 그 내부에 보이드가 유발되는 것을 방지할 수 있다. According to the present invention, since the wire bonding step is performed after all the semiconductor chips are bonded together, damage to the bonding wire can be prevented. And since the bonding wire is not located higher than the second semiconductor chip, it is possible to prevent the sealing resin from flowing smoothly in the molding process to cause voids therein.

뿐만 아니라, 본 발명에 의하면, 본딩 와이어를 윈도우 채널을 통하여 연결시키기 때문에 전체 패키지의 두께를 보다 얇게 만들 수 있고, 봉지용 수지의 접촉면을 증가시켜서 반도체 칩과 패키지용 기판의 접착성을 향상시킬 수 있다.In addition, according to the present invention, since the bonding wire is connected through the window channel, the thickness of the entire package can be made thinner, and the adhesion between the semiconductor chip and the package substrate can be improved by increasing the contact surface of the encapsulating resin. have.

도 1은 종래 기술에 따른 2개의 에지 패드형 반도체 칩을 포함하는 스택 패키지에 대한 개략적인 단면도이다.1 is a schematic cross-sectional view of a stack package including two edge pad type semiconductor chips according to the prior art.

도 2a는 본 발명에 따른 스택 패키지에 포함된 패키지용 기판에 대한 개략적인 평면도이다.2A is a schematic plan view of a substrate for a package included in a stack package according to the present invention.

도 2b는 도 2a의 XX'라인을 따라 절취한 개략적인 단면도이다.FIG. 2B is a schematic cross-sectional diagram cut along the line XX ′ of FIG. 2A.

도 3 내지 도 7은 본 발명에 따른 2개의 에지 패드형 반도체 칩을 포함하는 스택 패키지의 제조방법을 공정 순서에 따라 도시한 개략적인 단면도이다.3 to 7 are schematic cross-sectional views illustrating a method of manufacturing a stack package including two edge pad type semiconductor chips according to the present invention.

Claims (8)

장방형 패키지용 기판으로서, 상기 패키지용 기판을 관통하는 한 쌍의 윈도우 채널이 서로 평행하게 양측 가장자리에 형성되어 있으며, 상기 한 쌍의 윈도우 채널에 인접한 상기 패키지용 기판의 밑면에 형성되어 있는 다수의 연결 패드 및 상기 패키지용 기판의 밑면에 어레이되어 있는 다수의 접속 패드를 구비한 패키지용 기판;A rectangular package substrate, wherein a pair of window channels passing through the package substrate are formed at both edges in parallel to each other, and a plurality of connections formed on the bottom surface of the package substrate adjacent to the pair of window channels. A package substrate having a pad and a plurality of connection pads arranged on a bottom surface of the package substrate; 상기 다수의 접속 패드 상에 부착되어 있는 다수의 솔더 볼;A plurality of solder balls attached to the plurality of connection pads; 상기 한 쌍의 윈도우 채널 사이의 상기 패키지용 기판 상면에 도포되어 있는 제1 접착제층;A first adhesive layer applied to an upper surface of the package substrate between the pair of window channels; 다수의 제1 에지 패드가 아래를 향하도록 상기 제1 접착제층 상에 부착되어 있는 제1 반도체 칩;A first semiconductor chip attached on the first adhesive layer with a plurality of first edge pads facing downward; 상기 제1 반도체 칩의 상기 에지 패드 형성면의 반대쪽 면 상에 도포되어 있는 제2 접착제층;A second adhesive layer applied on an opposite side of the edge pad forming surface of the first semiconductor chip; 다수의 제2 에지 패드가 아래를 향하도록 상기 제2 접착제층 상에 부착되어 있는 제2 반도체 칩;A second semiconductor chip attached on the second adhesive layer with a plurality of second edge pads facing down; 상기 다수의 제1 에지 패드 및 상기 다수의 제2 에지 패드 각각을 상기 다수의 연결 패드 각각과 전기적으로 연결하는 다수의 본딩 와이어; 및A plurality of bonding wires electrically connecting each of the plurality of first edge pads and the plurality of second edge pads with each of the plurality of connection pads; And 상기 윈도우 채널을 충진하며 상기 제1 반도체 칩 및 상기 제2 반도체 칩을 둘러싸는 봉지용 수지를 포함하는 에지 패드형 반도체 칩의 스택 패키지.An edge pad type semiconductor chip stack package including an encapsulating resin filling the window channel and surrounding the first semiconductor chip and the second semiconductor chip. 제1항에 있어서,The method of claim 1, 상기 패키지용 기판은 인쇄회로기판(PCB), FR4 기판 또는 폴리이미드 기판인 것을 특징으로 하는 에지 패드형 반도체 칩의 스택 패키지.The package substrate is a stack package of an edge pad type semiconductor chip, characterized in that the printed circuit board (PCB), FR4 substrate or polyimide substrate. 제1항에 있어서,The method of claim 1, 상기 제1 반도체 칩과 상기 제2 반도체 칩은 서로 다른 종류의 반도체 칩이며, 상기 제2 반도체 칩이 상기 제1 반도체 칩보다 크기가 더 큰 것을 특징으로 하는 에지 패드형 반도체 칩의 스택 패키지.The first semiconductor chip and the second semiconductor chip is a different kind of semiconductor chip, wherein the second semiconductor chip is larger than the first semiconductor chip stack package of the edge pad type chip. 제1항에 있어서,The method of claim 1, 상기 봉지형 수지는 상기 제1 및 제2 반도체 칩의 본딩 패드 형성면과 상기 패키지용 기판의 상면 사이에 충진되어 있는 것을 특징으로 하는 에지 패드형 반도체 칩의 스택 패키지.And the encapsulating resin is filled between the bonding pad forming surfaces of the first and second semiconductor chips and the upper surface of the package substrate. 장방형 패키지용 기판으로서, 상기 패키지용 기판을 관통하는 한 쌍의 윈도우 채널이 서로 평행하게 양측 가장자리에 형성되어 있으며, 상기 한 쌍의 윈도우 채널에 인접한 상기 패키지용 기판의 밑면에 형성되어 있는 다수의 연결 패드 및 상기 패키지용 기판의 밑면에 어레이되어 있는 다수의 접속 패드를 구비한 패키지용 기판을 준비하는 단계;A rectangular package substrate, wherein a pair of window channels passing through the package substrate are formed at both edges in parallel to each other, and a plurality of connections formed on the bottom surface of the package substrate adjacent to the pair of window channels. Preparing a package substrate having a pad and a plurality of connection pads arranged on a bottom surface of the package substrate; 상기 한 쌍의 윈도우 채널 사이의 상기 패키지용 기판 상에 제1 접착제층을 도포하는 단계;Applying a first adhesive layer on the package substrate between the pair of window channels; 다수의 제1 에지 패드가 아래를 향하도록 상기 제1 접착제층 상에 제1 반도체 칩을 부착하는 단계;Attaching a first semiconductor chip on the first adhesive layer with a plurality of first edge pads facing down; 상기 제1 반도체 칩의 상기 에지 패드 형성면의 반대쪽 면 상에 제2 접착제층을 도포하는 단계;Applying a second adhesive layer on a surface opposite to the edge pad forming surface of the first semiconductor chip; 다수의 제2 에지 패드가 아래를 향하도록 상기 제2 접착제층 상에 제2 반도체 칩을 부착하는 단계;Attaching a second semiconductor chip on the second adhesive layer with a plurality of second edge pads facing down; 상기 다수의 제1 에지 패드 및 상기 다수의 제2 에지 패드 각각을 상기 다수의 연결 패드 각각과 전기적으로 연결하도록 와이어 본딩하는 단계; Wire bonding each of the plurality of first edge pads and the plurality of second edge pads to electrically connect with each of the plurality of connection pads; 상기 윈도우 채널을 충진하며 상기 제1 반도체 칩 및 상기 제2 반도체 칩을 둘러싸도록 봉지용 수지를 윈도우 몰딩하는 단계; 및Window molding the encapsulating resin to fill the window channel and surround the first semiconductor chip and the second semiconductor chip; And 상기 다수의 접속 패드 상에 다수의 솔더 볼을 형성하는 단계를 포함하는 에지 패드형 반도체 칩의 스택 패키지 제조방법.A method of manufacturing a stack package of an edge pad type semiconductor chip comprising forming a plurality of solder balls on the plurality of connection pads. 제5항에 있어서,The method of claim 5, 상기 패키지용 기판은 인쇄회로기판(PCB), FR4 기판 또는 폴리이미드 기판인 것을 특징으로 하는 에지 패드형 반도체 칩의 스택 패키지의 제조방법.The package substrate is a method of manufacturing a stack package of an edge pad type semiconductor chip, characterized in that the printed circuit board (PCB), FR4 substrate or polyimide substrate. 제5항에 있어서,The method of claim 5, 상기 제1 반도체 칩과 상기 제2 반도체 칩은 서로 다른 종류의 반도체 칩이며, 상기 제2 반도체 칩이 상기 제1 반도체 칩보다 크기가 더 큰 것을 특징으로 하는 에지 패드형 반도체 칩의 스택 패키지 제조방법.The first semiconductor chip and the second semiconductor chip is a different type of semiconductor chip, the second semiconductor chip is a stack package manufacturing method of the edge pad type semiconductor chip, characterized in that the size is larger than the first semiconductor chip. . 제5항에 있어서,The method of claim 5, 상기 윈도우 몰딩 단계에서는 상기 봉지형 수지가 상기 제1 및 제2 반도체 칩의 본딩 패드 형성면과 상기 패키지용 기판의 상면 사이에 충진되도록 몰딩하는 것을 특징으로 하는 에지 패드형 반도체 칩의 스택 패키지의 제조방법.In the window molding step, the encapsulated resin is molded so as to be filled between the bonding pad forming surfaces of the first and second semiconductor chips and the upper surface of the package substrate. Way.
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