JP2010157544A - Semiconductor device, method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device prevented in development of a crack around a bump and therefore disconnection or short-circuiting of a circuit by dispersing stress applied to the bump, and improved in connection reliability when mounted on a mounting board. <P>SOLUTION: This semiconductor device 1 includes: a semiconductor substrate 10 with an electrode 2 formed on one surface thereof; a first insulation resin layer 11 arranged on the one surface of the semiconductor substrate and having a first opening 11a for exposing at least a part of the electrode; a conductive layer 12 arranged on the first insulation layer and electrically connected to the electrode through the first opening; a second insulation layer 13 arranged to cover the conductive layer and having a second opening 13a for exposing a part of the conductive layer; and a bump 14 arranged on the conductive layer exposed from the second opening. A region in contact with the bump within the conductive layer has a flat central region 12a and an outer region 12b forming a tilt, and the tilt has a negative angle toward the central region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which connection reliability is improved in a wafer level CSP, a manufacturing method thereof, and an electronic apparatus including the semiconductor device.

  BGA (Ball Grid Array) is a widely used semiconductor package structure in recent years. This has a structure in which electrodes called solder bumps are two-dimensionally arranged on the flat surface of the package, so it has a higher density than conventional DIP (Dual inline Package) and QFP (Quad Flat Package). Implementation is possible. For this reason, the BGA is used as a package for a computer CPU and memory. A conventional BGA type semiconductor package has a package size larger than the chip size. Among them, a package that is downsized to a size almost close to the chip size is called a CSP (chip size package). Contributes greatly to the reduction in size and weight.

  These BGA type packages are obtained by cutting a silicon wafer on which a circuit is formed and mounting the semiconductor chip on a mounting substrate called an interposer to complete the package. In addition to the need for a patterned interposer, In addition, a process of individually mounting the semiconductor chip on the interposer is necessary. For this reason, a dedicated material or manufacturing apparatus has to be used, and there is a drawback that the cost is increased.

  On the other hand, in a manufacturing method generally called “wafer level CSP”, for example, as shown in FIG. 8, an insulating layer 103, a rewiring layer 104, a sealing layer are formed on a silicon wafer 102 having an electrode 101 on one surface. A semiconductor chip 100 having a package structure can be obtained by forming 105, solder bumps 106, and the like, and cutting the wafer into predetermined chip dimensions in the final process. Since the package structure is collectively formed on the wafer, an interposer is not required as in the prior art, and since processing is performed in the wafer state, a dedicated device is not required. For this reason, the manufacturing efficiency is high, and the cost disadvantage is reduced. In addition, since the entire surface of the wafer is packaged and diced into individual pieces, the size of the chip itself becomes a semiconductor chip with a package, and has a minimum projected area with respect to the mounting substrate. A semiconductor chip can be obtained. Further, the wiring distance is shorter than that of the conventional package, and the parasitic capacitance of the wiring is also small. These excellent features are extremely advantageous in that high-density mounting and high-speed information processing can be realized, which are currently proceeding rapidly (Reference: Nikkei Microdevices February 2000 issue p42, 2000). March issue p121, April 2000 issue p114).

  However, a semiconductor package mounted on a mounting substrate is not only subjected to stress due to mechanical strain from the outside such as impact and vibration, but also receives thermal stress generated due to a difference in thermal expansion coefficient between the semiconductor package and the mounting substrate. In a semiconductor package such as a wafer level CSP in which a mounting substrate and a semiconductor chip are electrically and mechanically connected via solder bumps, stress is most likely to be concentrated at the joint portion of the solder bumps. For this reason, problems such as cracks and peeling are likely to occur in the solder bumps and the vicinity thereof, and finally, there arises a problem that the device becomes inoperable due to disconnection or short circuit of the circuit.

In order to prevent such problems, attempts have been made to suppress the occurrence of bump cracks by the following methods.
A structure in which the outside of the bump is covered with resin or the like (for example, see Patent Document 1)
A structure having a bump that encloses a core (see, for example, Patent Document 2 and Patent Document 3)
However, it is difficult for the former to form the resin layer uniformly on the entire surface of the wafer, and in order to mount it on the substrate, it is necessary to remove a part of the resin layer and expose the bumps. In the latter case, bumps must be formed on the core, which is not easy.
JP 2006-060219 A JP 2006-245290 A JP 2005-29483 A

The present invention has been devised in view of such a conventional situation, and by dispersing the stress applied to the bump, the progress of cracks and delamination around the bump, and thus the disconnection and short circuit of the circuit, are prevented. A first object is to provide a semiconductor device with improved connection reliability when mounted on a mounting substrate.
In addition, the present invention can disperse the stress applied to the bumps, prevent cracks and the progress of peeling around the bumps, and thus prevent disconnection and short-circuiting of the circuit, thereby improving connection reliability when mounted on a mounting board. It is a second object of the present invention to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device at a low cost by a simple process.
A third object of the present invention is to provide an electronic device excellent in connection reliability of a semiconductor device mounted on a mounting substrate.

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having an electrode formed on one surface; and a first opening disposed on one surface of the semiconductor substrate and exposing at least a part of the electrode. An insulating resin layer, a conductive layer disposed on the first insulating resin layer and electrically connected to the electrode through the first opening, and disposed to cover the conductive layer, A second insulating resin layer having a second opening that exposes at least a portion thereof, and a bump disposed on the conductive layer exposed from the second opening, wherein the bump of the conductive layer The region in contact with the center region is composed of a flat central region and an outer region having an inclination, and the inclination has a negative angle toward the central region.
A semiconductor device according to a second aspect of the present invention is characterized in that, in the first aspect, a convex portion is arranged on the semiconductor substrate or the first insulating resin layer so as to correspond to the inclination.
According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the end portion of the conductive layer is in a position not exceeding the upper surface at a position farther from the electrode of the convex portion. And
According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, the convex portion has a substantially ring shape when viewed in plan.
A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the second or third aspect, wherein the convex portion has a substantially ring shape when viewed in plan, and the central portion of the bump and the central portion of the semiconductor substrate. It is characterized by comprising two or more structures arranged extending in a direction substantially perpendicular to the direction connecting the two.
The semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the second to fifth aspects, in which the convex portion is more Young than a material forming the first insulating resin layer and / or the second insulating resin layer. It is characterized by comprising a material with a low rate.
According to a seventh aspect of the present invention, there is provided a semiconductor device manufacturing method, comprising: a semiconductor substrate having an electrode formed on one surface; and a first opening that is disposed on one surface of the semiconductor substrate and exposes at least a part of the electrode. A first insulating resin layer, a conductive layer disposed on the first insulating resin layer and electrically connected to the electrode through the first opening, and disposed to cover the conductive layer, At least a second insulating resin layer having a second opening that exposes at least a part of the conductive layer, and a bump disposed on the conductive layer exposed from the second opening. The region in contact with the bump is composed of a flat central region and an outer region having an inclination, and the inclination is a method for manufacturing a semiconductor device having a negative angle toward the central region. , Laser processing, or RIE There are, the semiconductor substrate or said first insulating resin layer, and forming a protrusion in correspondence with the slope.
An electronic device according to an eighth aspect of the present invention includes the semiconductor device according to any one of the first to sixth aspects.

In the present invention, a region of the conductive layer that is in contact with the bump includes a flat central region and an outer region that is inclined, and the inclination has a negative angle toward the central region. Therefore, the conductive layer can be easily deformed in the outer region (inclined portion), and the stress applied to the bump can be dispersed. As a result, the progress of cracks and peeling around the bumps, and hence the disconnection and short circuit of the circuit can be prevented. As a result, the present invention can provide a semiconductor device with improved connection reliability when mounted on a mounting board.
In the present invention, the projection is formed on the semiconductor substrate or the first insulating resin layer in correspondence with the inclination by using photolithography, laser processing, or RIE. In the semiconductor device thus obtained, a region in contact with the bump in the conductive layer is composed of a flat central region and an outer region having an inclination, and the inclination is negative toward the central region. It will have an angle. Since the conductive layer can be easily deformed in the outer region (inclined portion), the stress applied to the bumps can be dispersed. Thereby, the progress of cracks and delamination around the bumps, and the disconnection and short circuit of the circuit can be prevented. As a result, according to the present invention, it is possible to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device with improved connection reliability when mounted on a mounting substrate at a low cost by a simple process.
Further, according to the present invention, since a semiconductor device that can prevent circuit disconnection or short circuit and has excellent connection reliability when mounted on a mounting board is provided, an electronic device having excellent reliability is provided. Can do.

  Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view schematically showing one structural example of the semiconductor device of the present invention.
The semiconductor device 1A (1) includes a semiconductor substrate 10 having an electrode 2 formed on one surface 10a, a protrusion 20 disposed on the semiconductor substrate 10, and a surface 10a of the semiconductor substrate 10. A first insulating resin layer 11 having a first opening 11a that exposes at least a part of the electrode 2 is disposed on the first insulating resin layer 11, and is electrically connected to the electrode 2 through the first opening 11a. A conductive layer 12 connected, a second insulating resin layer 13 disposed so as to cover the conductive layer 12 and having a second opening 13a exposing at least a part of the conductive layer 12, and the second opening And a bump 14 disposed on the conductive layer 12 exposed from 13a.
In the semiconductor device 1 of the present invention, a region of the conductive layer 12 that contacts the bumps 14 includes a flat central region 12a and an inclined outer region 12b, and the inclination is the central region 12a. It has a negative angle toward.

  In the present invention, a region of the conductive layer 12 that is in contact with the bump 14 includes a flat central region 12a and an inclined outer region 12b, and the inclination is negative toward the central region 12a. Since it has an angle, the conductive layer 12 can be easily deformed in the outer region 12b (inclined portion), and the stress applied to the bumps 14 can be dispersed. As a result, the progress of cracks and separation around the bumps 14, and hence the disconnection and short circuit of the circuit can be prevented. As a result, the semiconductor device 1 of the present invention has improved connection reliability when mounted on a mounting board.

  The semiconductor substrate 10 is made of, for example, silicon, gallium arsenide, or the like, and an Al pad, for example, as the electrode 2 is provided on one surface 10a of a base material whose at least surface layer forms an insulating portion (not shown).

The convex portion 20 is arranged on the semiconductor substrate 10 corresponding to the inclination. As a result, the conductive layer 12 disposed on the upper side of the convex portion 20 has a flat central region 12a in contact with the bumps 14 and an outer region 12b having a negative angle toward the central region 12a. It consists of.
FIG. 2 is a plan view showing the positional relationship between the convex portion 20 and the conductive layer 12 in the semiconductor device 1A (1) shown in FIG. As shown in FIG. 2, the convex portion 20 has a substantially ring shape in plan view, and the inner diameter of the upper surface is larger than the diameter of the region where the conductive layer 12 is in contact with the bumps 14. 2 and FIG. 7 to be described later, the outline of the convex portion 20 is indicated by a dotted line.

The convex portion 20 is preferably made of a material having a Young's modulus smaller than that of the material forming the first insulating resin layer 11 and / or the second insulating resin layer 13. Moreover, the material which comprises the convex part 20 has the high adhesive force with respect to the semiconductor substrate 10 or the 1st insulating resin layer 11, and a thing with a Young's modulus of 0.1-3.0 GPa is good. Specific examples of such a material include a polyimide resin, an epoxy resin, a phenol resin, a silicone resin, and an ABS resin.
Moreover, as for the thickness (height) of the convex part 20, 10-100 micrometers is preferable. Thereby, as will be described later, in the conductive layer 12 disposed on the upper side of the convex portion 20, the step between the outer region 12b in contact with the bump 14 and the central region 12a can be 10 μm or more.

The first insulating resin layer 11 is disposed on the semiconductor substrate 10 and has a first opening 11 a that exposes at least a part of the electrode 2.
The first insulating resin layer 11 is preferably one having high insulation, excellent heat resistance and chemical resistance, strong mechanical strength, and a coefficient of thermal expansion of 5 to 100 ppm / ° C. Specifically, for example, a polyimide resin, an epoxy resin, a phenol resin, a silicone resin, an ABS resin, and the like can be given.

The conductive layer 12 is disposed on the first insulating resin layer 11 and is electrically connected to the electrode 2 through the first opening 11a.
The conductive layer 12 is a rewiring layer (underpass) that electrically connects the electrode 2 and the bump 14. One end of the conductive layer 12 is electrically connected to the electrode 2 through the first opening 11 a of the first insulating resin layer 11. The other end portion of the conductive layer 12 is electrically connected to the bump 14.

The conductive layer 12 is made of a material having excellent electrical conductivity and high heat resistance. Examples of such a material include copper, silver, and nickel. Alternatively, an alloy containing these as a main component or a laminated structure thereof may be used. Among them, copper having a low electrical resistivity and relatively inexpensive is preferable.
Moreover, it is preferable that the thickness of the conductive layer 12 is 1-20 micrometers.

In particular, in the semiconductor device 1 of the present invention, a region of the conductive layer 12 that is in contact with the bump 14 includes a flat central region 12a and an inclined outer region 12b, and the inclination is the central region 12a. Has a negative angle towards
As described above, since the convex portion 20 is disposed on the semiconductor substrate 10, the conductive layer 12 disposed on the upper side of the convex portion 20 has a flat central region 12 a that is in contact with the bump 14. And an outer region 12b having an inclination with a negative angle toward the central region 12a.

Since the outer region 12b in contact with the bump 14 is inclined, the conductive layer 12 can be easily deformed in the outer region 12b (inclined portion) (see FIG. 3). As a result, the stress applied to the bumps 14 can be dispersed, and the connection reliability when mounted on the substrate can be improved.
Further, as shown in FIG. 4, a brittle intermetallic compound 30 is formed at the interface between the conductive layer 12 and the bumps 14, but the outer region 12b in contact with the bumps 14 is inclined, so that the horizontal direction in which cracks progress. This intermetallic compound 30 does not exist in the direction, and therefore, cracks are less likely to develop than in the conventional structure, and electrical characteristics are unlikely to deteriorate.

  Further, the end portion of the conductive layer 12 is in a position not exceeding the upper surface of the convex portion 20 at a position further away from the electrode 2. This facilitates deformation as shown in FIG. That is, when the upper surface is exceeded, the conductive layer 12 covers the convex portion 20, and the flexibility of the convex portion 20 is hindered, and the present invention can eliminate this.

In the conductive layer 12, the step between the outer region 12b in contact with the bump 14 and the central region 12a is preferably 10 μm or more. For example, when the main component of the bump 14 is tin (Sn) and the surface of the conductive layer 12 bonded to the bump 14 is copper (Cu), the bonding portion is made of a metal between Cu ₆ Sn ₅ and Cu ₃ Sn. Compounds are easily formed. Since these intermetallic compounds are brittle, if they are in the crack propagation path of the bump 14, the crack progresses quickly. Therefore, by setting the step between the outer region 12b in contact with the bump 14 of the conductive layer 12 and the central portion to 10 μm or more, even if the intermetallic compound grows, it does not reach the height at which the crack progresses. . Thereby, progress of a crack can be prevented more reliably.

The second insulating resin layer 13 has a second opening 13 a that is disposed so as to cover the conductive layer 12 and exposes the conductive layer 12.
The second insulating resin layer 13 preferably has high insulating properties, excellent heat resistance and chemical resistance, strong mechanical strength, and preferably has a Young's modulus of 0.1 to 5 GPa. Specific examples of such a material include polyimide resin, epoxy resin, phenol resin, silicone resin, and ABS resin.
Moreover, it is preferable that the thickness of the 2nd insulating resin layer 13 is 5-100 micrometers.

The bumps 14 are made of, for example, solder, and are disposed on the conductive layer 12 exposed from the second opening 13a.
The solder may have a composition containing lead or a composition not containing lead. As the composition not containing lead, a composition containing tin as a main component and at least one of elements of silver, copper, indium, zinc and bismuth is preferable.
In particular, in the semiconductor device 1 of the present invention, since the central area 12a in contact with the bumps 14 of the conductive layer 12 is recessed as described above, the bumps 14 are not easily displaced and are easy to form. Further, since the central region 12a of the conductive layer 12 has a concave shape, even if there is a void at the interface between the conductive layer 12 and the bump 14, it does not affect the progress of cracks. The width expands.

Next, a method for manufacturing such a semiconductor device 1 will be described.
FIG. 5 is a cross-sectional view showing an example of the method for manufacturing a semiconductor device of the present invention in the order of steps.
In the method for manufacturing a semiconductor device according to the present invention, the protrusions 20 are formed on the semiconductor substrate 10 or the first insulating resin layer 11 so as to correspond to the inclination using photolithography, laser processing, or RIE. It is characterized by.

In the present invention, the projections 20 are formed on the semiconductor substrate 10 or the first insulating resin layer 11 so as to correspond to the inclination by using photolithography, laser processing, or RIE. In the semiconductor device 1 obtained in this way, a region in contact with the bump 14 in the conductive layer 12 includes a flat central region 12a and an inclined outer region 12b, and the inclination is the central region. It will have a negative angle towards 12a. Since the conductive layer 12 can be easily deformed in the outer region 12b (inclined portion), the stress applied to the bumps 14 can be dispersed. As a result, the progress of cracks around the bumps 14, and thus the disconnection and short circuit of the circuit can be prevented. As a result, according to the present invention, a semiconductor device with improved connection reliability when mounted on a mounting board can be manufactured at low cost by a simple process.
Hereinafter, each step will be described.

(1) First, as shown in FIG. 5A, the convex portion 20 is formed on the semiconductor substrate 10.
The convex portion 20 is formed by using a photosensitive resin, laminating a dry film, or applying a varnish by a spin coating method, a screen printing method, or a spray coating method, and then patterning by photolithography. Alternatively, patterning may be performed using a non-photosensitive resin by a screen printing method or a dispensing method.

(2) Next, as shown in FIG. 5B, the first insulating resin layer 11 is formed on the one surface 10 a of the semiconductor substrate 10.
The first insulating resin layer 11 is formed by using a photosensitive resin, laminating a dry film, or applying a varnish using a spin coating method or a screen printing method. The first opening 11a can be formed, for example, by patterning using a photolithography technique or by patterning with a laser or RIE after forming a non-photosensitive resin on the entire surface of the wafer.

(3) Next, as shown in FIG. 5C, a conductive layer 12 is formed on the first insulating resin layer 11.
As a method for forming the conductive layer 12, there are an additive method, a semi-additive method, a subtractive method, a lift-off method, and the like. Among these, a semi-additive method capable of easily forming a fine wiring is more preferable.
In the case of the semi-additive method, the conductive layer 12 includes a close contact portion and a conductive portion.

The adhesion portion is provided to ensure adhesion between the conductive layer 12 and the semiconductor substrate 10 and to easily form the conductive layer 12. Further, it plays a role of suppressing migration between the electrode 2 of the semiconductor substrate 10 and the conductive portion.
The close contact portion is formed on one surface 10a of the semiconductor substrate 10 by vapor deposition, sputtering, CVD, or the like. The material is preferably a metal such as chromium, titanium, tungsten, titanium-tungsten, copper, nickel, and more preferably a laminated structure thereof.

Next, a patterned resist is formed on the contact portion. The resist is laminated with a dry film, or varnish is applied by spin coating or screen printing, and then patterned by photolithography.
Next, a conductive part is formed by electrolytic plating. The material is preferably a metal having excellent electrical conductivity and high heat resistance, such as copper, silver, and nickel. Alternatively, an alloy containing these as a main component or a laminated structure thereof may be used. Among them, copper having a low electrical resistivity and relatively inexpensive is most preferable. The thickness of the conductive part is preferably 1 to 20 μm. The resist is removed, and unnecessary portions of the close contact portion are removed by wet etching or dry etching.

In the case where the surface of the conductive layer 12 is copper, since copper easily dissolves in tin, which is one of the components of the solder, and easily forms an intermetallic compound. A layer containing at least one element of nickel, gold, and palladium may be formed on the surface of the surface using electroless plating.
Since the convex portion 20 is formed on the semiconductor substrate 10, the conductive layer 12 formed on the upper side of the convex portion 20 has a flat central region 12 a in contact with the bumps 14, and toward the central region 12 a. And an outer region 12b having an inclination having a negative angle.

(4) Next, as shown in FIG. 5D, a second insulating resin layer 13 is formed so as to cover the conductive layer 12.
The second insulating resin layer 13 is formed by using a photosensitive resin, laminating a dry film, or applying a varnish using a spin coating method or a screen printing method. The second opening 13a can be formed, for example, by patterning using a photolithography technique or by patterning with a laser or RIE after forming a non-photosensitive resin on the entire surface of the wafer.

(5) Next, as shown in FIG. 5E, bumps 14 are formed on the conductive layer 12 exposed from the second openings 13a.
The bumps 14 can be formed by a solder ball mounting method, an electrolytic solder plating method, a solder paste printing method, a solder paste dispensing method, a solder vapor deposition method, or the like.

At this time, in the present invention, since the central region 12a in contact with the bumps 14 of the conductive layer 12 is recessed, the bumps 14 are not easily displaced and are easy to form. Further, since the central region 12a of the conductive layer 12 has a concave shape, even if there is a void at the interface between the conductive layer 12 and the bump 14, it does not affect the progress of cracks. The width expands.
Through the above steps, the semiconductor device 1A (1) as shown in FIG. 1 is obtained.

<Second embodiment>
Next, a second embodiment of the semiconductor device of the present invention will be described.
FIG. 6 is a cross-sectional view showing an example of the semiconductor device 1B (1) of this embodiment.
In the following description, portions different from the above-described first embodiment will be mainly described, and description of similar portions will be omitted.
In the first embodiment described above, the protrusions 20 are formed on the semiconductor substrate 10. However, in the present embodiment, the protrusions 20 are arranged on the first insulating resin layer 11 so as to correspond to the inclination.

  A convex portion 20 having a lower Young's modulus is formed on the first insulating resin layer 11 so that the conductive layer 12 bonded to the bumps 14 can be easily deformed compared to the case of the first embodiment. Directly adhered to. Thereby, the stress concerning bump 14 can be distributed more effectively. As a result, the semiconductor device 1B (1) has improved connection reliability when mounted on the mounting board.

  When forming the convex portion 20 on the first insulating resin layer 11, in order to make the side surface of the convex portion 20 have a gentle inclination, the photosensitive resin is improved, and the developer in the exposed portion and the unexposed portion is developed. It is preferable to reduce the difference in the dissolution rate in and further increase the development time. In addition, when using a non-photosensitive resin, it is preferable to select one that has improved wet spreadability.

<Third embodiment>
Next, a third embodiment of the semiconductor device of the present invention will be described.
FIG. 7 is a diagram illustrating an example of the semiconductor device 1C (1) of the present embodiment, and is a plan view illustrating a positional relationship between the convex portion 20 and the conductive layer 12 in the semiconductor device 1C (1).
In the following description, portions different from the above-described first embodiment will be mainly described, and description of similar portions will be omitted.
In the semiconductor device 1 </ b> C (1), the convex portion 20 has a substantially ring shape when seen in a plan view, and is substantially perpendicular to the direction connecting the central portion of the bump 14 and the central portion of the semiconductor substrate 10. It consists of two or more structures 20a and 20b arranged extending in the direction of forming.

  In the first embodiment described above, since the convex portions 20 are arranged in a substantially ring shape, the conductive layer 12 must be formed over the protrusions formed by the convex portions 20, and it is difficult to manufacture. Therefore, in the present embodiment, the convex portion 20 is divided into a plurality (here, two) of arcuate structures 20a and 20b that are substantially perpendicular to the chip center direction, and the conductive layer 12 is formed of the structures 20a and 20b. The conductive layer 12 can be formed more easily by providing the gap between them. In addition, since the stress applied to the bumps 14 is parallel to the chip center direction, the effect of dispersing the stress applied to the bumps 14 and preventing the progress of cracks can be sufficiently maintained even in this shape.

The present invention can also be applied to an electronic device using the semiconductor device 1 as described above.
The present invention can be applied to electronic devices that require small and high-density electronic components such as mobile phones, digital cameras, and notebook computers. Further, the present invention can be applied not only to the wafer level CSP but also to all BGA packages connected via bumps or flip chip.

  Although the semiconductor device, the manufacturing method thereof, and the electronic apparatus of the present invention have been described above, the present invention is not limited to this, and can be appropriately changed without departing from the spirit of the invention.

  The present invention can be widely applied to semiconductor devices, manufacturing methods thereof, and electronic devices.

FIG. 10 is a cross-sectional view illustrating an example of a semiconductor device according to the invention. FIG. 2 is a plan view showing a positional relationship between a convex portion and a conductive layer in the semiconductor device shown in FIG. 1. Sectional drawing which expands and shows the part of an electroconductive part and a bump. Sectional drawing which expands and shows the part of an electroconductive part and a bump. Sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention in process order. Sectional drawing which shows another example of the semiconductor device which concerns on this invention. It is a figure which shows another example of the semiconductor device which concerns on this invention, and is a top view which shows the positional relationship of a convex part and a conductive layer. Sectional drawing which shows an example of the conventional semiconductor device.

Explanation of symbols

  1 (1A, 1B, 1C) Semiconductor device, 2 electrodes, 10 semiconductor substrate, 11 first insulating resin layer, 11a first opening, 12 conductive layer, 12a central region, 12b outer region, 13 second insulating resin layer, 13a 2nd opening part, 14 bump, 20 convex part, 20a, 20b Structure.

Claims (8)

A semiconductor substrate having an electrode formed on one surface;
A first insulating resin layer disposed on one surface of the semiconductor substrate and having a first opening exposing at least a portion of the electrode;
A conductive layer disposed on the first insulating resin layer and electrically connected to the electrode through the first opening;
A second insulating resin layer disposed so as to cover the conductive layer and having a second opening that exposes at least a part of the conductive layer;
And at least a bump disposed on the conductive layer exposed from the second opening,
Of the conductive layer, a region in contact with the bump is composed of a flat central region and an outer region having an inclination,
The semiconductor device according to claim 1, wherein the inclination has a negative angle toward the central region.   The semiconductor device according to claim 1, wherein a convex portion is disposed on the semiconductor substrate or the first insulating resin layer so as to correspond to the inclination.   3. The semiconductor device according to claim 2, wherein the end portion of the conductive layer is in a position not exceeding the upper surface of the convex portion at a position further away from the electrode.   The semiconductor device according to claim 2, wherein the convex portion has a substantially ring shape when seen in a plan view.   The projections have a substantially ring shape when seen in a plan view, and two or more arranged to extend in a direction substantially perpendicular to the direction connecting the central part of the bump and the central part of the semiconductor substrate. The semiconductor device according to claim 2, wherein the semiconductor device is formed of the following structure.   6. The semiconductor according to claim 2, wherein the convex portion is made of a material having a Young's modulus smaller than that of the material forming the first insulating resin layer and / or the second insulating resin layer. apparatus. A semiconductor substrate having an electrode formed on one surface;
A first insulating resin layer disposed on one surface of the semiconductor substrate and having a first opening exposing at least a portion of the electrode;
A conductive layer disposed on the first insulating resin layer and electrically connected to the electrode through the first opening;
A second insulating resin layer disposed so as to cover the conductive layer and having a second opening that exposes at least a part of the conductive layer;
And at least a bump disposed on the conductive layer exposed from the second opening,
Of the conductive layer, a region in contact with the bump is composed of a flat central region and an outer region having an inclination,
The inclination is a method of manufacturing a semiconductor device having a negative angle toward the central region,
A method of manufacturing a semiconductor device, wherein a convex portion is formed on the semiconductor substrate or the first insulating resin layer so as to correspond to the inclination by using photolithography, laser processing, or RIE.   An electronic device comprising the semiconductor device according to claim 1.

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