JP2007242783A - Semiconductor device and electronic apparatus - Google Patents

Semiconductor device and electronic apparatus Download PDF

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JP2007242783A
JP2007242783A JP2006061015A JP2006061015A JP2007242783A JP 2007242783 A JP2007242783 A JP 2007242783A JP 2006061015 A JP2006061015 A JP 2006061015A JP 2006061015 A JP2006061015 A JP 2006061015A JP 2007242783 A JP2007242783 A JP 2007242783A
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bump
semiconductor device
resin layer
disposed
semiconductor substrate
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Toshiaki Inoue
俊明 井上
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Fujikura Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate in which bumps used as electrodes for external connection are joined to a semiconductor substrate, which can disperse a stress imposed on the external peripheral portion of the semiconductor substrate, and which can ensure stability of electrical connection by being equipped with a simple configuration without an increase in thickness. <P>SOLUTION: This semiconductor device 1 is provided with an insulating resin layer 4 having an opening 4a for an electrode on a position matching an electrode 3 arranged on one surface of the semiconductor substrate 2. A plurality of connections 10A, 10B provided with conductive sections 5 (5A, 5B) to be electrically connected to the electrode through the opening are arranged so as to cover a part of the insulating resin layer. Of the connections, at least one arranged on an internal region β on one surface of the semiconductor substrate has rigidity larger than that of the one arranged on an external region α on the one surface of the semiconductor substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置及び電子装置に関し、詳しくはバンプと呼ばれる半導体素子の電極を配した構造を有する半導体装置において、実装基板等に実装した状態での充分な接続寿命を持つパッケージを実現するための構造を有する半導体装置及びこの半導体装置を具備する電子機器に関するものである。   The present invention relates to a semiconductor device and an electronic device, and more particularly, to realize a package having a sufficient connection life when mounted on a mounting substrate or the like in a semiconductor device having a structure in which electrodes of semiconductor elements called bumps are arranged. The present invention relates to a semiconductor device having the structure and an electronic device including the semiconductor device.

従来、電子部品で用いられる半導体パッケージ構造として、たとえば半導体チップを樹脂により封止したパッケージ（所謂、「Dual Inline Package、以下「ＤＩＰ」と略記する場合がある」や「Quad Flat Package、以下「ＱＦＰ」と略記する場合がある」）では、樹脂パッケージ周辺の側面に金属リード電極を配置する周辺端子配置型が主流であった。   Conventionally, as a semiconductor package structure used in an electronic component, for example, a package in which a semiconductor chip is sealed with a resin (so-called “Dual Inline Package” may be abbreviated as “DIP” hereinafter) or “Quad Flat Package” hereinafter referred to as “QFP”. In some cases, the peripheral terminal arrangement type in which the metal lead electrode is arranged on the side surface around the resin package has been the mainstream.

これに対し、近年広く普及している半導体パッケージ構造として、たとえばボールグリットアレイ（Ball Grid Array、以下「ＢＧＡ」と略記する場合がある）がある。これは、パッケージの平坦な表面に半田バンプと呼ばれる電極を二次元的に配置した構造を有しているため、ＤＩＰやＱＦＰに比べて高密度な実装が可能となる。このため、ＢＧＡはコンピュータのＣＰＵやメモリなどのパッケージとして使われている。従来のＢＧＡタイプの半導体パッケージは、パッケージサイズがチップサイズよりも大きいが、なかでもパッケージをほとんどチップサイズに近い大きさにまで小型化したパッケージはＣＳＰ（チップスケールパッケージ）と呼ばれ、電子機器の小型軽量化に大きく貢献している。   On the other hand, as a semiconductor package structure widely spread in recent years, there is, for example, a ball grid array (hereinafter sometimes abbreviated as “BGA”). This has a structure in which electrodes called solder bumps are two-dimensionally arranged on the flat surface of the package, so that high-density mounting is possible as compared with DIP or QFP. For this reason, the BGA is used as a package for a computer CPU and memory. A conventional BGA type semiconductor package has a package size larger than the chip size, and a package that is downsized to a size almost close to the chip size is called a CSP (chip scale package). Contributes greatly to the reduction in size and weight.

これらＢＧＡタイプの半導体パッケージは、回路を形成したウエハ基板を切断し、その半導体チップをインターポーザと呼ばれる基板に搭載してパッケージを完成させるもので、パターニングされたインターポーザが必要である上に、個々に半導体チップを個別にインターポーザに実装する工程が必要である。このため、専用の材料や製造装置を用いなければならず、コストが高くなるという欠点があった。   In these BGA type semiconductor packages, a wafer substrate on which a circuit is formed is cut, and the semiconductor chip is mounted on a substrate called an interposer to complete the package. In addition to the need for a patterned interposer, individually A process of individually mounting the semiconductor chip on the interposer is necessary. For this reason, a dedicated material or manufacturing apparatus has to be used, and there is a drawback that the cost is increased.

これに対し、一般的に「ウエハレベルＣＳＰ」と呼ばれる製法においては、このウエハ基板上に、絶縁樹脂層、再配線層、封止樹脂層、はんだバンプ等を形成し、最終工程おいてウエハを所定のチップ寸法に切断することでパッケージ構造を具備した半導体チップを得ることができる。したがって、パッケージ構造をウエハ基板上に一括形成するため、従来のようにインターポーザを必要とせず、またウエハ状態で加工するので専用の装置を必要としない。このため製造効率が高く、コスト面で有利となっている。しかも、ウエハ全面にパッケージ加工を施した後にダイシングして個片化することから、個片化したチップそのものの大きさが、パッケージの施された半導体チップとなり、実装基板に対して最小投影面積を有する半導体チップを得ることが可能となる。また、配線距離が従来のパッケージよりも短く、配線の寄生容量も小さい。これら優れた特徴は、現在急速に進んでいる実装の高密度化や、情報処理速度の高速化が実現できるという点において非常に優位である。ウエハレベルＣＳＰの技術については、たとえば、日経マイクロデバイス誌、２００２年２月号のｐ．４２や、同誌２０００年３月号のｐ．１２１、同誌２０００年４月号のｐ．１１４などに詳細が記載されている。   On the other hand, in a manufacturing method generally called “wafer level CSP”, an insulating resin layer, a rewiring layer, a sealing resin layer, solder bumps, and the like are formed on the wafer substrate, and the wafer is formed in the final process. A semiconductor chip having a package structure can be obtained by cutting to a predetermined chip size. Therefore, since the package structure is collectively formed on the wafer substrate, an interposer is not required as in the prior art, and since processing is performed in the wafer state, a dedicated apparatus is not required. For this reason, manufacturing efficiency is high and it is advantageous in terms of cost. Moreover, since the entire wafer surface is packaged and then diced into individual pieces, the size of the individual chips themselves becomes the semiconductor chip with the package, and the minimum projected area on the mounting substrate is reduced. It is possible to obtain a semiconductor chip having the same. Further, the wiring distance is shorter than that of the conventional package, and the parasitic capacitance of the wiring is also small. These excellent features are extremely advantageous in that high-density mounting and high-speed information processing can be realized, which are currently progressing rapidly. Regarding the wafer level CSP technology, see, for example, p. 42, p. 121, p. Details are described in 114 and the like.

このようにウエハレベルＣＳＰは、高密度な実装を実現できる安価な半導体パッケージであるが、半導体パッケージを実装基板に実装した状態での接続寿命は、従来のパッケージに比べてやや劣るという問題点がある。
このため、半導体パッケージを実装基板に実装した状態での接続寿命を向上させるためにさまざまな構造が提案されている。たとえば、応力の緩和・吸収の機能を有する樹脂コアを備えたこのポスト構造を、はんだバンプのそれぞれに形成する方法（特許文献１参照）や、バンプが配設された基板を金型のキャビティ内に装着し、樹脂を供給してバンプを封止する方法（特許文献２参照）、厚さが２００μｍ以下である半導体素子の主面が樹脂封止された半導体装置を実装基板上に配置し、熱処理によって半導体装置と実装基板とを接続する方法（特許文献３参照）、バンプ下地金属上に形成されるアウターリードを、バンプ下地金属上の第１バンプおよび第１バンプ上の第２バンプで構成する方法（特許文献４参照）が提案されている。 As described above, the wafer level CSP is an inexpensive semiconductor package that can realize high-density mounting. However, the connection life in a state where the semiconductor package is mounted on the mounting substrate is slightly inferior to that of the conventional package. is there.
For this reason, various structures have been proposed in order to improve the connection life when the semiconductor package is mounted on the mounting substrate. For example, a method of forming this post structure having a resin core having a stress relaxation / absorption function on each solder bump (see Patent Document 1), or a substrate on which a bump is disposed in a mold cavity A method of sealing a bump by supplying a resin and supplying a resin (see Patent Document 2), disposing a semiconductor device on which a main surface of a semiconductor element having a thickness of 200 μm or less is resin-sealed on a mounting substrate, A method of connecting a semiconductor device and a mounting substrate by heat treatment (see Patent Document 3), and an outer lead formed on a bump base metal is composed of a first bump on the bump base metal and a second bump on the first bump A method (see Patent Document 4) has been proposed.

すなわち、実装基板に実装した半導体パッケージは、衝撃、振動など外部から機械的な荷重を受けるだけでなく、半導体パッケージと実装基板との熱膨張率の違いによって発生する熱応力を受ける。このような応力は、ＢＧＡを始めとする半田バンプを介して実装基板と半導体チップとを電気的・機械的に接続する半導体パッケージでは、この半田バンプの接合部に最も集中しやすい。このため、この半田バンプやその周辺では、図１１に示すように、クラック１００ａや剥離１００ｂなどの問題が発生し易く、最終的には回路の断線や短絡に至って、デバイスが動作しなくなってしまうという虞がある。特に、半導体素子の外周部は、内側より大きな応力を受け易く、半田バンプにクラックが入る可能性が高い。
図１１は、半田バンプ１０８が接合された半導体パッケージ１０１を、半田バンプ１０８を介して実装基板１１０の接続部１１２に実装した概略断面図であり、半田バンプ１０８に接続寿命を低下させるクラック１００ａ等が発生した状態を示す。半導体パッケージ１０１は、半導体基板１０２の一面に絶縁樹脂層１０４、配線１０５、半田バンプ１０８が順に設けられている。 That is, the semiconductor package mounted on the mounting substrate receives not only a mechanical load from the outside such as impact and vibration, but also a thermal stress generated by a difference in thermal expansion coefficient between the semiconductor package and the mounting substrate. Such stress is most likely to be concentrated at the solder bump joint in a semiconductor package in which the mounting substrate and the semiconductor chip are electrically and mechanically connected via a solder bump such as a BGA. For this reason, as shown in FIG. 11, problems such as cracks 100a and peeling 100b are likely to occur in the solder bumps and the vicinity thereof, eventually leading to circuit disconnection and short circuit, and the device becomes inoperable. There is a fear. In particular, the outer peripheral portion of the semiconductor element is likely to be subjected to a larger stress than the inner side, and there is a high possibility that the solder bump will crack.
FIG. 11 is a schematic cross-sectional view in which the semiconductor package 101 to which the solder bumps 108 are bonded is mounted on the connection portion 112 of the mounting substrate 110 via the solder bumps 108. Indicates the state where has occurred. In the semiconductor package 101, an insulating resin layer 104, wiring 105, and solder bumps 108 are sequentially provided on one surface of the semiconductor substrate 102.

具体的には、このウエハレベルＣＳＰは、以下に示すような二つの問題を有する。
（１）強度の不利
半田バンプは、実装基板から受ける外部応力あるいは熱応力を緩和・吸収する機能を有する。しかし、その応力が大きいほど、あるいは加わる回数が多いほど、はんだバンプには金属疲労が蓄積していくため、強度が劣化してしまう。その結果、バンプにクラックが生じ、破断してしまう。
また、はんだバンプで緩和・吸収できなかった応力成分は、半導体パッケージの配線や絶縁樹脂層、あるいは半導体デバイスそのものに加わるため、これらの接続境界からの剥離が発生しやすくなる。
（２）電気的接続の不利
バンプにクラックが発生すると、配線回路の電気抵抗が増大してしまうため、半導体デバイスに必要な電力が供給できなくなる。あるいは電気信号が正常に伝達しなくなってしまう。特に、１００ＭＨｚを越えるような周波数の高い信号になると、その伝達特性は劣化しやすい。 Specifically, this wafer level CSP has the following two problems.
(1) Disadvantage of strength Solder bumps have a function to relieve and absorb external stress or thermal stress received from a mounting substrate. However, as the stress increases or the number of times of application increases, metal fatigue accumulates in the solder bumps, and the strength deteriorates. As a result, the bump is cracked and broken.
Moreover, since the stress component that could not be relaxed / absorbed by the solder bumps is applied to the wiring of the semiconductor package, the insulating resin layer, or the semiconductor device itself, peeling from these connection boundaries is likely to occur.
(2) Disadvantage of electrical connection If cracks occur in the bumps, the electrical resistance of the wiring circuit increases, making it impossible to supply the necessary power to the semiconductor device. Or an electric signal will not transmit normally. In particular, when the signal has a high frequency exceeding 100 MHz, its transfer characteristics are likely to deteriorate.

このような問題を防ぐため、さらに、ポストと呼ばれる金属製の柱をはんだバンプと半導体デバイスとの間に有する構造（特許文献５参照）、あるいは応力緩和機能を有する厚い樹脂層を有する構造（特許文献６及び７参照）といった手段が提案されている。
また、半導体パッケージを基板に実装した後にバンプ周辺を樹脂で補強するアンダーフィルという方法もある。 In order to prevent such a problem, a structure having a metal pillar called a post between the solder bump and the semiconductor device (see Patent Document 5) or a structure having a thick resin layer having a stress relaxation function (Patent Means such as documents 6 and 7) have been proposed.
There is also a method called underfill in which the periphery of the bump is reinforced with resin after the semiconductor package is mounted on the substrate.

しかしながら、このような複雑な構造を実現するためには多くのプロセスが必要になるため、製造コストが高価になり、かつ、時間を要するといった問題がある。また、パッケージの薄型化にも不利である。
ＷＯ２０００／０７７８４４号公報 特開平１０−７９３６２号公報 特開２０００−２９４５１９号公報 特開２０００−９１３３９号公報 特開２０００−２００８００号公報 ＷＯ１９９８／０２５２９７号公報 特開２００１−２２３２９２号公報 However, since many processes are required to realize such a complicated structure, there are problems that the manufacturing cost is high and time is required. It is also disadvantageous for making the package thinner.
WO2000 / 077784 JP-A-10-79362 JP 2000-294519 A JP 2000-91339 A JP 2000-200800 A WO1998 / 025297 JP 2001-223292 A

本発明は、上記事情に鑑みてなされたものであり、半導体基板に外部接続用電極としてのバンプが接合された半導体装置において、厚さの増加を伴わない簡単な構造を備えることにより、半導体装置の外周部において受ける応力を分散すると共に、電気的接続の安定性を確保できる半導体装置を提供することを目的とする。
また、本発明は、半導体装置を実装した際に機械的・電気的な接続安定性が確保されると共に、薄型化も図れることが可能な電子機器を提供することを目的とする。 The present invention has been made in view of the above circumstances, and in a semiconductor device in which bumps as external connection electrodes are bonded to a semiconductor substrate, the semiconductor device has a simple structure without an increase in thickness. An object of the present invention is to provide a semiconductor device that can disperse stress received at the outer peripheral portion of the semiconductor device and can ensure the stability of electrical connection.
It is another object of the present invention to provide an electronic device that can ensure mechanical and electrical connection stability and can be thinned when a semiconductor device is mounted.

本発明の請求項１に係る半導体装置は、一面に電極を配してなる半導体基板と、前記半導体基板の一面を覆うように配され、前記電極と整合する位置に電極用の開口部を有する絶縁樹脂層と、前記絶縁樹脂層の一部を覆うように配され、前記開口部を通して前記電極と電気的に接続される導電部を備えた複数の接続部と、を少なくとも備える半導体装置であって、前記接続部のうち、前記半導体基板の内域に配された少なくとも一つは、前記半導体基板の外域に配されたものより剛性が高いことを特徴とする。   According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate having an electrode disposed on one surface thereof, an electrode opening disposed at a position aligned with the electrode, the semiconductor substrate being disposed so as to cover the one surface of the semiconductor substrate. A semiconductor device comprising at least an insulating resin layer and a plurality of connecting portions provided so as to cover a part of the insulating resin layer and including a conductive portion electrically connected to the electrode through the opening. In addition, at least one of the connecting portions disposed in the inner region of the semiconductor substrate is higher in rigidity than that disposed in the outer region of the semiconductor substrate.

また、本発明の請求項２に係る半導体装置は、請求項１において、前記剛性の高い接続部は、前記導電部の上方に配されるバンプと、前記バンプの下方に配される中間層を備え、前記中間層は、前記バンプよりもヤング率が高い材料からなることを特徴とする。   The semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the highly rigid connecting portion includes a bump disposed above the conductive portion and an intermediate layer disposed below the bump. The intermediate layer is made of a material having a higher Young's modulus than the bump.

また、本発明の請求項３に係る半導体装置は、請求項２において、前記中間層は、前記半導体基板の一面と前記絶縁樹脂層の間に配されていることを特徴とする。   According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the intermediate layer is disposed between one surface of the semiconductor substrate and the insulating resin layer.

また、本発明の請求項４に係る半導体装置は、請求項２において、前記中間層は、前記導電部と前記バンプの間に配されていることを特徴とする。   The semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second aspect, wherein the intermediate layer is disposed between the conductive portion and the bump.

また、本発明の請求項５に係る半導体装置は、請求項２において、前記中間層は、前記絶縁樹脂層と前記導電部の間に配されていることを特徴とする。   According to a fifth aspect of the present invention, in the semiconductor device according to the second aspect, the intermediate layer is disposed between the insulating resin layer and the conductive portion.

また、本発明の請求項６に係る半導体装置は、請求項５において、前記絶縁樹脂層及び前記導電部を覆うように封止樹脂層を備え、前記封止樹脂層は表面が平滑であることを特徴とする。   The semiconductor device according to claim 6 of the present invention is the semiconductor device according to claim 5, further comprising a sealing resin layer so as to cover the insulating resin layer and the conductive portion, and the surface of the sealing resin layer is smooth. It is characterized by.

また、本発明の請求項７に係る半導体装置は、請求項１乃至６の何れか１項において、前記中間層は、連続体であることを特徴とする。   According to a seventh aspect of the present invention, in any one of the first to sixth aspects, the intermediate layer is a continuous body.

また、本発明の請求項８に係る半導体装置は、請求項１において、前記剛性の高い接続部は、前記導電部の上方に配されるバンプと、前記バンプの内部に配される補強部材をさらに備えており、前記補強部材は、前記バンプよりもヤング率が高い材料からなることを特徴とする。   The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the first aspect, wherein the highly rigid connecting portion includes a bump disposed above the conductive portion and a reinforcing member disposed inside the bump. Further, the reinforcing member is made of a material having a higher Young's modulus than the bump.

また、本発明の請求項９に係る半導体装置は、請求項１乃至８の何れか１項において、前記中間層もしくは前記補強部材のヤング率は、６０Ｇｐａ以上であることを特徴とする。   According to a ninth aspect of the present invention, in any one of the first to eighth aspects, the intermediate layer or the reinforcing member has a Young's modulus of 60 Gpa or more.

また、本発明の請求項１０に係る電子装置は、請求項１乃至９の何れか１項に記載の半導体装置を用いたことを特徴とする。   An electronic device according to a tenth aspect of the present invention uses the semiconductor device according to any one of the first to ninth aspects.

本発明に係る半導体装置は、半導体基板の一面に配された電極と電気的に接続される導電部を備えた複数の接続部のうち、半導体基板の一面において内域に配された少なくとも一つが、半導体基板の一面において外域に配されたものより剛性が高い構成となっている。ゆえに、内域に配された剛性が高い接続部が実装基板から受ける応力が相対的に大きくなると共に、外域に配された接続部にかかる応力が相対的に小さくなる。
したがって、半導体装置に加わる機械荷重あるいは熱応力が、複数の接続部によって緩和・吸収されてクラックの発生を抑制すると共に、半導体装置の外周部において受ける応力が、外域に配された接続部より剛性が高い内域の接続部によって分散されるので、ポストや応力緩和機能を有する厚い樹脂層といった厚さの増加を伴わない簡単な構造を備え、電気的接続の安定性を確保できる半導体装置とすることができる。 In the semiconductor device according to the present invention, at least one of the plurality of connection portions including the conductive portion electrically connected to the electrode disposed on the one surface of the semiconductor substrate is disposed in the inner region on the one surface of the semiconductor substrate. The semiconductor substrate has a higher rigidity than that disposed on the outer surface of one surface of the semiconductor substrate. Therefore, the stress received from the mounting substrate by the connection portion having high rigidity disposed in the inner region is relatively increased, and the stress applied to the connection portion disposed in the outer region is relatively decreased.
Therefore, the mechanical load or thermal stress applied to the semiconductor device is relaxed and absorbed by a plurality of connecting portions to suppress the generation of cracks, and the stress received at the outer peripheral portion of the semiconductor device is more rigid than the connecting portion disposed in the outer region. The semiconductor device has a simple structure that does not increase in thickness, such as a post and a thick resin layer having a stress relaxation function, and can ensure the stability of electrical connection. be able to.

また、本発明の電子装置は、厚さの増加を伴わない簡単な構造を備え、半導体装置の外周部において受ける応力を分散すると共に、電気的接続の安定性を確保できる半導体装置を用いることで、半導体装置を実装した際に機械的・電気的な接続安定性が確保されると共に、薄型化も図ることができる。
したがって、携帯電話やデジタルカメラ、ノートパソコンなど、小型で高密度な電子部品を必要とする電子装置において、耐衝撃性の改善や電気的な接続信頼性の向上をもたらす電子装置とすることができる。 In addition, the electronic device of the present invention has a simple structure that does not increase the thickness, disperses the stress received in the outer peripheral portion of the semiconductor device, and uses a semiconductor device that can ensure the stability of electrical connection. In addition, when the semiconductor device is mounted, the mechanical and electrical connection stability is ensured and the thickness can be reduced.
Therefore, in an electronic device that requires small and high-density electronic components such as a mobile phone, a digital camera, and a notebook personal computer, the electronic device can be improved in impact resistance and electrical connection reliability. .

以下、最良の形態に基づき、図面を参照して本発明を説明する。
図１及び図２は、本発明の半導体装置の一例を示す図面であり、図１は、本発明に係る第一の半導体装置の構造を全体的に説明する平面図であり、図２は、図１に示すＩ−Ｉ線に沿う拡大断面図である。なお、後述する実施形態においては、本実施形態と同様の構成部分については同じ符合を用い、その説明は省略することとし、特に説明しない限り同じであるものとする。
図１及び図２に示すように、本発明の第一の半導体装置１は、半導体基板２と、該半導体基板２の一面を覆うように配された絶縁樹脂層４と、該絶縁樹脂層４の一部を覆うように配された複数の接続部１０とを少なくとも備えている。 The present invention will be described below with reference to the drawings based on the best mode.
1 and 2 are drawings showing an example of a semiconductor device of the present invention, FIG. 1 is a plan view for explaining the overall structure of a first semiconductor device according to the present invention, and FIG. It is an expanded sectional view which follows the II line | wire shown in FIG. In the embodiments described later, the same reference numerals are used for the same components as in the present embodiment, the description thereof is omitted, and the same unless otherwise described.
As shown in FIGS. 1 and 2, a first semiconductor device 1 of the present invention includes a semiconductor substrate 2, an insulating resin layer 4 disposed so as to cover one surface of the semiconductor substrate 2, and the insulating resin layer 4. And a plurality of connection portions 10 arranged so as to cover a part thereof.

半導体基板２は、一面に電極３を配している。この半導体基板２は、シリコンやガリウム砒素等の半導体ウエハでもよく、半導体ウエハをチップ寸法に切断（ダイシング）した半導体チップであってもよい。半導体基板２が半導体チップである場合は、まず、半導体ウエハの上に、各種半導体素子やＩＣ等を形成した後、チップ寸法に切断することで複数の半導体チップを得ることができる。   The semiconductor substrate 2 has an electrode 3 disposed on one surface. The semiconductor substrate 2 may be a semiconductor wafer such as silicon or gallium arsenide, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the semiconductor substrate 2 is a semiconductor chip, first, various semiconductor elements, ICs, and the like are formed on the semiconductor wafer, and then a plurality of semiconductor chips can be obtained by cutting into chip dimensions.

絶縁樹脂層４は、半導体基板２の一面を覆うように配され、電極３が露呈するように、その整合する位置に開口部４ａを有する。
この絶縁樹脂層４を成す材料としては、絶縁性が高く、耐熱性、耐薬品性に優れ、機械的強度が強い樹脂が好ましい。具体的には、ポリイミド樹脂やエポキシ樹脂、フェノール樹脂、フッ素樹脂、ポリベンゾオキサゾール樹脂、ポリフェニレンサルファイド樹脂などのポリマー、あるいは窒化シリコンなどのセラミックスが好ましい。また、厚さは、ポリマーの場合は１〜２０μｍ、セラミックスの場合は０．１〜５μｍとすると良い。 The insulating resin layer 4 is disposed so as to cover one surface of the semiconductor substrate 2, and has an opening 4a at the matching position so that the electrode 3 is exposed.
As a material constituting the insulating resin layer 4, a resin having high insulation, excellent heat resistance and chemical resistance, and strong mechanical strength is preferable. Specifically, a polymer such as a polyimide resin, an epoxy resin, a phenol resin, a fluororesin, a polybenzoxazole resin, or a polyphenylene sulfide resin, or a ceramic such as silicon nitride is preferable. The thickness is preferably 1 to 20 μm in the case of a polymer and 0.1 to 5 μm in the case of a ceramic.

絶縁樹脂層４は、たとえばフォトリソグラフィ技術を利用したパターニングなどにより形成することができる。この絶縁樹脂層４の塗布方法においては、液状の感光性樹脂を、たとえばスピンコート法、キャスティング法、ディスペンス法等により、半導体基板２上に塗布することが可能である。
また、絶縁樹脂層４のパターニングにおいて、フォトリソグラフィ技術のほかに、レーザ加工法、プラズマエッチング法、シート状の樹脂をラミネート法にて圧着させる方法、により形成することもできる。さらに、絶縁樹脂層４は、樹脂をスクリーン印刷にて直接、成膜かつパターニングする方法も可能であり、その場合は、樹脂が感光性である必要はなくなる。 The insulating resin layer 4 can be formed by, for example, patterning using a photolithography technique. In this coating method of the insulating resin layer 4, a liquid photosensitive resin can be coated on the semiconductor substrate 2 by, for example, a spin coating method, a casting method, a dispensing method, or the like.
Further, in the patterning of the insulating resin layer 4, in addition to the photolithography technique, it can be formed by a laser processing method, a plasma etching method, or a method in which a sheet-like resin is pressure-bonded by a laminating method. Further, the insulating resin layer 4 can be formed by direct film formation and patterning by screen printing. In this case, the resin does not need to be photosensitive.

接続部１０は、縁樹脂層４の一部を覆うように複数配されており、たとえば図１示す二点鎖線を境として、半導体基板の一面における外側を外域α、内側を内域β、また、たとえば図２示す二点鎖線を境として半導体基板の一面における左側を外域α、右側を内域βとすると、内域βに配された少なくとも一つの接続部は、外域α側に配された接続部より剛性が高い構成となっている。すなわち、半導体基板の内域βに配された接続部が全て、外域αに配された接続部より剛性が高い必要はなく、半導体基板の内域βに、半導体基板の外域αに配された接続部の何れかより剛性が高い接続部が少なくとも一つ（たとえば、最も応力が加わる個所に）配されていれば良い。
したがって、接続部１０が、たとえば半導体基板２の外域αに位置する第１接続部１０Ａと、その他の領域である半導体基板２の内域βに位置する第２接続部１０Ｂとから構成された場合、少なくとも第２接続部１０Ｂの一部に、第１接続部１０Ａより剛性が高い構成の接続部が含まれるものであっても良いし、本実施形態のように、第２接続部１０Ｂの全てが、第１接続部１０Ａの何れか一つより剛性が高い構成の接続部であるものであっても良い。 A plurality of connection portions 10 are arranged so as to cover a part of the edge resin layer 4. For example, with the two-dot chain line shown in FIG. 1 as a boundary, the outer side α on the one surface of the semiconductor substrate, the inner side β on the inner side, For example, assuming that the left side of the one side of the semiconductor substrate is the outer region α and the right side is the inner region β with the two-dot chain line shown in FIG. 2 as a boundary, at least one connection portion arranged in the inner region β is arranged on the outer region α side. The structure is higher in rigidity than the connection part. That is, all the connecting portions arranged in the inner region β of the semiconductor substrate do not have to be higher in rigidity than the connecting portions arranged in the outer region α, and are arranged in the inner region β of the semiconductor substrate in the outer region α of the semiconductor substrate. It suffices that at least one connecting portion having higher rigidity than any one of the connecting portions is disposed (for example, at a place where the stress is most applied).
Therefore, when the connection part 10 is comprised from the 1st connection part 10A located in the outer area | region (alpha) of the semiconductor substrate 2, for example, and the 2nd connection part 10B located in the inner area | region (beta) of the semiconductor substrate 2 which is another area | region. In addition, at least a part of the second connection portion 10B may include a connection portion having a higher rigidity than the first connection portion 10A, or all of the second connection portions 10B as in the present embodiment. However, it may be a connecting portion having a higher rigidity than any one of the first connecting portions 10A.

本実施形態の場合、第１接続部１０Ａと第２接続部１０Ｂは共に、絶縁樹脂層４の一部を覆うように配され、開口部４ａを通して電極３と電気的に接続される導電部５（５Ａまたは５Ｂ）を備える。また、第１接続部１０Ａは、導電部５Ａの他に第１のバンプ８をさらに備え、一方、第２接続部１０Ｂの少なくとも一つは、導電部５Ｂの他に中間層６と第２のバンプ９とをさらに備える。したがって、第１接続部１０Ａは、導電部５Ａと第１のバンプ８とから構成され、第２接続部１０Ｂは、導電部５Ｂと中間層６と第２のバンプ９とから構成されている。   In the case of the present embodiment, the first connection portion 10A and the second connection portion 10B are both arranged so as to cover a part of the insulating resin layer 4, and are electrically connected to the electrode 3 through the opening 4a. (5A or 5B). The first connection portion 10A further includes a first bump 8 in addition to the conductive portion 5A. On the other hand, at least one of the second connection portions 10B includes the intermediate layer 6 and the second layer in addition to the conductive portion 5B. A bump 9 is further provided. Therefore, the first connection portion 10A is composed of the conductive portion 5A and the first bump 8, and the second connection portion 10B is composed of the conductive portion 5B, the intermediate layer 6, and the second bump 9.

導電部５Ａ，５Ｂは、外部基板との接続領域に、絶縁樹脂層４の一部を覆うようにシード層を介して配された接続パッドであり、導電部５Ａがバンプ８を介して外部基板と接続され、導電部５Ｂがバンプ９を介して外部基板と接続される。
導電部５（５Ａ，５Ｂ）の材料としては共に、導電性に優れ、耐熱性に優れた金属が良く、たとえば、銅（Ｃｕ）や銀（Ａｇ）、金（Ａｕ）、ニッケル（Ｎｉ）、アルミニウム（Ａｌ）などが好ましい。あるいはこれらを主成分とした合金、またはこれらの積層構造でも構わない。その中でも、電気抵抗率が低く、比較的安価な銅がより好ましい。また、バンプ８，９との接続を容易にするために、導電部５Ａ，５Ｂの少なくともバンプ８，９と接する面は、金であるのがより好ましい。 The conductive portions 5A and 5B are connection pads arranged through a seed layer so as to cover a part of the insulating resin layer 4 in a connection region with the external substrate, and the conductive portion 5A is connected to the external substrate via the bumps 8. And the conductive portion 5B is connected to the external substrate through the bumps 9.
As the material of the conductive portion 5 (5A, 5B), a metal excellent in conductivity and excellent in heat resistance is preferable. For example, copper (Cu), silver (Ag), gold (Au), nickel (Ni), Aluminum (Al) or the like is preferable. Or the alloy which has these as a main component, or these laminated structures may be sufficient. Among them, copper having a low electrical resistivity and relatively inexpensive is more preferable. In order to facilitate the connection with the bumps 8 and 9, it is more preferable that at least the surface of the conductive portions 5A and 5B in contact with the bumps 8 and 9 is gold.

また、この導電部５Ａ，５Ｂの厚さは１〜２０μｍとすると良く、これにより充分な導電性が得られる。なお、導電部５を金表面の積層構造とした場合、表面の金層の厚みは１μｍ以下が好ましい。
この導電部５Ａ，５Ｂは、電解銅めっき法等のめっき法、スパッタリング法、蒸着法、または２つ以上の方法の組み合わせにより形成することができる。 Further, the thickness of the conductive portions 5A and 5B is preferably 1 to 20 μm, and sufficient conductivity can be obtained. In addition, when the electroconductive part 5 is made into the laminated structure of the gold surface, the thickness of the gold layer on the surface is preferably 1 μm or less.
The conductive portions 5A and 5B can be formed by a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

中間層６は、絶縁樹脂層４の一部を覆うように、導電部５Ｂと電気的に接続されるバンプ９が配置される位置、すなわち絶縁樹脂層４と導電部５Ｂの間に配される。この中間層６の材料としては、バンプ８，９をなす材料よりもヤング率の高い部材が好ましく、たとえば銅（Ｃｕ）やニッケル（Ｎｉ）、クロム（Ｃｒ）、亜鉛（Ｚｎ）、金（Ａｕ）、銀（Ａｇ）、アルミニウム（Ａｌ）、プラチナ（Ｐｔ）など、ヤング率が６０Ｇｐａより高い金属が好ましい。あるいはこれらを主成分とした合金、またはこれらの積層構造であっても構わない。中間層６は、ヤング率が６０Ｇｐａを下回るとバンプよりもヤング率が低くなってしまうため本発明の効果が得られなくなる。
この中間層６の高さ（厚さ）は５〜１００μｍが適当である。 The intermediate layer 6 is arranged so as to cover a part of the insulating resin layer 4 at a position where the bump 9 electrically connected to the conductive portion 5B is disposed, that is, between the insulating resin layer 4 and the conductive portion 5B. . As the material of the intermediate layer 6, a member having a higher Young's modulus than the material forming the bumps 8 and 9 is preferable. For example, copper (Cu), nickel (Ni), chromium (Cr), zinc (Zn), gold (Au ), Silver (Ag), aluminum (Al), platinum (Pt) and the like, metals having a Young's modulus higher than 60 Gpa are preferable. Alternatively, an alloy containing these as a main component or a laminated structure thereof may be used. If the Young's modulus is less than 60 Gpa, the Young's modulus becomes lower than that of the bump, so that the effect of the present invention cannot be obtained.
The height (thickness) of the intermediate layer 6 is suitably 5 to 100 μm.

このように、中間層６のヤング率を、バンプ８，９をなす材料よりも高い部材にすることで、半導体基板２の内域βに位置する第２接続部１０Ｂの剛性が、半導体基板２の外域αに位置する第１接続部１０Ａの剛性より高いものとなる。そうすると、実装基板から第２接続部１０Ｂのバンプ９が受ける応力が相対的に大きくなり、逆に第１接続部１０Ａのバンプ８にかかる応力が相対的に小さくなる。この結果、第１接続部１０Ａのバンプ８にかかる最大応力を小さくすることができ、半導体パッケージとして接続信頼性を向上させることができる。   Thus, by making the Young's modulus of the intermediate layer 6 higher than that of the material forming the bumps 8 and 9, the rigidity of the second connection portion 10 </ b> B located in the inner region β of the semiconductor substrate 2 can be increased. This is higher than the rigidity of the first connecting portion 10A located in the outer region α. Then, the stress applied to the bump 9 of the second connection portion 10B from the mounting substrate becomes relatively large, and conversely, the stress applied to the bump 8 of the first connection portion 10A becomes relatively small. As a result, the maximum stress applied to the bump 8 of the first connection portion 10A can be reduced, and the connection reliability as a semiconductor package can be improved.

この中間層６の形成方法としては、材料がニッケル、クロム、銅、亜鉛、金、銀の場合、電解めっき法が適している。また、材料がアルミニウム、亜鉛、金、銀、プラチナ、ニッケルの場合、ＰＶＤ法が適している。さらに、材料が銀、銅の場合、ペースト印刷法が適している。
また、中間層６は、アルミナ、ジルコニア、窒化珪素などのセラミック、あるいはアモルファスであっても良い。この場合の形成方法としては、個片の搭載あるいは個片を埋め込んだフィルムのラミネート法が適している。 As a method for forming the intermediate layer 6, when the material is nickel, chromium, copper, zinc, gold, or silver, an electrolytic plating method is suitable. Further, when the material is aluminum, zinc, gold, silver, platinum, or nickel, the PVD method is suitable. Further, when the material is silver or copper, a paste printing method is suitable.
The intermediate layer 6 may be ceramic such as alumina, zirconia, silicon nitride, or amorphous. As a forming method in this case, mounting of individual pieces or laminating a film in which the individual pieces are embedded is suitable.

また、これら絶縁樹脂層４及び導電部５Ａ，５Ｂの上には、必要に応じて封止樹脂層７を設けることができる。また、絶縁樹脂層４と導電部５Ｂの間に中間層６が配されている場合、中間層６も封止樹脂層７によって覆われる。したがって、封止樹脂層７は、中間層６を有する第２接続部１０Ｂ側が、中間層６の高さ（厚み）と略等しい分だけ表面が隆起した構成となる。   Further, a sealing resin layer 7 can be provided on the insulating resin layer 4 and the conductive portions 5A and 5B as necessary. Further, when the intermediate layer 6 is disposed between the insulating resin layer 4 and the conductive portion 5 </ b> B, the intermediate layer 6 is also covered with the sealing resin layer 7. Therefore, the sealing resin layer 7 has a configuration in which the surface of the second connecting portion 10B side having the intermediate layer 6 is raised by an amount substantially equal to the height (thickness) of the intermediate layer 6.

封止樹脂層７に適した部材は、絶縁樹脂層４に適する絶縁性部材と同じとすることができ、加えて難燃性に優れており、あるいは吸水性が低いとより好ましく、たとえば、ポリイミド樹脂、エポキシ樹脂、フェノール樹脂等が挙げられる。
また、封止樹脂層７の厚さは１〜５０μｍが適当である。
この封止樹脂層７の形成方法としては、たとえばスクリーン印刷法、スピンコート法、ラミネート法が好ましい。 The member suitable for the sealing resin layer 7 can be the same as the insulating member suitable for the insulating resin layer 4, and is preferably excellent in flame retardancy or low in water absorption. Resin, epoxy resin, phenol resin, etc. are mentioned.
Further, the thickness of the sealing resin layer 7 is suitably 1 to 50 μm.
As a method for forming the sealing resin layer 7, for example, a screen printing method, a spin coating method, or a laminating method is preferable.

封止樹脂層７は、前記導電部５と整合する位置に、バンプ８，９を搭載するための複数のバンプ用の開口部７ａ，７ｂを有し、前記開口部７ａ，７ｂは、前記半導体基板２の外域αに主に位置する第１開口部７ａと、内域βに位置する第２開口部７ｂとから構成されている。そして、少なくとも前記第１開口部７ａの一部は、前記第２開口部７ｂより大きな開口面積を有する。したがって、前記第１開口部７ａには、直径の大きい第１のバンプ８を配置し、前記第２開口部７ｂには、直径の小さい第２のバンプ９を配置する。   The sealing resin layer 7 has a plurality of bump openings 7a and 7b for mounting the bumps 8 and 9 at positions aligned with the conductive portion 5, and the openings 7a and 7b The first opening 7 a is mainly located in the outer area α of the substrate 2 and the second opening 7 b is located in the inner area β. At least a part of the first opening 7a has an opening area larger than that of the second opening 7b. Therefore, the first bump 8 having a large diameter is disposed in the first opening 7a, and the second bump 9 having a small diameter is disposed in the second opening 7b.

また、第１のバンプ８が位置する一部の第１開口部７ａの開口面積（すなわち、導電部５Ａの露出している面積）は、第２のバンプ９が位置する第２開口部７ｂの開口面積（すなわち、導電部５Ｂの露出している面積）よりも、たとえば２０％以上大きくするのが望ましい。   Further, the opening area of a part of the first opening 7a where the first bump 8 is located (that is, the exposed area of the conductive part 5A) is the same as that of the second opening 7b where the second bump 9 is located. For example, it is desirable that the opening area be 20% or more larger than the opening area (that is, the exposed area of the conductive portion 5B).

また、バンプ８，９の形成を容易にするため、図３に示すように、第１のバンプ８を配置する第１開口部７ａと第２のバンプ９を配置する第２開口部７ｂとの間隔は、前記第２開口部７ｂの配列ピッチよりも広くとるのが望ましい。たとえば、第１開口部７ａの開口面積を、第２開口部７ｂの開口面積よりもｘ％増やした場合、第１開口部７ａと第２開口部７ｂのピッチＰ１は、第２開口部７ｂ同士のピッチＰ２の０．２５ｘ％以上増加させるとよい。すなわち、Ｐ１＝（１＋０．２５ｘ）Ｐ２という式を満たす構成が望ましい。具体的には、第１開口部７ａの開口面積を４０％増やした場合、ピッチＰ１は１０％以上増加させる。   In order to facilitate the formation of the bumps 8 and 9, as shown in FIG. 3, a first opening 7a in which the first bump 8 is disposed and a second opening 7b in which the second bump 9 is disposed. The interval is preferably wider than the arrangement pitch of the second openings 7b. For example, when the opening area of the first opening 7a is increased by x% more than the opening area of the second opening 7b, the pitch P1 between the first opening 7a and the second opening 7b is the same between the second openings 7b. It is preferable to increase the pitch P2 by 0.25x% or more. That is, a configuration satisfying the expression P1 = (1 + 0.25x) P2 is desirable. Specifically, when the opening area of the first opening 7a is increased by 40%, the pitch P1 is increased by 10% or more.

ここで本質は、第１開口部７ａと第２開口部７ｂとの間に残る封止樹脂層７の幅Ｌ１を、第２開口部７ｂ同士のその幅Ｌ２と同程度かそれ以上に確保する、すなわちＬ１≧Ｌ２とすることにある。こうすることで、バンプ８，８を形成する時に隣接するバンプと連結してしまうという不良を回避することができる。   In essence, the width L1 of the sealing resin layer 7 remaining between the first opening 7a and the second opening 7b is ensured to be equal to or greater than the width L2 of the second openings 7b. That is, L1 ≧ L2. By doing so, it is possible to avoid a defect that the bumps 8 and 8 are connected to adjacent bumps when the bumps 8 and 8 are formed.

バンプ８，９は、外部基板と電気的に接続するための出力端子であり、導電部５に整合して搭載されている。本発明の場合、複数形成されたバンプ８，９の高さは何れも略等しいものとなっている。すなわち、バンプ８，９は、この封止樹脂層７に形成されたバンプ用の開口部７ａ，７ｂを介して前記導電部５に接合される。
このバンプ８，９は、たとえば半田または金等の材料によってボール状に形成され、特に半田が好ましい。半田は、鉛を含む組成であっても含まない組成であっても構わない。鉛を含まない組成としては、錫を主成分として、銀、銅、インジウム、亜鉛、ビスマスなどの元素を一つ、あるいは複数含む組成が好ましい。 The bumps 8 and 9 are output terminals for electrical connection with an external substrate, and are mounted in alignment with the conductive portion 5. In the case of the present invention, the heights of the plurality of formed bumps 8 and 9 are substantially equal. That is, the bumps 8 and 9 are joined to the conductive portion 5 through the bump openings 7 a and 7 b formed in the sealing resin layer 7.
The bumps 8 and 9 are formed in a ball shape with a material such as solder or gold, and solder is particularly preferable. The solder may have a composition containing lead or a composition not containing lead. As the composition not containing lead, a composition containing tin as a main component and one or more elements such as silver, copper, indium, zinc and bismuth is preferable.

また、バンプは、それぞれの高さを揃える必要がある。したがって、第１のバンプ８の体積を第２のバンプ９の体積よりも大きくするか、または第２のバンプ９の体積を第１のバンプ８の体積よりも小さくしなければならない。あるいは第１のバンプ８と第２のバンプ９の径は変えずに同じとし、バンプを形成する半田の量をコントロールして、高さを変えるようにしても良い。このため、バンプの形成方法としては、電解めっき法あるいはペーストディスペンス法が好ましい。
なお、封止樹脂層７の表面凹凸が大きいため、ペースト印刷法は適さない。また、同一サイズの半田ボールを搭載することに有利なボール搭載法は適さないが、中間層６の厚さが薄ければ、ボール搭載法を適用することもできる。そして、何れの方法も、その後リフローすることでバンプが得られる。 Moreover, it is necessary to arrange the bumps at the same height. Therefore, it is necessary to make the volume of the first bump 8 larger than the volume of the second bump 9 or make the volume of the second bump 9 smaller than the volume of the first bump 8. Alternatively, the diameters of the first bumps 8 and the second bumps 9 may be the same without changing, and the height may be changed by controlling the amount of solder forming the bumps. For this reason, as a bump forming method, an electrolytic plating method or a paste dispensing method is preferable.
In addition, since the surface unevenness | corrugation of the sealing resin layer 7 is large, the paste printing method is not suitable. Also, a ball mounting method that is advantageous for mounting solder balls of the same size is not suitable, but if the intermediate layer 6 is thin, the ball mounting method can be applied. In either method, the bump is obtained by reflowing thereafter.

また、半導体基板２の外域αに主に位置する少なくとも一部の第１開口部７ａには、第２のバンプ９が受ける応力と同等かそれ以上の応力が加わる場合があるため、バンプに亀裂がより発生しやすい。このため、亀裂が発生しても電気的な接続不良が発生しないように、第１のバンプ８の直径は第２のバンプ９の直径よりも大きくしておく必要がある。このように、半導体基板２の外域αに配置される第１のバンプ８の直径を大きくすることで強度が向上するので、半導体パッケージと実装基板との接続信頼性（接続寿命）を向上させることができる。したがって、アンダーフィルを必ずしもする必要はなくなる。一方、半導体基板２の内域βに位置する第２開口部７ｂに配置された第２のバンプ９に加わる応力は小さいため、亀裂が入りにくく、強度が弱い微小なバンプであっても接続信頼性には殆ど影響しない。このため、使用環境下における導電部とバンプからなる配線のインピーダンス変化が小さいので、周波数の高い信号の伝達に適する。   Further, since the stress that is equal to or higher than the stress that the second bump 9 receives may be applied to at least a part of the first opening 7a that is mainly located in the outer region α of the semiconductor substrate 2, the bump is cracked. Is more likely to occur. For this reason, the diameter of the first bump 8 needs to be larger than the diameter of the second bump 9 so that an electrical connection failure does not occur even if a crack occurs. Thus, since the strength is improved by increasing the diameter of the first bump 8 disposed in the outer region α of the semiconductor substrate 2, the connection reliability (connection life) between the semiconductor package and the mounting substrate is improved. Can do. Therefore, it is not always necessary to underfill. On the other hand, since the stress applied to the second bump 9 disposed in the second opening 7b located in the inner region β of the semiconductor substrate 2 is small, even if it is a minute bump that is hard to crack and has a weak strength, the connection reliability Has almost no effect on sex. For this reason, since the impedance change of the wiring composed of the conductive portion and the bump in the use environment is small, it is suitable for transmission of a signal having a high frequency.

この第１のバンプ８はサイズが大きい分、電気抵抗が第２のバンプ９より小さいため、大電流を流す必要のある、たとえばＩＣの電源用端子などの電極に適している。一方、パッケージの中央に位置する第２のバンプ８は、頂点の高さが第１のバンプ８と同じで、かつ、直径が小さい微小なバンプで良いので、ピッチを狭く（小さく）できる。これにより、パッケージの多ピン化に非常に有利になる。
また、外域αに位置する大きな第１のバンプ８によるセルフアライメント効果が大きいので、パッケージの基板実装において、位置合わせ精度がラフであっても、内域βに位置する狭ピッチな第２のバンプ８を接続することができる。
以上の構成された半導体装置１は、その後、バンプ８，９面を実装基板１０に形成された導電部に対向して配置し、半導体装置１が有するバンプ８，９と実装基板が有する導電部を接触させて実装する。 Since the first bump 8 is larger in size and has an electric resistance smaller than that of the second bump 9, it is suitable for an electrode such as an IC power supply terminal that requires a large current to flow. On the other hand, the second bump 8 located at the center of the package may be a fine bump having the same apex height as that of the first bump 8 and a small diameter, so that the pitch can be made narrow (small). This is very advantageous for increasing the number of pins of the package.
In addition, since the large first bump 8 located in the outer area α has a large self-alignment effect, the second bump with a narrow pitch located in the inner area β even if the alignment accuracy is rough in the package mounting of the package. 8 can be connected.
In the semiconductor device 1 configured as described above, the bumps 8 and 9 are then disposed so as to face the conductive portions formed on the mounting substrate 10, and the bumps 8 and 9 included in the semiconductor device 1 and the conductive portions included in the mounting substrate are disposed. Mount with contact.

このように半導体装置１は、ポストや応力緩和機能を有する厚い樹脂層といった厚さの増加を伴わない簡単な構造であるので、その作製に多くの手間や製造コストを要することない。また、半導体装置１を実装基板に実装した場合に、半導体装置１に加わる機械荷重あるいは熱応力を、第２開口部より大きな開口面積を有する第１開口部に配されるバンプによって緩和・吸収を図ることができる。しかも、半導体基板２の外域αに発生する応力を内域βに位置する接続部に分散させ、クラックの発生を抑制して実装基板との接続寿命を向上させることができる。
したがって、バンプ強度の増強及びバンプの狭ピッチ化を同時に実現できるため、基板実装後における優れた耐久性と高い信頼性とを兼ね備え、かつ、多ピン化に対応できる小型の電子部品及び電子装置を提供することができる。 Thus, since the semiconductor device 1 has a simple structure that does not increase in thickness, such as a post or a thick resin layer having a stress relaxation function, it does not require much labor and manufacturing cost. Further, when the semiconductor device 1 is mounted on the mounting substrate, the mechanical load or thermal stress applied to the semiconductor device 1 is reduced and absorbed by the bumps arranged in the first opening having a larger opening area than the second opening. Can be planned. In addition, the stress generated in the outer region α of the semiconductor substrate 2 can be dispersed in the connection portion located in the inner region β, and the generation of cracks can be suppressed to improve the connection life with the mounting substrate.
Therefore, the bump strength can be increased and the bump pitch can be reduced at the same time. Therefore, a compact electronic component and an electronic device that have both excellent durability after mounting on the substrate and high reliability and can cope with the increase in the number of pins. Can be provided.

次に、本発明における半導体装置の製造方法の一例について説明する。
図４及び図５は、その製造方法の一例を工程順に示す断面図である。
まず、半導体基板２を用意する。この半導体基板２としては、たとえば、一面に電極３が配された半導体ウエハがある［図４（ａ）参照］。
次いで、半導体基板２を覆い、前記電極３が露呈するように開口部４ａを有する絶縁樹脂層４を形成する［図４（ｂ）参照］。絶縁樹脂層４に使われる材料は、たとえば、感光性をもち、フォトリソグラフィ技術を利用してパターニングすることにより形成することができる。この絶縁樹脂層４は、たとえばスピンコート法、キャスティング法、ディスペンス法等によって半導体基板２上に塗布したり、印刷法でパターン形成したり、さらに、シート状の材料を貼ることで形成したりするものでも良い。 Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described.
4 and 5 are sectional views showing an example of the manufacturing method in the order of steps.
First, the semiconductor substrate 2 is prepared. An example of the semiconductor substrate 2 is a semiconductor wafer having an electrode 3 disposed on one surface [see FIG. 4A].
Next, an insulating resin layer 4 having an opening 4a is formed so as to cover the semiconductor substrate 2 and expose the electrode 3 [see FIG. 4B]. The material used for the insulating resin layer 4 is, for example, photosensitive and can be formed by patterning using a photolithography technique. The insulating resin layer 4 is formed on the semiconductor substrate 2 by, for example, spin coating, casting, or dispensing, or by patterning by printing, or by pasting a sheet-like material. Things can be used.

次に、絶縁樹脂層４の一部を覆うように、第２のバンプ９は配置される位置に中間層６を形成する［図４（ｃ）参照］。中間層６の形成手法としては、電解めっき法、ラミネート法、ペースト印刷法などが挙げられる。
また、絶縁樹脂層４の一部及び中間層６の一部をそれぞれ覆うように、前記開口部４ａを通して前記電極３と電気的に接続され、かつ、外部基板との接続を可能とする第１のバンプ８又は第２のバンプ９が搭載される導電部５（５Ａ，５Ｂ）を形成する［図５（ａ）参照］。導電部５（５Ａ，５Ｂ）の形成手法としては、電解めっき法、無電解めっき法、スパッタ法、蒸着法などが挙げられるが、配線厚さが１〜２０μｍの場合は電解めっきがより好ましい。 Next, an intermediate layer 6 is formed at a position where the second bump 9 is disposed so as to cover a part of the insulating resin layer 4 [see FIG. 4C]. Examples of the method for forming the intermediate layer 6 include an electrolytic plating method, a laminating method, and a paste printing method.
The first electrode is electrically connected to the electrode 3 through the opening 4a so as to cover a part of the insulating resin layer 4 and a part of the intermediate layer 6 and can be connected to an external substrate. The conductive portion 5 (5A, 5B) on which the bump 8 or the second bump 9 is mounted is formed [see FIG. 5A]. Examples of the method for forming the conductive portion 5 (5A, 5B) include an electrolytic plating method, an electroless plating method, a sputtering method, and a vapor deposition method. When the wiring thickness is 1 to 20 μm, electrolytic plating is more preferable.

さらに、絶縁樹脂層４及び導電部５（５Ａ，５Ｂ）を覆い、バンプ８，９を前記導電部５（５Ａ，５Ｂ）に直接接触させるための開口部７ａ，７ｂを有する封止樹脂層７を形成する［図５（ｂ）参照］。この開口部７ａ，７ｂは、たとえば図５（ｂ）に示す二点鎖線を境として半導体基板２の一面における左側を外域α、右側を内域βとすると、外域αに主に位置し、第１のバンプ８の形成を可能とする第１開口部７ａと、前記半導体基板２の内域βに位置し、第２のバンプ９の形成を可能とする第２開口部７ｂとから構成され、前記第１開口部７ａは前記第２開口部７ｂより大きな開口面積を有している。   Further, the sealing resin layer 7 that covers the insulating resin layer 4 and the conductive portion 5 (5A, 5B) and has openings 7a, 7b for directly contacting the bumps 8, 9 with the conductive portion 5 (5A, 5B). [See FIG. 5B]. The openings 7a and 7b are mainly located in the outer region α, assuming that the left side of the one surface of the semiconductor substrate 2 is the outer region α and the right side is the inner region β with the two-dot chain line shown in FIG. A first opening 7a that enables the formation of one bump 8 and a second opening 7b that is located in the inner region β of the semiconductor substrate 2 and that allows the formation of the second bump 9; The first opening 7a has a larger opening area than the second opening 7b.

その後、封止樹脂層７の第１開口部７ａを通して導電部５Ａと接続するように第１のバンプ８を搭載すると共に、同第２開口部７ｂを通して導電部５Ｂと接続するように第２のバンプ９を搭載することにより、図１及び図２に示すような半導体装置１を得ることができる。
そして、この半導体装置１を所定の寸法にダイシングすることにより、所望の半導体チップが得られる。 Thereafter, the first bump 8 is mounted so as to be connected to the conductive portion 5A through the first opening 7a of the sealing resin layer 7, and the second bump is set so as to be connected to the conductive portion 5B through the second opening 7b. By mounting the bumps 9, the semiconductor device 1 as shown in FIGS. 1 and 2 can be obtained.
A desired semiconductor chip is obtained by dicing the semiconductor device 1 to a predetermined size.

以上のように本発明の半導体装置は、バンプの高さが略等しく、外域αにおいてバンプの面積を大きくすることができるので、バンプ強度の増強及びバンプの狭ピッチ化を同時に実現でき、基板実装後の外周領域における優れた耐久性と高い信頼性とを兼ね備え、さらに多ピン化に対応できるものとなる。
また、本発明の半導体装置の製造工程は従来と同じままで良いので、作製時間及び材料費の増加はない。しかも、パッケージが厚くならない構造であるので、薄型化への不利がない。 As described above, the semiconductor device according to the present invention has substantially the same bump height and can increase the bump area in the outer region α. Therefore, the bump strength can be increased and the bump pitch can be reduced at the same time. It has excellent durability and high reliability in the subsequent outer peripheral region, and can cope with the increase in the number of pins.
Further, since the manufacturing process of the semiconductor device of the present invention may be the same as the conventional one, there is no increase in manufacturing time and material cost. In addition, since the package does not become thick, there is no disadvantage in reducing the thickness.

また、図１及び図２に示す例では、中間層６を有する第２接続部１０Ｂ側の封止樹脂層７の表面が、中間層６の高さ（厚み）と略等しい分だけ隆起した構成となっているが、本発明の半導体装置はこれに限定されない。
すなわち、図６に示すように、たとえば図６中に示す二点鎖線を境として半導体基板の一面における左側を外域α、右側を内域βとすると、外域αに位置する導電部５Ａを覆う封止樹脂層１７の厚さを、内域βに位置する導電部５Ｂを覆う封止樹脂層１７部分に比べて肉厚とし、半導体基板２上に配した封止樹脂層１７形成後の表面を平滑に形成したものとしても良い。したがって、第二の半導体装置１１は、第２接続部１０Ｂは第一の半導体装置１と変わらないが、第１接続部２０Ａが、半導体基板２の外域αに位置する導電部５Ａと、封止樹脂層１７の肉厚部分に形成された第１開口部１７ａを介してこの導電部５Ａと電気的に接続される第１のバンプ１８とから構成されたものとなっている。 In the example shown in FIGS. 1 and 2, the surface of the sealing resin layer 7 on the second connecting portion 10 </ b> B side having the intermediate layer 6 is raised by an amount substantially equal to the height (thickness) of the intermediate layer 6. However, the semiconductor device of the present invention is not limited to this.
That is, as shown in FIG. 6, for example, assuming that the left side of one surface of the semiconductor substrate is the outer region α and the right side is the inner region β with the two-dot chain line shown in FIG. The thickness of the stopping resin layer 17 is made thicker than that of the sealing resin layer 17 covering the conductive portion 5B located in the inner region β, and the surface after forming the sealing resin layer 17 disposed on the semiconductor substrate 2 is formed. It may be formed smoothly. Therefore, in the second semiconductor device 11, the second connection portion 10B is the same as the first semiconductor device 1, but the first connection portion 20A is sealed with the conductive portion 5A located in the outer region α of the semiconductor substrate 2. The first bump 18 is electrically connected to the conductive portion 5A through a first opening 17a formed in the thick portion of the resin layer 17.

こうすることで、バンプ形成法として、容易で安価なペースト印刷法を適用することができる。
また、封止樹脂層１７を形成する方法としては、スクリーン印刷法あるいはモールド法、ラミネート法が適している。また、封止樹脂層１７を形成する方法としてスピンコート法を用いる場合は、複数回塗布することで、必要な厚みを得ることが可能である。そして、その後に封止樹脂層１７の表面を研磨することで、平滑度をさらに向上させても良い。 By doing so, an easy and inexpensive paste printing method can be applied as the bump forming method.
As a method for forming the sealing resin layer 17, a screen printing method, a molding method, or a laminating method is suitable. Further, when the spin coating method is used as a method for forming the sealing resin layer 17, it is possible to obtain a necessary thickness by applying a plurality of times. Then, the smoothness may be further improved by polishing the surface of the sealing resin layer 17 thereafter.

また、本発明の半導体装置は、図７に示すように、中間層２６が絶縁樹脂層２４の下方に配された構成としても良い。したがって、第三の半導体装置２１は、第１接続部１０Ａは第一の半導体装置１と変わらないが、第２接続部３０Ｂが、たとえば図７示す二点鎖線を境として半導体基板の一面における左側を外域α、右側を内域βとすると、内域βに位置する導電部５Ｂと、封止樹脂層２７に形成された第２開口部２７ａを介してこの導電部５Ｂと電気的に接続される第２のバンプ９と、この第２のバンプ９が配置される位置における半導体基板２の一面と絶縁樹脂層２４の間に配された中間層２６とから構成されたものとなっている。したがって、絶縁樹脂層２４及び封止樹脂層２７は、中間層２６を有する第２接続部３０Ｂ側が、中間層２６の高さ（厚み）と略等しい分だけ表面が隆起した構成となる。   Further, the semiconductor device of the present invention may have a configuration in which the intermediate layer 26 is disposed below the insulating resin layer 24 as shown in FIG. Therefore, in the third semiconductor device 21, the first connection portion 10A is the same as that of the first semiconductor device 1, but the second connection portion 30B is, for example, the left side on one surface of the semiconductor substrate with the two-dot chain line shown in FIG. Is the outer region α and the right side is the inner region β, the conductive portion 5B located in the inner region β is electrically connected to the conductive portion 5B via the second opening 27a formed in the sealing resin layer 27. The second bump 9 and the intermediate layer 26 disposed between the one surface of the semiconductor substrate 2 and the insulating resin layer 24 at the position where the second bump 9 is disposed. Therefore, the insulating resin layer 24 and the sealing resin layer 27 have a configuration in which the surfaces of the second connecting portion 30B side having the intermediate layer 26 are raised by an amount substantially equal to the height (thickness) of the intermediate layer 26.

こうすることで、中間層２６と導電部５Ｂは電気的に接続されないため、図８に示すように、複数の第２のバンプ９に跨る大きな連続体を形成する中間層２６とすることができる。この場合、第一の半導体装置１よりも微細に中間層をパターン形成する必要がなくなるので、中間層の形成がより容易になる。
また、第三の半導体装置２１では、第二の半導体装置１１のように、半導体基板２上に配した封止樹脂層２７形成後の表面を平滑に形成したものとしても良い。 By doing so, since the intermediate layer 26 and the conductive portion 5B are not electrically connected, as shown in FIG. 8, the intermediate layer 26 can be formed to form a large continuous body extending over the plurality of second bumps 9. . In this case, it is not necessary to pattern the intermediate layer more finely than the first semiconductor device 1, so that it is easier to form the intermediate layer.
Further, in the third semiconductor device 21, like the second semiconductor device 11, the surface after forming the sealing resin layer 27 arranged on the semiconductor substrate 2 may be formed smoothly.

また、本発明の半導体装置は、図９に示すように、中間層２６が導電部５Ｂの上に配された構成、すなわち、中間層２６が導電部５Ｂと第２のバンプ９の間に配された構成としても良い。したがって、第四の半導体装置３１は、第１接続部１０Ａは第一の半導体装置１と変わらないが、第２接続部４０Ｂが、たとえば図９示す二点鎖線を境として半導体基板の一面における左側を外域α、右側を内域βとすると、内域βに位置し、第２のバンプ９が配置される位置の絶縁樹脂層４の上方に配された導電部３５Ｂと、この導電部３５Ｂの上方に配された中間層３６と、封止樹脂層７に形成された第２開口部７ａを介してこの中間層３６と電気的に接続される第２のバンプ９とから構成されたものとなっている。したがって、封止樹脂層７は、中間層３６を有する第２接続部４０Ｂ側が、中間層３６の高さ（厚み）と略等しい分だけ表面が隆起した構成となる。   Further, as shown in FIG. 9, the semiconductor device of the present invention has a configuration in which the intermediate layer 26 is disposed on the conductive portion 5B, that is, the intermediate layer 26 is disposed between the conductive portion 5B and the second bump 9. It is good also as the structure made. Therefore, in the fourth semiconductor device 31, the first connection portion 10A is not different from the first semiconductor device 1, but the second connection portion 40B is on the left side of one surface of the semiconductor substrate with the two-dot chain line shown in FIG. 9 as a boundary, for example. Is the outer region α, and the right side is the inner region β, the conductive portion 35B located in the inner region β and disposed above the insulating resin layer 4 at the position where the second bump 9 is disposed, and the conductive portion 35B An intermediate layer 36 disposed above and a second bump 9 electrically connected to the intermediate layer 36 through a second opening 7a formed in the sealing resin layer 7 It has become. Therefore, the sealing resin layer 7 has a configuration in which the surface of the second connecting portion 40B side having the intermediate layer 36 is raised by an amount substantially equal to the height (thickness) of the intermediate layer 36.

こうすることで、導電部５Ａ，５Ｂを形成するときの表面は、第一の半導体装置１と比べて平坦になるため、導電部５Ａ，５Ｂを微細なパターンで形成することが容易にできる。また、第一の半導体装置１では、中間層が高すぎると導電部５Ｂを微細に形成することができないため、あまり中間層を高くすることができなかったが、第四の半導体装置３１では、中間層３６は導電部５Ｂを形成した後に形成するため、中間層３６の高さを第一の半導体装置１よりも高く形成することが可能となる。
中間層３６は、導電部５Ｂと第２のバンプ９とを電気的に接続することから、電気抵抗率が低く、かつ第２のバンプ９との接合が容易な金属がより好ましい。具体的には、銅や銀、金、ニッケルが好ましい。または、これらの合金あるいは積層構造でも良い。さらに、銅や銀、金などを含む導電性ペーストを用いてもよい。
中間層３６を高く形成することで、第２のバンプ９の剛性はよりアップするので、その結果、第１のバンプ８に加わる最大応力を小さくすることができる。このため、接続信頼性はより向上したものとなる。 By doing so, the surface when the conductive portions 5A and 5B are formed becomes flat as compared with the first semiconductor device 1, so that the conductive portions 5A and 5B can be easily formed in a fine pattern. In the first semiconductor device 1, if the intermediate layer is too high, the conductive portion 5 </ b> B cannot be finely formed. Therefore, the intermediate layer cannot be increased too much, but in the fourth semiconductor device 31, Since the intermediate layer 36 is formed after the conductive portion 5B is formed, the intermediate layer 36 can be formed higher than the first semiconductor device 1.
Since the intermediate layer 36 electrically connects the conductive portion 5B and the second bump 9, a metal that has a low electrical resistivity and can be easily joined to the second bump 9 is more preferable. Specifically, copper, silver, gold, and nickel are preferable. Or these alloys or laminated structure may be sufficient. Furthermore, a conductive paste containing copper, silver, gold, or the like may be used.
By forming the intermediate layer 36 high, the rigidity of the second bump 9 is further increased. As a result, the maximum stress applied to the first bump 8 can be reduced. For this reason, the connection reliability is further improved.

さらに、本発明の半導体装置は、第２接続部１０Ｂの剛性を高めるための中間層に代えて、図１０に示すように、バンプ４９の内部に補強部材４６を配した構成としても良い。したがって、第五の半導体装置４１は、第１接続部１０Ａは第一の半導体装置１と変わらないが、第２接続部５０Ｂが、たとえば図１０示す二点鎖線を境として半導体基板の一面における左側を外域α、右側を内域βとすると、内域βに位置し、第２のバンプ４９が配置される位置の絶縁樹脂層４の上方に配された導電部４５Ｂと、この導電部４５Ｂの上方に配された補強部材４６と、この補強部材４６を包み込み、封止樹脂層４７に形成された第２開口部７ａを介して導電部４５Ｂと電気的に接続される第２のバンプ４９とから構成されたものとなっている。すなわち、第２接続部５０Ｂは、導電部４５Ｂと補強部材４６と第２のバンプ４９とから構成されている。   Furthermore, the semiconductor device of the present invention may have a configuration in which a reinforcing member 46 is arranged inside the bump 49 as shown in FIG. 10 instead of the intermediate layer for increasing the rigidity of the second connection portion 10B. Therefore, in the fifth semiconductor device 41, the first connection portion 10A is the same as that of the first semiconductor device 1, but the second connection portion 50B is, for example, the left side of one surface of the semiconductor substrate with the two-dot chain line shown in FIG. Is the outer region α and the right side is the inner region β, the conductive portion 45B located in the inner region β and disposed above the insulating resin layer 4 at the position where the second bump 49 is disposed, and the conductive portion 45B A reinforcing member 46 disposed above, and a second bump 49 that wraps around the reinforcing member 46 and is electrically connected to the conductive portion 45B through the second opening 7a formed in the sealing resin layer 47. It is made up of. That is, the second connection portion 50 </ b> B includes the conductive portion 45 </ b> B, the reinforcing member 46, and the second bump 49.

この補強部材４６は、少なくとも頂点がバンプ４９で覆われている必要があるため、材料としては、中間層と同様に、バンプ４９との接合が容易で、バンプ４９をなす材料よりもヤング率の高い部材が好ましく、たとえば銅（Ｃｕ）や銀（Ａｇ）、金（Ａｕ）、ニッケル（Ｎｉ）など、ヤング率が６０Ｇｐａより高い金属が好ましい。
また、補強部材４６の高さ（厚さ）は１０〜２００μｍが適当である。
このように、補強部材４６のヤング率を、バンプ４９をなす材料よりも高い部材にすることで、半導体基板２の内域βに位置する第２接続部５０Ｂの剛性が、半導体基板２の外域αに位置する第１接続部１０Ａの剛性より高いものとなる。 Since this reinforcing member 46 needs to be covered at least at the apex by the bump 49, the material can be easily joined to the bump 49 like the intermediate layer, and has a Young's modulus higher than that of the material forming the bump 49. A high member is preferable, for example, a metal having a Young's modulus higher than 60 Gpa, such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), or the like is preferable.
Further, the height (thickness) of the reinforcing member 46 is suitably 10 to 200 μm.
As described above, by making the Young's modulus of the reinforcing member 46 higher than that of the material forming the bump 49, the rigidity of the second connection portion 50 </ b> B located in the inner region β of the semiconductor substrate 2 can be increased. It becomes higher than the rigidity of the first connecting portion 10A located at α.

補強部材４６の形成方法としては、電解めっき法のほかに、ラミネートした金属フィルムをエッチングして形成しても良いし、導電性ペーストを用いても良い。
また、補強部材４６は、少なくとも表面がバンプ４９との接合が容易な金属であれば良く、内部が別の金属やセラミックス、アモルファスであっても構わない。この場合の補強部材４６の形成方法としては、内部の部材を導電部４５Ｂ上に搭載した後、蒸着法、スパッタ法、電解めっき法、あるいは無電解めっき法にてその表面を覆う。また、ワイヤバンプ法（スタッドバンプ法ともいう）を用いて、金あるいはアルミニウム、銅などの突起にしても良い。 As a method for forming the reinforcing member 46, in addition to the electrolytic plating method, a laminated metal film may be formed by etching, or a conductive paste may be used.
Further, the reinforcing member 46 may be any metal as long as at least the surface can be easily bonded to the bump 49, and the inside may be another metal, ceramics, or amorphous. As a method for forming the reinforcing member 46 in this case, an internal member is mounted on the conductive portion 45B, and then the surface is covered by a vapor deposition method, a sputtering method, an electrolytic plating method, or an electroless plating method. Further, a wire bump method (also referred to as a stud bump method) may be used to form protrusions such as gold, aluminum, or copper.

こうすることで、導電部５Ａ，４５Ｂを形成するときの表面は、第一の半導体装置１と比べて平坦になるため、導電部５Ａ，４５Ｂを微細なパターンで形成することが容易にできる。さらに、封止樹脂層４７の表面も平坦であるので、バンプ形成法として、容易で安価なペースト印刷法を適用することができる。   By doing so, the surface when the conductive portions 5A and 45B are formed becomes flat as compared with the first semiconductor device 1, so that the conductive portions 5A and 45B can be easily formed in a fine pattern. Furthermore, since the surface of the sealing resin layer 47 is also flat, an easy and inexpensive paste printing method can be applied as the bump forming method.

本発明は、たとえば携帯電話やデジタルカメラ、ノートパソコンなど、小型で高密度な電子部品を必要とする電子装置に適用できる。また、ウエハレベルＣＳＰに限らず、バンプを介して接続されるＢＧＡパッケージ全般、あるいはフリップチップにも適用できる。   The present invention can be applied to electronic devices that require small and high-density electronic components such as mobile phones, digital cameras, and notebook computers. Further, the present invention can be applied not only to the wafer level CSP but also to all BGA packages connected via bumps or flip chip.

本発明に係る第一の半導体装置の構造例を示す平面図である。It is a top view which shows the structural example of the 1st semiconductor device which concerns on this invention. 図１のＩ−Ｉ線における断面図である。It is sectional drawing in the II line | wire of FIG. 図１に示すバンプ用の開口部の構成を説明する平面図である。It is a top view explaining the structure of the opening part for bumps shown in FIG. 図１に示す半導体装置の製造方法の一例を工程順に示す断面図である。FIG. 2 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 図４の次工程を順に示す断面図である。It is sectional drawing which shows the next process of FIG. 4 in order. 本発明に係る第二の半導体装置の構造例を示す断面図である。It is sectional drawing which shows the structural example of the 2nd semiconductor device which concerns on this invention. 本発明に係る第三の半導体装置の構造例を示す断面図である。It is sectional drawing which shows the structural example of the 3rd semiconductor device which concerns on this invention. 図７に示す半導体装置における中間層の構成を説明する平面図である。FIG. 8 is a plan view illustrating a configuration of an intermediate layer in the semiconductor device illustrated in FIG. 7. 本発明に係る第四の半導体装置の構造例を示す断面図である。It is sectional drawing which shows the structural example of the 4th semiconductor device which concerns on this invention. 本発明に係る第五の半導体装置の構造例を示す断面図である。It is sectional drawing which shows the structural example of the 5th semiconductor device which concerns on this invention. 従来の半導体装置の構造例を示す断面図である。It is sectional drawing which shows the structural example of the conventional semiconductor device.

符号の説明Explanation of symbols

α 外域、β 内域、１ 半導体装置、２ 半導体基板、３ 電極、４ 絶縁樹脂層、４ａ （電極用）開口部、５Ａ，５Ｂ 導電部、６ 中間層、７ 封止樹脂層、７ａ （バンプ用）第１開口部、７ｂ （バンプ用）第２開口部、８ 第１のバンプ、９ 第２のバンプ、１０Ａ 第１接続部、１０Ｂ 第２接続部。
α outer region, β inner region, 1 semiconductor device, 2 semiconductor substrate, 3 electrode, 4 insulating resin layer, 4a (for electrode) opening, 5A, 5B conductive portion, 6 intermediate layer, 7 sealing resin layer, 7a (bump 1st opening, 7b (for bump) 2nd opening, 8 1st bump, 9 2nd bump, 10A 1st connection part, 10B 2nd connection part.

Claims (10)

一面に電極を配してなる半導体基板と、
前記半導体基板の一面を覆うように配され、前記電極と整合する位置に電極用の開口部を有する絶縁樹脂層と、
前記絶縁樹脂層の一部を覆うように配され、前記開口部を通して前記電極と電気的に接続される導電部を備えた複数の接続部と、
を少なくとも備える半導体装置であって、
前記接続部のうち、前記半導体基板の内域に配された少なくとも一つは、前記半導体基板の外域に配されたものより剛性が高いことを特徴とする半導体装置。 A semiconductor substrate having electrodes on one surface;
An insulating resin layer disposed so as to cover one surface of the semiconductor substrate and having an electrode opening at a position aligned with the electrode;
A plurality of connecting portions provided to cover a part of the insulating resin layer, and having a conductive portion electrically connected to the electrode through the opening;
A semiconductor device comprising at least
At least one of the connecting portions disposed in the inner region of the semiconductor substrate has higher rigidity than that disposed in the outer region of the semiconductor substrate. 前記剛性の高い接続部は、前記導電部の上方に配されるバンプと、前記バンプの下方に配される中間層を備え、
前記中間層は、前記バンプよりもヤング率が高い材料からなることを特徴とする請求項１に記載の半導体装置。 The highly rigid connection portion includes a bump disposed above the conductive portion and an intermediate layer disposed below the bump,
The semiconductor device according to claim 1, wherein the intermediate layer is made of a material having a Young's modulus higher than that of the bump. 前記中間層は、前記半導体基板の一面と前記絶縁樹脂層の間に配されていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the intermediate layer is disposed between one surface of the semiconductor substrate and the insulating resin layer. 前記中間層は、前記導電部と前記バンプの間に配されていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the intermediate layer is disposed between the conductive portion and the bump. 前記中間層は、前記絶縁樹脂層と前記導電部の間に配されていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the intermediate layer is disposed between the insulating resin layer and the conductive portion. 前記絶縁樹脂層及び前記導電部を覆うように封止樹脂層を備え、
前記封止樹脂層は表面が平滑であることを特徴とする請求項５に記載の半導体装置。 A sealing resin layer is provided so as to cover the insulating resin layer and the conductive part,
The semiconductor device according to claim 5, wherein the sealing resin layer has a smooth surface. 前記中間層は、連続体であることを特徴とする請求項２乃至６の何れか１項に記載の半導体装置。   The semiconductor device according to claim 2, wherein the intermediate layer is a continuous body. 前記剛性の高い接続部は、前記導電部の上方に配されるバンプと、前記バンプの内部に配される補強部材をさらに備えており、
前記補強部材は、前記バンプよりもヤング率が高い材料からなることを特徴とする請求項１に記載の半導体装置。 The highly rigid connection portion further includes a bump disposed above the conductive portion, and a reinforcing member disposed inside the bump,
The semiconductor device according to claim 1, wherein the reinforcing member is made of a material having a Young's modulus higher than that of the bump. 前記中間層もしくは前記補強部材のヤング率は、６０Ｇｐａ以上であることを特徴とする請求項２乃至８の何れか１項に記載の半導体装置。   9. The semiconductor device according to claim 2, wherein a Young's modulus of the intermediate layer or the reinforcing member is 60 Gpa or more. 前記請求項１乃至９の何れか１項に記載の半導体装置を用いたことを特徴とする電子装置。
An electronic device using the semiconductor device according to claim 1.
JP2006061015A 2006-03-07 2006-03-07 Semiconductor device and electronic apparatus Withdrawn JP2007242783A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227355A (en) * 2007-03-15 2008-09-25 Shinko Electric Ind Co Ltd Electronic equipment and method for manufacturing the same
WO2010067481A1 (en) * 2008-12-10 2010-06-17 パナソニック株式会社 Semiconductor integrated circuit device and method for designing the same
JP2010272716A (en) * 2009-05-22 2010-12-02 Fujitsu Ten Ltd Circuit part
US8759941B2 (en) 2008-12-10 2014-06-24 Panasonic Corporation Semiconductor integrated circuit device and method for designing the same
US9490232B2 (en) 2013-12-09 2016-11-08 Fujitsu Limited Electronic apparatus and method for fabricating the same
CN114649286A (en) * 2022-05-19 2022-06-21 甬矽电子(宁波)股份有限公司 Fan-out type packaging structure and fan-out type packaging method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227355A (en) * 2007-03-15 2008-09-25 Shinko Electric Ind Co Ltd Electronic equipment and method for manufacturing the same
WO2010067481A1 (en) * 2008-12-10 2010-06-17 パナソニック株式会社 Semiconductor integrated circuit device and method for designing the same
US8759941B2 (en) 2008-12-10 2014-06-24 Panasonic Corporation Semiconductor integrated circuit device and method for designing the same
JP2010272716A (en) * 2009-05-22 2010-12-02 Fujitsu Ten Ltd Circuit part
US9490232B2 (en) 2013-12-09 2016-11-08 Fujitsu Limited Electronic apparatus and method for fabricating the same
US9530745B2 (en) 2013-12-09 2016-12-27 Fujitsu Limited Electronic apparatus and method for fabricating the same
US9761552B2 (en) 2013-12-09 2017-09-12 Fujitsu Limited Electronic apparatus and method for fabricating the same
US9812418B2 (en) 2013-12-09 2017-11-07 Fujitsu Limited Electronic apparatus and method for fabricating the same
CN114649286A (en) * 2022-05-19 2022-06-21 甬矽电子(宁波)股份有限公司 Fan-out type packaging structure and fan-out type packaging method

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