SG11201606399VA - Method and process for emib chip interconnections - Google Patents

Method and process for emib chip interconnections

Info

Publication number
SG11201606399VA
SG11201606399VA SG11201606399VA SG11201606399VA SG11201606399VA SG 11201606399V A SG11201606399V A SG 11201606399VA SG 11201606399V A SG11201606399V A SG 11201606399VA SG 11201606399V A SG11201606399V A SG 11201606399VA SG 11201606399V A SG11201606399V A SG 11201606399VA
Authority
SG
Singapore
Prior art keywords
emib
chip interconnections
interconnections
chip
emib chip
Prior art date
Application number
SG11201606399VA
Inventor
Rajendra C Dias
Manish Dubey
Emre Armagan
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG11201606399VA publication Critical patent/SG11201606399VA/en

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US10121679B1 (en) 2017-09-29 2018-11-06 Intel Corporation Package substrate first-level-interconnect architecture
KR102121808B1 (en) * 2018-03-15 2020-06-11 한국광기술원 Apparatus and Method for Laser Transferring
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CN106104799B (en) 2020-03-06
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