JP4952527B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP4952527B2
JP4952527B2 JP2007296254A JP2007296254A JP4952527B2 JP 4952527 B2 JP4952527 B2 JP 4952527B2 JP 2007296254 A JP2007296254 A JP 2007296254A JP 2007296254 A JP2007296254 A JP 2007296254A JP 4952527 B2 JP4952527 B2 JP 4952527B2
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electrode layer
semiconductor device
electrode
recess
semiconductor element
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JP2009123918A (en
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一寿 山崎
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H01L2224/1111—Shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, and the semiconductor device that offers high bonding reliability and that has projecting electrodes (bump electrodes) on a semiconductor element. <P>SOLUTION: A support substrate having a plurality of first recessions and second recessions formed in the first recessions is provided (step S1), after which first electrode layers are disposed in the second recessions (step S2). The semiconductor element having a plurality of second electrode layers is then brought closer to the support substrate (step S3). Subsequently, while the second electrode layers are received in the first recessions of the support substrate under a heat treatment, part of the first electrode layers is inserted in the second electrode layers (step S4). Finally, the first and second electrode layers are cooled to separate the support substrate from the first and second electrode layers (step S5). <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は半導体装置の製造方法及び半導体装置に関し、特に突起電極を備えた半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a protruding electrode and the semiconductor device.

回路基板に実装する半導体素子には、予め、半導体素子に突起電極（バンプ電極）を配設する場合がある。当該突起電極の形成方法として、スタッドバンプ形成方法または転写バンプ形成方法等がある。   In some cases, a protruding electrode (bump electrode) is provided in advance on a semiconductor element mounted on a circuit board. As a method for forming the protruding electrode, there are a stud bump forming method and a transfer bump forming method.

スタッドバンプ形成方法は、ピン形状の突起電極を半導体素子の主面に形成された電極上に形成するものである。近年では、当該突起電極の高さを揃えるために、半導体素子に配置した突起電極を、研磨冶具により研磨する方法が開示されている（例えば、特許文献１参照）。   In the stud bump forming method, a pin-shaped protruding electrode is formed on an electrode formed on the main surface of a semiconductor element. In recent years, a method has been disclosed in which a protruding electrode disposed on a semiconductor element is polished by a polishing jig in order to make the height of the protruding electrode uniform (see, for example, Patent Document 1).

一方、転写バンプ形成方法は、例えば、絶縁基板の表面にバンプ電極の平面視形状と略等しい形状の下地導体を形成し、下地導体の表面を除く基板表面に、ポリイミド樹脂等の耐熱性の保護層を形成する。そして、下地導体の表面に鍍金電極を形成し、当該鍍金電極の表面に、茸形の突起電極を形成するというものである（例えば、特許文献２参照）。
特開平５−２５１４５３号公報 特開平５−１６６８１４号公報 On the other hand, the transfer bump forming method, for example, forms a base conductor having a shape substantially equal to the shape of the bump electrode in plan view on the surface of the insulating substrate, and heat-resistant protection such as polyimide resin on the substrate surface excluding the surface of the base conductor. Form a layer. Then, a plating electrode is formed on the surface of the base conductor, and a plating-shaped protruding electrode is formed on the surface of the plating electrode (see, for example, Patent Document 2).
JP-A-5-251453 JP-A-5-166814

しかし、上述したスタッドバンプ形成方法は、研磨手段を用いるために、半導体素子に配設する突起電極の高さを充分に制御することができない。
また、上述した転写バンプ形成方法では、バンプ転写時に溶融状態が異なり、バンプ電極の高さ、形状等が不均一になることがある。 However, since the stud bump forming method described above uses the polishing means, the height of the protruding electrode provided on the semiconductor element cannot be controlled sufficiently.
Further, in the above-described transfer bump forming method, the melted state is different at the time of bump transfer, and the height, shape, etc. of the bump electrode may become uneven.

このように高さや形状の異なる突起電極が半導体素子に形成すると、実装時において夫々の突起電極と被接合部との接合面積が異なり、半導体装置としての接合信頼性が低下してしまう。   When the protruding electrodes having different heights and shapes are formed on the semiconductor element in this way, the bonding areas of the protruding electrodes and the bonded portions are different at the time of mounting, and the bonding reliability as a semiconductor device is lowered.

特に、最近の半導体素子は、高集積化により益々、突起電極の狭ピッチ化が進行する傾向にある。従って、確実に高さ、形状の揃った突起電極を半導体素子に配設することが望ましい。   In particular, recent semiconductor devices tend to have a narrower pitch of protruding electrodes due to higher integration. Therefore, it is desirable to arrange the protruding electrodes having the same height and shape on the semiconductor element.

また、上述した研磨に委ねると、研磨により発生する発塵を除去する作業が必要になり、作業効率を向上させることができない。また、研磨による半導体素子へのダメージも無視できない。   In addition, if it is left to the above-described polishing, it is necessary to remove dust generated by the polishing, and the working efficiency cannot be improved. Further, damage to the semiconductor element due to polishing cannot be ignored.

本発明はこのような点に鑑みてなされたものであり、信頼性の高い半導体装置を製造する方法及び半導体装置を提供することを目的とする。   The present invention has been made in view of these points, and an object thereof is to provide a method for manufacturing a highly reliable semiconductor device and a semiconductor device.

本発明の一観点によれば、第１の凹部と前記第１の凹部内に形成された第２の凹部とを有する支持基板を準備する工程と、前記第２の凹部に、第１の電極層を配置する工程と、半導体素子に配設した第２の電極層を前記第１の凹部に受容し、前記第１の電極層の一部を前記第２の電極層内に貫入する工程と、を有する半導体装置の製造方法が提供される。 According to one aspect of the present invention, a step of preparing a supporting substrate for chromatic and a second recess formed in the first recess and the first recess, the second recess, the first A step of disposing an electrode layer; and a step of receiving a second electrode layer disposed in a semiconductor element in the first recess and penetrating a part of the first electrode layer into the second electrode layer. When, a method of manufacturing a semiconductor device which have a are provided.

更に、本発明の一観点によれば、前記第１の電極層の一部を前記第２の電極層内に貫入する工程後に、前記支持基板を前記第１の電極層及び前記第２の電極層から分離する工程と、前記支持基板が分離された前記第１の電極層を、前記半導体素子を実装する部材に配設された被接合部に接合する工程と、前記第１の電極層が接合された前記被接合部に前記第２の電極層を接合する工程とを有する半導体装置の製造方法が提供される。Furthermore, according to one aspect of the present invention, after the step of penetrating a part of the first electrode layer into the second electrode layer, the support substrate is attached to the first electrode layer and the second electrode. A step of separating from the layer, a step of bonding the first electrode layer from which the support substrate has been separated to a bonded portion provided on a member for mounting the semiconductor element, and the first electrode layer And a step of bonding the second electrode layer to the bonded portion to be bonded.

また、本発明の一観点によれば、半導体素子と、前記半導体素子に配設された突起電極とを含み、前記突起電極は、円錐状の第１の電極層と、前記第１の電極層の周部を被覆する第２の電極層と、を備え、円錐状の前記第１の電極層が、先細の先端部を前記半導体素子側に向けて配設され、前記先端部と反対側の端部が前記第２の電極層から突出する半導体装置が提供される。
 According to another aspect of the present invention, the semiconductor device includes a semiconductor element and a protruding electrode disposed on the semiconductor element, and the protruding electrode includes a conical first electrode layer and the first electrode layer. A conical first electrode layer is disposed with a tapered tip portion facing the semiconductor element side, and is opposite to the tip portion. A semiconductor device having an end protruding from the second electrode layer is provided .

上記手段によれば、信頼性の高い半導体装置を製造する方法及び半導体装置を実現させることができる。   According to the above means, a method and a semiconductor device for manufacturing a highly reliable semiconductor device can be realized.

以下、本実施の形態に係る半導体装置の製造方法及び半導体装置を、図面を参照しながら詳細に説明する。
図１は半導体装置の製造方法の概要を説明するフロー図である。このフロー図には、半導体装置の製造方法に係る工程の概要が示されている。 Hereinafter, a semiconductor device manufacturing method and a semiconductor device according to the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a flowchart for explaining an outline of a method for manufacturing a semiconductor device. This flowchart shows an overview of the steps related to a method for manufacturing a semiconductor device.

先ず、本実施の形態の半導体装置の製造方法では、複数の第１の凹部と当該第１の凹部内に形成された第２の凹部とを有した支持基板を準備する（ステップＳ１）。
次に、第２の凹部に、第１の電極層を配置する（ステップＳ２）。例えば、第２の凹部にスタッドバンプ法で円錐状の電極層を立設する。 First, in the method for manufacturing a semiconductor device according to the present embodiment, a support substrate having a plurality of first recesses and a second recess formed in the first recess is prepared (step S1).
Next, the first electrode layer is disposed in the second recess (step S2). For example, a conical electrode layer is erected in the second recess by a stud bump method.

次に、複数の第２の電極層を配設した半導体素子を準備する。そして、当該第２の電極層に加熱処理を施すことにより、第２の電極層を溶融状態にする。更に、支持基板と複数の第２の電極層を配設した半導体素子との主面間を接近させる（ステップＳ３）。この際、支持基板の主面と半導体素子の主面との平行状態を維持しながら、夫々の主面を接近させる。   Next, a semiconductor element provided with a plurality of second electrode layers is prepared. Then, the second electrode layer is brought into a molten state by performing heat treatment on the second electrode layer. Further, the main surfaces of the support substrate and the semiconductor element provided with the plurality of second electrode layers are brought close to each other (step S3). At this time, the main surfaces of the support substrate and the main surface of the semiconductor element are kept close to each other while maintaining the parallel state.

次に、加熱処理を継続し、第２の電極層を支持基板の第１の凹部に受容しながら、第２の電極層内に第１の電極層の一部を貫入する（ステップＳ４）。
続いて、加熱処理により第１の電極層と第２の電極層との固溶拡散接合を促進させた後、第１の電極層及び第２の電極層を冷却し、支持基板を第１の電極層及び第２の電極層から離反する（ステップＳ５）。 Next, the heat treatment is continued, and a part of the first electrode layer is penetrated into the second electrode layer while receiving the second electrode layer in the first recess of the support substrate (step S4).
Subsequently, after the solid solution diffusion bonding between the first electrode layer and the second electrode layer is promoted by heat treatment, the first electrode layer and the second electrode layer are cooled, and the support substrate is moved to the first electrode layer. Separate from the electrode layer and the second electrode layer (step S5).

このような方法により、高さまたは形状の揃った突起電極を配設した半導体装置が完成する。
次に、上述した半導体装置の製造方法の概要に基づき、より具体的な半導体装置の製造方法を説明する。以下に示す、図２乃至図６には、半導体装置の製造方法を説明するための要部断面模式図が例示されている。 By such a method, a semiconductor device in which protruding electrodes having a uniform height or shape are arranged is completed.
Next, a more specific method for manufacturing a semiconductor device will be described based on the outline of the method for manufacturing a semiconductor device described above. FIGS. 2 to 6 shown below exemplify cross-sectional schematic diagrams of relevant parts for explaining a method for manufacturing a semiconductor device.

先ず、図２（ａ）に示すように、段差の異なる複数の凹部１０ａ，１０ｂを備えた支持基板１０を準備する。ここで、支持基板１０の材質は、例えば、テフロン（登録商標）等のフッ素樹脂またはポリイミド樹脂を主たる成分とする樹脂が適用される。   First, as shown in FIG. 2A, a support substrate 10 having a plurality of recesses 10a and 10b having different steps is prepared. Here, the material of the support substrate 10 is, for example, a resin mainly composed of a fluororesin such as Teflon (registered trademark) or a polyimide resin.

具体的には、支持基板１０上に、後述する半導体素子に配設されている電極パッド（電極端子）と同ピッチの凹部１０ａ（第１の凹部）を形成する。この凹部１０ａの底面は、当該電極パッドと同寸法である。また、夫々の凹部１０ａの深さは同一とする。そして、この凹部１０ａの側壁（周縁部）には、テーパ部１０ａｔを設ける。   Specifically, on the support substrate 10, recesses 10a (first recesses) having the same pitch as electrode pads (electrode terminals) arranged in a semiconductor element described later are formed. The bottom surface of the recess 10a has the same dimensions as the electrode pad. Moreover, the depth of each recessed part 10a shall be the same. And the taper part 10at is provided in the side wall (periphery part) of this recessed part 10a.

更に、凹部１０ａの底面の中心部に、別の凹部１０ｂ（第２の凹部）を形成する。ここで、夫々の凹部１０ｂの深さ及び幅は同一とする。そして、当該凹部１０ｂの中心は、凹部１０ａの中心と一致させる。これにより、半導体素子に配設されている電極パッドと凹部１０ｂのピッチとが一致する。   Further, another recess 10b (second recess) is formed at the center of the bottom surface of the recess 10a. Here, the depth and width of each recess 10b are the same. And the center of the said recessed part 10b is made to correspond with the center of the recessed part 10a. Thereby, the pitch of the electrode pad arrange | positioned at a semiconductor element and the recessed part 10b corresponds.

このような凹部１０ａ，１０ｂの形成は、例えば、型による転写法、成形法、レーザ加工法、フォトリソグラフィ等の何れかの方法により行う。
また、凹部１０ｂの底面１０ｂｂは、平坦性が良好であり、支持基板１０の主面と平行となるように形成されている。 Such recesses 10a and 10b are formed by any method such as a transfer method using a mold, a molding method, a laser processing method, or photolithography.
The bottom surface 10bb of the recess 10b has good flatness and is formed to be parallel to the main surface of the support substrate 10.

また、この図では、凹部１０ｂの側壁が略垂直となるように表示されているが、必要に応じて、その側壁にテーパを設けてもよい。
続いて、図２（ｂ）に示すように、凹部１０ｂの底面１０ｂｂに金属膜１１ａを選択的に形成する。ここで、金属膜１１ａの材質は、例えば、金（Ａｕ）を主たる成分とする金属が適用される。このような金属膜１１ａは、例えば、スパッタ法、ＣＶＤ（Chemical Vapor Deposition）法、鍍金法等の何れかの手段により形成する。 Further, in this figure, the side wall of the recess 10b is displayed so as to be substantially vertical. However, if necessary, the side wall may be tapered.
Subsequently, as shown in FIG. 2B, a metal film 11a is selectively formed on the bottom surface 10bb of the recess 10b. Here, as a material of the metal film 11a, for example, a metal whose main component is gold (Au) is applied. Such a metal film 11a is formed by any means such as sputtering, CVD (Chemical Vapor Deposition), and plating.

そして、図２（ｃ）に示すように、金属膜１１ａ上に、スタッドバンプ法によって円錐状のバンプ１１ｂを接合する。このバンプ１１ｂの材質は、例えば、金（Ａｕ）を主たる成分とする金属が適用される。   Then, as shown in FIG. 2C, a conical bump 11b is joined on the metal film 11a by a stud bump method. As the material of the bump 11b, for example, a metal whose main component is gold (Au) is applied.

尚、金属膜１１ａとバンプ１１ｂの主たる成分は同一であり、金属膜１１ａとバンプ１１ｂはスタッドバンプ法によって互いに接合することから、以下、一体となった金属膜１１ａとバンプ１１ｂをバンプ電極層（第１の電極層）１１と称する。   The main components of the metal film 11a and the bump 11b are the same, and the metal film 11a and the bump 11b are joined to each other by the stud bump method. First electrode layer) 11 is called.

次に、図３に示すように、半導体素子２０を準備し、支持冶具３０によって半導体素子２０の主面を吸着・保持する。そして、支持冶具３０によって吸着・保持されていない半導体素子２０の主面をバンプ電極層１１を配置した支持基板１０の主面に対向させ、半導体素子２０と支持基板１０との主面同士を平行にする。   Next, as shown in FIG. 3, the semiconductor element 20 is prepared, and the main surface of the semiconductor element 20 is sucked and held by the support jig 30. Then, the main surface of the semiconductor element 20 that is not attracted / held by the support jig 30 is opposed to the main surface of the support substrate 10 on which the bump electrode layer 11 is disposed, and the main surfaces of the semiconductor element 20 and the support substrate 10 are parallel to each other. To.

ここで、支持冶具３０は、半導体素子２０を吸着・保持する機構の他、半導体素子２０を加熱・冷却する機構を備えている。また、支持冶具３０は、支持基板１０の主面と半導体素子２０の主面との平行状態を維持しながら、その主面間を接近させたり、離反させたりする移動機構を備えている。   Here, the support jig 30 includes a mechanism for heating and cooling the semiconductor element 20 in addition to a mechanism for attracting and holding the semiconductor element 20. Further, the support jig 30 includes a moving mechanism that moves the main surfaces closer to or away from each other while maintaining the parallel state between the main surface of the support substrate 10 and the main surface of the semiconductor element 20.

また、半導体素子２０においては、シリコン（Ｓｉ）またはガリウムヒ素（ＧａＡｓ）等の半導体基材の一方の主面に、所謂ウエハプロセスを適用し、トランジスタ等の能動素子、容量素子等の受動素子を形成させた半導体チップが適用される。更に、半導体チップには、これらの素子に接続された多層構造の配線層が形成されている。そして、半導体素子２０の主面には、上記配線層に電気的に接続された電極パッド２０ａが配設されている。更に、電極パッド２０ａ上には、予め、半田層（第２の電極層）２１ａが形成されている。このような半田層２１ａは、鍍金法、スクリーン印刷法、蒸着法、スパッタ法等のいずれかの手段により形成する。   In the semiconductor element 20, a so-called wafer process is applied to one main surface of a semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs), so that active elements such as transistors and passive elements such as capacitive elements are provided. The formed semiconductor chip is applied. Furthermore, a multilayered wiring layer connected to these elements is formed on the semiconductor chip. An electrode pad 20 a electrically connected to the wiring layer is disposed on the main surface of the semiconductor element 20. Further, a solder layer (second electrode layer) 21a is formed in advance on the electrode pad 20a. Such a solder layer 21a is formed by any means such as a plating method, a screen printing method, a vapor deposition method, and a sputtering method.

尚、電極パッド２０ａの材質は、アルミニウム（Ａｌ）または銅（Ｃｕ）を主たる成分とする金属が適用される。
また、半田層２１ａの材質は、例えば、錫（Ｓｎ）−鉛（Ｐｂ）共晶系半田、または鉛（Ｐｂ）フリーである２元系の錫（Ｓｎ）−銀（Ａｇ）半田、或いは３元系の錫（Ｓｎ）−銀（Ａｇ）−銅（Ｃｕ）半田が適用される。 The material of the electrode pad 20a is a metal whose main component is aluminum (Al) or copper (Cu).
The material of the solder layer 21a is, for example, tin (Sn) -lead (Pb) eutectic solder, binary (Pb) -free binary tin (Sn) -silver (Ag) solder, or 3 An original tin (Sn) -silver (Ag) -copper (Cu) solder is applied.

このような半導体素子２０と、支持基板１０の主面同士を平行に対向させた後、半田層２１ａとバンプ電極層１１との位置あわせを行う。
上述したように、電極パッド２０ａと凹部１０ｂとのピッチは一致している。従って、上記の位置あわせにより、電極パッド２０ａ上に形成させた半田層２１ａと、凹部１０ｂに設けたバンプ電極層１１とのピッチも一致する。また、半田層２１ａとバンプ電極層１１との中心位置も一致する。 After the semiconductor element 20 and the main surfaces of the support substrate 10 are opposed to each other in parallel, the solder layer 21a and the bump electrode layer 11 are aligned.
As described above, the pitch between the electrode pad 20a and the recess 10b is the same. Therefore, the pitch between the solder layer 21a formed on the electrode pad 20a and the bump electrode layer 11 provided in the recess 10b is also matched by the above alignment. Further, the center positions of the solder layer 21a and the bump electrode layer 11 also coincide.

そして、支持冶具３０の加熱機構により、電極パッド２０ａ上に形成した半田層２１ａが溶融状態になるまで加熱する。処理温度は、１５０℃〜３００℃である。例えば、上記に例示した半田材の融点以上の温度にまで、半田層２１ａを加熱する。   And it heats with the heating mechanism of the support jig 30 until the solder layer 21a formed on the electrode pad 20a will be in a molten state. Processing temperature is 150 to 300 degreeC. For example, the solder layer 21a is heated to a temperature equal to or higher than the melting point of the solder material exemplified above.

次に、図４（ａ）に示すように、支持冶具３０を支持基板１０に対し降下させ、溶融状態にある半田層２１ｂ内に、バンプ電極層１１の一部を貫入する。上述したように、半田層２１ａとバンプ電極層１１との中心位置が一致していることから、夫々のバンプ電極層１１は、夫々の半田層２１ｂの中心に貫入する。   Next, as shown in FIG. 4A, the support jig 30 is lowered with respect to the support substrate 10, and a part of the bump electrode layer 11 penetrates into the solder layer 21b in a molten state. As described above, since the center positions of the solder layer 21a and the bump electrode layer 11 coincide with each other, each bump electrode layer 11 penetrates into the center of each solder layer 21b.

続いて、半導体素子２０の主面と支持基板１０の主面との距離を所定の距離だけ隔てた状態を維持しながら、加熱処理を所定の時間継続する。処理温度は、１５０℃〜３００℃である。このような加熱処理により、半田層２１ｂとバンプ電極層１１との界面における固相拡散が促進する。   Subsequently, the heat treatment is continued for a predetermined time while maintaining a state in which the main surface of the semiconductor element 20 and the main surface of the support substrate 10 are separated by a predetermined distance. Processing temperature is 150 to 300 degreeC. By such heat treatment, solid phase diffusion at the interface between the solder layer 21b and the bump electrode layer 11 is promoted.

例えば、半田層２１ｂに貫入したバンプ電極層１１は、固相状態にあるが、このような加熱処理により、バンプ電極層１１の表面から所定の深さに、半田層２１ｂを構成する元素が拡散する。   For example, the bump electrode layer 11 penetrating the solder layer 21b is in a solid state, but the elements constituting the solder layer 21b are diffused from the surface of the bump electrode layer 11 to a predetermined depth by such heat treatment. To do.

なお、当該加熱処理中には、溶融状態にある半田層２１ｂが支持基板１０の凹部１０ａに受容された状態が維持される。
この溶融状態にある半田層２１ｂは、半田材の金（Ａｕ）材に対する濡れ性の良さ、更には、凹部１０ａに設けたテーパ部１０ａｔのダム効果または半田材の樹脂材に対する濡れ性の悪さから、バンプ電極層１１の周囲に回り込むだけにとどまる。従って、夫々の半田層２１ｂが凹部１０ａ外に流出することはない。 During the heat treatment, a state where the molten solder layer 21b is received in the recess 10a of the support substrate 10 is maintained.
The solder layer 21b in the molten state has good wettability with respect to the gold (Au) material of the solder material, and further, due to the dam effect of the taper portion 10at provided in the recess 10a or poor wettability with respect to the resin material of the solder material. It only stays around the periphery of the bump electrode layer 11. Therefore, each solder layer 21b does not flow out of the recess 10a.

また、半田材自体の表面張力により、半田層２１ｂの外形は球状になる。
また、凹部１０ｂにおいては、バンプ電極層１１を構成する金属材が埋設していることから、当該凹部１０ｂ内に、半田層２１ｂが回り込むことはない。 Further, the outer shape of the solder layer 21b becomes spherical due to the surface tension of the solder material itself.
Further, since the metal material constituting the bump electrode layer 11 is embedded in the recess 10b, the solder layer 21b does not go into the recess 10b.

そして、図４（ｂ）に示すように、支持冶具３０の冷却機構によって、半田層２１ｂを冷却し、固相状態の半田層２１をバンプ電極層１１の周囲に形成する。
これにより、半田層２１とバンプ電極層１１とが一体となり、電極パッド２０ａと導通する突起電極２２が半導体素子２０に配置される。 4B, the solder layer 21b is cooled by the cooling mechanism of the support jig 30, and the solid-state solder layer 21 is formed around the bump electrode layer 11. As shown in FIG.
As a result, the solder layer 21 and the bump electrode layer 11 are integrated, and the protruding electrode 22 that is electrically connected to the electrode pad 20 a is disposed on the semiconductor element 20.

尚、半田層２１は、固相状態となったことから、半田層２１ｂより若干、外形が収縮する。
また、半導体素子２０の主面と支持基板１０の主面間の平行状態を維持しながら、半田層２１内に、バンプ電極層１１を貫設したので、半導体素子２０の主面からバンプ電極層１１の高さは均一に構成されている。 Since the solder layer 21 is in a solid phase, the outer shape is slightly contracted from the solder layer 21b.
In addition, since the bump electrode layer 11 is provided in the solder layer 21 while maintaining a parallel state between the main surface of the semiconductor element 20 and the main surface of the support substrate 10, the bump electrode layer extends from the main surface of the semiconductor element 20. The height of 11 is constituted uniformly.

また、図４（ａ）に示す半田層２１ｂ内に、バンプ電極層１１を貫入する場合には、半田層２１ｂを完全な溶融状態とせず、半溶融状態としてもよい。上述したように、バンプ電極層１１は円錐状であるために、半田層２１ｂが溶融状態または半溶融状態のいずれの場合でも、バンプ電極層１１が容易に半田層２１ｂに貫入する。   When the bump electrode layer 11 is penetrated into the solder layer 21b shown in FIG. 4A, the solder layer 21b may not be completely melted but may be semi-molten. As described above, since the bump electrode layer 11 has a conical shape, the bump electrode layer 11 easily penetrates into the solder layer 21b regardless of whether the solder layer 21b is in a molten state or a semi-molten state.

次に、図５（ａ）に示すように、支持冶具３０に吸着・保持された半導体素子２０を上方に移動させ、支持基板１０をバンプ電極層１１及び半田層２１から離反する。
ここで、金属材と有機樹脂を主成分とする支持基板１０との密着性は弱いので、上記の移動により、バンプ電極層１１及び半田層２１と支持基板１０とは容易に剥離する。 Next, as shown in FIG. 5A, the semiconductor element 20 attracted and held by the support jig 30 is moved upward, and the support substrate 10 is separated from the bump electrode layer 11 and the solder layer 21.
Here, since the adhesion between the metal material and the support substrate 10 containing organic resin as a main component is weak, the bump electrode layer 11 and the solder layer 21 and the support substrate 10 are easily separated by the above movement.

そして、図５（ｂ）に示すように、半導体素子２０を支持冶具３０から開放し、形状または高さの揃った突起電極２２を配設した半導体装置１を得る。
尚、突起電極２２に含まれる半田層２１とバンプ電極層１１との界面は、固相拡散接合をさせたことから、それらは強固に密着している。 Then, as shown in FIG. 5B, the semiconductor element 20 is released from the support jig 30 to obtain the semiconductor device 1 provided with the protruding electrodes 22 having the same shape or height.
In addition, since the interface between the solder layer 21 and the bump electrode layer 11 included in the protruding electrode 22 is solid-phase diffusion bonded, they are firmly adhered.

また、上述したように、バンプ電極層１１は、凹部１０ｂを下地として形成させたことから、当該凹部１０ｂに半田層２１が回り込むことがない。従って、突起電極２２の下部においては、凹部１０ｂの内形状に対応するように、バンプ電極層１１の下面が半田層２１の先端から表出する構造を有している。   Further, as described above, since the bump electrode layer 11 is formed using the recess 10b as a base, the solder layer 21 does not go around the recess 10b. Therefore, the lower surface of the bump electrode 22 has a structure in which the lower surface of the bump electrode layer 11 is exposed from the tip of the solder layer 21 so as to correspond to the inner shape of the recess 10 b.

このように、これまでの方法で作製した半導体装置１は、複数の層からなる突起電極２２を複数個、配設した構造を有している。更に、この突起電極２２は、バンプ電極層１１と、バンプ電極層１１の周部を被覆する半田層２１と、を備え、バンプ電極層１１の下面が半田層２１の先端から突出した構造を有している。   As described above, the semiconductor device 1 manufactured by the conventional method has a structure in which a plurality of protruding electrodes 22 including a plurality of layers are arranged. Further, the bump electrode 22 includes a bump electrode layer 11 and a solder layer 21 covering the periphery of the bump electrode layer 11, and has a structure in which the lower surface of the bump electrode layer 11 protrudes from the tip of the solder layer 21. is doing.

次に、この半導体装置１を、更に別の部材に実装する半導体装置の製造方法について説明する。ここでは、その部材として配線基板を用いた場合の半導体装置の製造方法について説明する。   Next, a method for manufacturing a semiconductor device in which the semiconductor device 1 is mounted on another member will be described. Here, a manufacturing method of a semiconductor device when a wiring board is used as the member will be described.

先ず、図６（ａ）に示すように、半導体装置１に配設した突起電極２２と配線基板４０に配設した電極パッド４０ａとが接触するように、半導体装置１を配線基板４０上に載置する。   First, as shown in FIG. 6A, the semiconductor device 1 is mounted on the wiring board 40 so that the protruding electrodes 22 arranged on the semiconductor device 1 and the electrode pads 40a arranged on the wiring board 40 are in contact with each other. Put.

ここで、半導体素子２０の主面からのバンプ電極層１１の高さは均一であり、突起電極２２の下面は平坦であることから、夫々のバンプ電極層１１と夫々の電極パッド４０ａの全ての接触面が隙間なく接触する。   Here, since the height of the bump electrode layer 11 from the main surface of the semiconductor element 20 is uniform and the lower surface of the bump electrode 22 is flat, all the bump electrode layers 11 and all of the electrode pads 40a are all. Contact surface contacts without gaps.

尚、配線基板４０の材質は、ガラス−エポキシ樹脂、ガラス−ビスマレイミドトリアジン（ＢＴ）、またはポリイミド等の有機材絶縁性樹脂を主たる成分としている。また、セラミックあるいはガラス等の無機絶縁材料を主たる成分とする場合もある。また、配線基板４０は、回路基板、インターポーザ、或いはパッケージ基板とも称される。   The material of the wiring board 40 is mainly composed of glass-epoxy resin, glass-bismaleimide triazine (BT), or organic insulating resin such as polyimide. In some cases, the main component is an inorganic insulating material such as ceramic or glass. The wiring board 40 is also referred to as a circuit board, an interposer, or a package board.

また、配線基板４０の主面に配設した、夫々の電極パッド４０ａは、配線基板４０内に積層された回路（図示しない）と導通している。また、電極パッド４０ａは、半導体装置１の突起電極２２と接続する接続用端子になる。   Each electrode pad 40 a disposed on the main surface of the wiring board 40 is electrically connected to a circuit (not shown) stacked in the wiring board 40. The electrode pad 40 a serves as a connection terminal that is connected to the protruding electrode 22 of the semiconductor device 1.

また、電極パッド４０ａの材質は、例えば、アルミニウム（Ａｌ）、銅（Ｃｕ）の少なくとも一つを含む金属を主たる成分としている。また、電極パッド４０ａの表面には、例えば、下層からニッケル（Ｎｉ）、金（Ａｕ）の２層メッキが施されている。   The material of the electrode pad 40a is mainly composed of a metal including at least one of aluminum (Al) and copper (Cu), for example. The surface of the electrode pad 40a is subjected to, for example, two-layer plating of nickel (Ni) and gold (Au) from the lower layer.

続いて、突起電極２２が配設されている半導体素子２０の主面とは反対側の主面に、超音波振動子３１を設置し、当該超音波振動子３１を作動することによって、バンプ電極層１１の先端に超音波を印加する。   Subsequently, an ultrasonic transducer 31 is installed on the main surface opposite to the main surface of the semiconductor element 20 on which the protruding electrodes 22 are disposed, and the ultrasonic transducer 31 is operated to thereby form a bump electrode. An ultrasonic wave is applied to the tip of the layer 11.

これにより、バンプ電極層１１と電極パッド４０ａの界面での超音波接合が遂行され、バンプ電極層１１の下面と電極パッド４０ａの上面とが接合する。この接続を仮接続と称する。この仮接続により、電極パッド２０ａ，４０ａの中心位置同士が一致する。そして、当該仮接続を完了させた後、超音波振動子３１を半導体素子２０の主面から離反する（図示しない）。   Thus, ultrasonic bonding is performed at the interface between the bump electrode layer 11 and the electrode pad 40a, and the lower surface of the bump electrode layer 11 and the upper surface of the electrode pad 40a are bonded. This connection is referred to as temporary connection. By this temporary connection, the center positions of the electrode pads 20a and 40a coincide. Then, after completing the temporary connection, the ultrasonic transducer 31 is separated from the main surface of the semiconductor element 20 (not shown).

次に、図６（ｂ）に示すように、仮接続により一体となった半導体装置１及び配線基板４０を加熱容器（図示しない）に設置し、加熱処理（リフロー処理）を半導体装置１及び配線基板４０に施す。処理温度は、１５０℃〜３００℃である。なお、当該加熱処理においては、必要に応じて、予め、仮接続がなされていない電極パッド４０ａ上面に、フラックス材を塗布してもよい。   Next, as shown in FIG. 6B, the semiconductor device 1 and the wiring substrate 40 integrated by temporary connection are installed in a heating container (not shown), and the heat treatment (reflow treatment) is performed on the semiconductor device 1 and the wiring. It is applied to the substrate 40. Processing temperature is 150 to 300 degreeC. In the heat treatment, a flux material may be applied in advance to the upper surface of the electrode pad 40a that is not temporarily connected as necessary.

このリフロー処理によって、再び、半田層２１は溶融状態となり、半田層２１が仮接続した部分以外の電極パッド４０ａに濡れ広がる。但し、半田材の金（Ａｕ）材に対する濡れ性の良さ、または半田材自体の表面張力から、夫々の半田層２１が電極パッド４０ａ外に漏出することはない。   By this reflow process, the solder layer 21 is again melted and spreads wet on the electrode pads 40a other than the part where the solder layer 21 is temporarily connected. However, each solder layer 21 does not leak out of the electrode pad 40a due to the good wettability of the solder material to the gold (Au) material or the surface tension of the solder material itself.

そして、この後においては、半導体装置１及び配線基板４０を加熱容器から取り出し、半導体装置１及び配線基板４０を室温まで冷却する。
これにより、半導体装置１の電極パッド２０ａと配線基板４０の電極パッド４０ａとが仮接続の他、半田層２１を通じて、電気的に接続される。この接続を本接続と称する。 Thereafter, the semiconductor device 1 and the wiring substrate 40 are taken out of the heating container, and the semiconductor device 1 and the wiring substrate 40 are cooled to room temperature.
Thereby, the electrode pad 20a of the semiconductor device 1 and the electrode pad 40a of the wiring board 40 are electrically connected through the solder layer 21 in addition to the temporary connection. This connection is called a main connection.

尚、仮接続後において、電極パッド２０ａ，４０ａの中心位置同士が一致していることから、当該本接続においても、電極パッド２０ａ，４０ａの中心位置同士は一致する。
また、加熱処理により、半田層２１と電極パッド４０ａとの界面における固相拡散が促進するので、半田層２１と電極パッド４０ａとは、強固に密着する。 Since the center positions of the electrode pads 20a and 40a match after temporary connection, the center positions of the electrode pads 20a and 40a also match in the main connection.
Further, since the solid phase diffusion at the interface between the solder layer 21 and the electrode pad 40a is promoted by the heat treatment, the solder layer 21 and the electrode pad 40a are firmly adhered.

このように、本実施の形態では、仮接続により、半導体装置１に設けられたバンプ電極層１１と、配線基板４０に設けられた電極パッド４０ａの中心部とを接合する。これにより、半導体装置１と配線基板４０との相対位置が完全に固定する。続いて、本接続により、当該中心部分以外の電極パッド４０ａに、突起電極２２の半田層２１を接合する。   As described above, in the present embodiment, the bump electrode layer 11 provided in the semiconductor device 1 and the central portion of the electrode pad 40 a provided in the wiring substrate 40 are joined by temporary connection. Thereby, the relative position of the semiconductor device 1 and the wiring board 40 is completely fixed. Subsequently, the solder layer 21 of the protruding electrode 22 is joined to the electrode pad 40a other than the central portion by this connection.

尚、半導体装置１の被実装基板としては、配線基板４０に限ることはない。配線基板４０の代わりに、別の半導体素子を用いてもよい。即ち、当該別の半導体素子に設けられた電極パッドに、突起電極２２を上記と同様の方法で接合して、複数の半導体素子を積層させた半導体装置を作製してもよい。   The mounting substrate of the semiconductor device 1 is not limited to the wiring substrate 40. Instead of the wiring substrate 40, another semiconductor element may be used. That is, a semiconductor device in which a plurality of semiconductor elements are stacked may be manufactured by bonding the protruding electrode 22 to the electrode pad provided in the other semiconductor element by the same method as described above.

以上説明したように、本実施の形態は、以下に示す有利な効果を有する。
半導体装置１では、半導体素子２０の主面から高さの揃った突起電極２２を複数個、配設している。また、当該突起電極２２においては、半田層２１の先端からバンプ電極層１１の底面を表出させた構造としている。また、夫々のバンプ電極層１１の底面の平坦性は良好で、その面積は均一である。 As described above, the present embodiment has the following advantageous effects.
In the semiconductor device 1, a plurality of protruding electrodes 22 having a uniform height from the main surface of the semiconductor element 20 are disposed. Further, the protruding electrode 22 has a structure in which the bottom surface of the bump electrode layer 11 is exposed from the tip of the solder layer 21. Further, the flatness of the bottom surface of each bump electrode layer 11 is good and the area thereof is uniform.

このような半導体装置１を用いることにより、半導体装置１に配設された全ての突起電極２２と被接合部とが隙間なく接合する。
また、半田層２１の先端からバンプ電極層１１の底面を表出させた構造とすることにより、接続工程を仮接続と本接続に分けることが可能になり、接合信頼性がより向上する。 By using such a semiconductor device 1, all the protruding electrodes 22 disposed in the semiconductor device 1 and the bonded portions are bonded without a gap.
Further, by adopting a structure in which the bottom surface of the bump electrode layer 11 is exposed from the tip of the solder layer 21, the connection process can be divided into temporary connection and main connection, and the bonding reliability is further improved.

特に、最近の半導体素子は、高集積化により益々、突起電極の狭ピッチ化が進行する傾向にあるが、上述した半導体装置の製造方法によれば、高さ、形状の揃った突起電極を配設した半導体装置を確実に実現することができる。   In particular, recent semiconductor elements tend to have narrower pitches of protruding electrodes due to higher integration. However, according to the semiconductor device manufacturing method described above, protruding electrodes having a uniform height and shape are arranged. The provided semiconductor device can be realized with certainty.

また、上記の半導体装置の製造方法では、研磨工程がないため、研磨による発塵が発生しない。また、研磨工程により生じる半導体素子のダメージも発生しない。
このように、本実施の形態によれば、信頼性の高い半導体装置を製造する方法及び半導体装置が実現する。 Further, in the above method for manufacturing a semiconductor device, since there is no polishing step, dust generation due to polishing does not occur. Further, damage to the semiconductor element caused by the polishing process does not occur.
Thus, according to the present embodiment, a method and a semiconductor device for manufacturing a highly reliable semiconductor device are realized.

半導体装置の製造方法の概要を説明するフロー図である。It is a flowchart explaining the outline | summary of the manufacturing method of a semiconductor device. 半導体装置の製造方法を説明するための要部断面模式図である（その１）。FIG. 6 is a schematic cross-sectional view of a relevant part for explaining the method of manufacturing a semiconductor device (No. 1). 半導体装置の製造方法を説明するための要部断面模式図である（その２）。FIG. 6 is a schematic cross-sectional view of the relevant part for explaining the method of manufacturing a semiconductor device (part 2); 半導体装置の製造方法を説明するための要部断面模式図である（その３）。FIG. 6 is a schematic cross-sectional view of the relevant part for explaining the method of manufacturing a semiconductor device (No. 3). 半導体装置の製造方法を説明するための要部断面模式図である（その４）。FIG. 6 is a schematic cross-sectional view of the relevant part for explaining the method of manufacturing a semiconductor device (No. 4). 半導体装置の製造方法を説明するための要部断面模式図である（その５）。FIG. 6 is a schematic cross-sectional view of the relevant part for explaining the method of manufacturing a semiconductor device (No. 5).

符号の説明Explanation of symbols

１ 半導体装置
１０ 支持基板
１０ａ，１０ｂ 凹部
１０ａｔ テーパ部
１０ｂｂ 底面
１１ バンプ電極層
１１ａ 金属膜
１１ｂ バンプ
２０ 半導体素子
２０ａ，４０ａ 電極パッド
２１，２１ａ，２１ｂ 半田層
２２ 突起電極
３０ 支持冶具
３１ 超音波振動子
４０ 配線基板 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Support substrate 10a, 10b Concave part 10at Tapered part 10bb Bottom face 11 Bump electrode layer 11a Metal film 11b Bump 20 Semiconductor element 20a, 40a Electrode pad 21,21a, 21b Solder layer 22 Protruding electrode 30 Support jig 31 Ultrasonic vibrator 40 Wiring board

Claims (7)

第１の凹部と前記第１の凹部内に形成された第２の凹部とを有する支持基板を準備する工程と、
前記第２の凹部に、第１の電極層を配置する工程と、
半導体素子に配設した第２の電極層を前記第１の凹部に受容し、前記第１の電極層の一部を前記第２の電極層内に貫入する工程と、
を有することを特徴とする半導体装置の製造方法。 Preparing a supporting substrate for chromatic and a second recess formed in the first recess and the first recess,
Disposing a first electrode layer in the second recess;
Receiving a second electrode layer disposed on the semiconductor element in the first recess, and penetrating a part of the first electrode layer into the second electrode layer;
A method for manufacturing a semiconductor device, comprising: スタッドバンプ法で円錐状の前記第１の電極層を前記第２の凹部に形成することを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode layer having a conical shape is formed in the second recess by a stud bump method. 前記第１の凹部の周縁部は、テーパ形状をしていることを特徴とする請求項１または２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein a peripheral edge portion of the first recess has a tapered shape. 前記第１の電極層の一部を前記第２の電極層内に貫入する工程後に、
前記支持基板を前記第１の電極層及び前記第２の電極層から分離する工程と、
前記支持基板が分離された前記第１の電極層を、前記半導体素子を実装する部材に配設された被接合部に接合する工程と、
前記第１の電極層が接合された前記被接合部に前記第２の電極層を接合する工程と
を有することを特徴とする請求項１乃至３のいずれかに記載の半導体装置の製造方法。 After the step of penetrating a part of the first electrode layer into the second electrode layer,
Separating the support substrate from the first electrode layer and the second electrode layer;
Bonding the first electrode layer from which the support substrate is separated to a bonded portion disposed on a member for mounting the semiconductor element;
4. The method of manufacturing a semiconductor device according to claim 1 , further comprising a step of bonding the second electrode layer to the bonded portion to which the first electrode layer is bonded . 5. 前記第１の電極層と前記被接合部とを超音波接合により接合することを特徴とする請求項４記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first electrode layer and the bonded portion are bonded by ultrasonic bonding. 前記第２の電極層と前記被接合部とを半田付けにより接合することを特徴とする請求項４または５記載の半導体装置の製造方法。 A method according to claim 4 or 5, wherein the joining and said bonding portion and the second electrode layer by soldering. 半導体素子と、
前記半導体素子に配設された突起電極と
を含み、
前記突起電極は、
円錐状の第１の電極層と、
前記第１の電極層の周部を被覆する第２の電極層と、
を備え、
円錐状の前記第１の電極層が、先細の先端部を前記半導体素子側に向けて配設され、前記先端部と反対側の端部が前記第２の電極層から突出する
ことを特徴とする半導体装置。 A semiconductor element;
A protruding electrode disposed on the semiconductor element;
Including
The protruding electrode is
A conical first electrode layer;
A second electrode layer covering the periphery of the first electrode layer;
With
The first electrode layer having a conical shape is provided with a tapered tip portion facing the semiconductor element side, and an end portion opposite to the tip portion projects from the second electrode layer. Semiconductor device.
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