JP2000174059A - Method of mounting electronic component - Google Patents
Method of mounting electronic componentInfo
- Publication number
- JP2000174059A JP2000174059A JP10350092A JP35009298A JP2000174059A JP 2000174059 A JP2000174059 A JP 2000174059A JP 10350092 A JP10350092 A JP 10350092A JP 35009298 A JP35009298 A JP 35009298A JP 2000174059 A JP2000174059 A JP 2000174059A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- solder
- mounting
- substrate
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
- H01L2224/81906—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
- H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品を基板に
半田接合により実装する電子部品の実装方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an electronic component on a substrate by soldering.
【０００２】[0002]
【従来の技術】電子部品を基板に実装する方法として半
田接合が広く用いられている。この半田接合による実装
の形態として、半田の突出電極である半田バンプを電子
部品もしくは基板の電極に予め形成し、半田バンプを加
熱溶融させて電子部品を基板に半田接合する方法が知ら
れている。従来半田バンプによる半田接合に際しては、
接合部位にフラックスを塗布して仮固定を行うととも
に、フラックスの活性作用により半田表面の酸化膜を除
去して半田接合性を向上させることが一般に行われてい
た。2. Description of the Related Art Soldering is widely used as a method for mounting electronic components on a substrate. As a form of mounting by solder bonding, there is known a method in which a solder bump, which is a protruding electrode of solder, is previously formed on an electrode of an electronic component or a substrate, and the solder bump is heated and melted to solder the electronic component to the substrate. . Conventionally, when soldering with solder bumps,
It has been common practice to apply a flux to the joint site and temporarily fix it, and to remove the oxide film on the solder surface by activating the flux to improve the solder jointability.
【０００３】[0003]
【発明が解決しようとする課題】従来上記フラックスを
使用する半田接合においては、フラックス中の腐食成分
を除去して実装後の信頼性を確保するため、半田接合後
の洗浄が必要とされていた。しかしながら近年この洗浄
は工程の複雑化・高コスト化が顕著であり、実装コスト
の低減を阻害する要因となっていた。このため半田接合
後の洗浄を必要としない、すなわちフラックスを使用し
ない実装方法が求められていた。この要求に応える方法
として、半田接合を還元雰囲気中で行う方法が用いられ
ているが、この方法では長い実装タクトタイムを要して
実装効率が悪い点など、生産性に問題があり一般的に採
用可能な実装方法とは云えないものであった。Conventionally, in soldering using the above flux, cleaning after soldering has been required in order to remove corrosion components in the flux and secure reliability after mounting. . However, in recent years, this cleaning has significantly increased the complexity and cost of the process, and has been a factor that hinders a reduction in mounting cost. For this reason, there has been a demand for a mounting method that does not require cleaning after soldering, that is, does not use flux. As a method to meet this demand, a method in which solder bonding is performed in a reducing atmosphere is used.However, this method requires a long mounting tact time and has a low mounting efficiency, and generally has a problem in productivity and has a problem in productivity. This was not a possible mounting method.
【０００４】そこで本発明は、フラックスを使用せずに
電子部品を効率よく半田接合により実装できる電子部品
の実装方法を提供することを目的とする。Accordingly, an object of the present invention is to provide a method for mounting an electronic component by which an electronic component can be efficiently mounted by soldering without using a flux.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の電子部品
の実装方法は、半田バンプを電極に接合することにより
電子部品を基板に実装する電子部品の実装方法であっ
て、前記電子部品を前記基板に搭載する際または搭載後
に振動付与手段により電子部品に振動を付与する工程
と、この電子部品が搭載された前記基板を加熱して前記
半田バンプを溶融させるリフロー工程とを含む。According to a first aspect of the present invention, there is provided a method for mounting an electronic component on a substrate by bonding a solder bump to an electrode. The method includes a step of applying vibration to the electronic component by a vibration applying unit when or after mounting on the substrate, and a reflow step of heating the substrate on which the electronic component is mounted to melt the solder bumps.
【０００６】請求項２記載の電子部品の実装方法は、請
求項１記載の電子部品の実装方法であって、前記リフロ
ー工程は還元雰囲気中で行われるようにした。According to a second aspect of the present invention, there is provided the electronic component mounting method according to the first aspect, wherein the reflow step is performed in a reducing atmosphere.
【０００７】本発明によれば、電子部品の搭載に際して
振動を付与して半田バンプを電極に仮止めし、その後リ
フロー工程で加熱して半田バンプを半田接合することに
より、効率よい実装を行うことができる。According to the present invention, efficient mounting can be performed by applying vibration to temporarily mount the solder bumps to the electrodes when mounting electronic components, and then heating the solder bumps in the reflow process to bond the solder bumps to the solder. Can be.
【０００８】[0008]
【発明の実施の形態】（実施の形態１）図１（ａ），
（ｂ），（ｃ），（ｄ），（ｅ）は、本発明の実施の形
態１の電子部品の実装方法の工程説明図である。本実施
の形態１は、電子部品に形成された半田バンプを基板の
電極に接合することにより電子部品を基板に実装するも
のである。図１（ａ）において、基板１には電極２が形
成されている。電極２は銅膜上に金メッキを施したもの
である。電極２としては、これ以外にもアルミなどの他
の良導体を用いたもの、また表面に半田がプリコートさ
れたものなど、半田接合性のよいものであれば本実施の
形態に用いることができる。(Embodiment 1) FIG. 1 (a),
(B), (c), (d), and (e) are process explanatory diagrams of the electronic component mounting method according to the first embodiment of the present invention. In the first embodiment, an electronic component is mounted on a substrate by bonding a solder bump formed on the electronic component to an electrode of the substrate. In FIG. 1A, an electrode 2 is formed on a substrate 1. The electrode 2 is formed by plating a copper film with gold. The electrode 2 can be used in the present embodiment as long as it has a good solder bonding property, such as an electrode using other good conductors such as aluminum, or an electrode having a surface pre-coated with solder.
【０００９】基板１上には半田バンプ４が形成された電
子部品３が搭載されている。半田バンプ４は電極２に位
置合わせされており、この状態で電子部品３には振動付
与手段である振動子６を備えた圧着ツール５により水平
方向の超音波振動が付与されるとともに、半田バンプ４
は電極２に対して押圧される。このときの押圧荷重や押
圧時間および超音波振動の条件は、半田バンプ４が電極
２の表面に対して摩擦されて表面の酸化膜が部分的に破
壊され、これらの半田バンプ４の幾つかが電極２と接合
されるような条件に設定される。すなわち、この過程で
の超音波圧接は、半田バンプ４表面の酸化膜の部分的除
去、および電子部品３を基板１に仮固定するために幾つ
かの半田バンプ４を接合する目的で行われるものであ
る。An electronic component 3 on which a solder bump 4 is formed is mounted on a substrate 1. The solder bump 4 is aligned with the electrode 2, and in this state, the electronic component 3 is subjected to horizontal ultrasonic vibration by a crimping tool 5 having a vibrator 6 as a vibration applying means, 4
Is pressed against the electrode 2. At this time, the conditions of the pressing load, the pressing time, and the ultrasonic vibration are such that the solder bump 4 is rubbed against the surface of the electrode 2 and the oxide film on the surface is partially destroyed, and some of these solder bumps 4 The conditions are set so as to be bonded to the electrode 2. That is, the ultrasonic pressure welding in this process is performed for the purpose of partially removing the oxide film on the surface of the solder bump 4 and joining several solder bumps 4 to temporarily fix the electronic component 3 to the substrate 1. It is.
【００１０】図１（ｂ）はこの超音波圧接により、電子
部品３の両端の半田バンプ４のみが電極２表面に部分的
に接合された状態を示している。なおこの超音波圧接を
行う過程は、電子部品３を別途移載ツールで基板１に搭
載した後に行っても、また移載ツールを兼ねた吸着機能
を有する超音波圧着ツールによって電子部品３を基板に
搭載し、その搭載の際に超音波圧接を同時に行うように
してもよい。また、この超音波圧接時に基板１を半田融
点以下の温度まで加熱するようにしてもよい。この加熱
により、超音波圧接を効率よく速やかに行うことができ
る。FIG. 1B shows a state in which only the solder bumps 4 at both ends of the electronic component 3 are partially joined to the surface of the electrode 2 by the ultrasonic pressure welding. The process of performing the ultrasonic pressure welding may be performed after the electronic component 3 is separately mounted on the substrate 1 by using a transfer tool, or the electronic component 3 may be bonded to the substrate by an ultrasonic pressure bonding tool having a suction function also serving as the transfer tool. And ultrasonic pressure welding may be performed at the same time. Further, the substrate 1 may be heated to a temperature lower than the melting point of the solder during the ultrasonic pressure welding. By this heating, ultrasonic pressure welding can be performed efficiently and promptly.
【００１１】次に、電子部品３が搭載され、仮固定され
た基板１は図１（ｃ）に示すようにリフロー工程に送ら
れ、半田融点温度以上に加熱される。これにより半田バ
ンプ４は溶融し、図１（ｄ）に示すように電極２に半田
接合される。このとき、半田バンプ４の表面は超音波振
動により電極２の表面に摩擦され、表面の酸化膜が部分
的に剥離しているため、半田バンプ４が溶融した溶融半
田は半田接合性の良い電極２の表面を濡らして良好に半
田接合される。なお、このリフロー工程を還元雰囲気中
で行うようにすることにより、さらに良好な半田接合性
を確保することができ、より信頼性の優れた実装を行う
ことができる。Next, the substrate 1 on which the electronic components 3 are mounted and temporarily fixed is sent to a reflow process as shown in FIG. As a result, the solder bumps 4 are melted and soldered to the electrodes 2 as shown in FIG. At this time, the surface of the solder bump 4 is rubbed against the surface of the electrode 2 by the ultrasonic vibration, and the oxide film on the surface is partially peeled off. 2 is wetted on the surface and soldered well. By performing this reflow step in a reducing atmosphere, it is possible to secure better solder jointability and to perform mounting with more excellent reliability.
【００１２】この後基板１はアンダーフィル工程に送ら
れる。ここでは電子部品３と基板１の間の隙間にノズル
７によりアンダーフィル樹脂が注入される。これにより
半田バンプ４と電極２の接合部の周囲は樹脂封止され、
これにより電子部品３の基板１への実装を完了する。Thereafter, the substrate 1 is sent to an underfill step. Here, an underfill resin is injected into the gap between the electronic component 3 and the substrate 1 by the nozzle 7. Thereby, the periphery of the joint between the solder bump 4 and the electrode 2 is sealed with resin,
Thus, the mounting of the electronic component 3 on the substrate 1 is completed.
【００１３】上記説明したように本実施の形態では、半
田バンプ４を電極２に接合する電子部品３の実装におい
て、従来電子部品３の仮固定と半田接合性の確保を目的
として行われていたフラックス塗布を、リフローに先立
って行われる超音波圧接によって置き換えたものであ
る。これにより、従来行われていた電極２へのフラック
ス塗布、または半田バンプ４へのフラックス転写などの
工程を削除することができ、従来必要とされていた半田
接合後の洗浄工程が不要となり、工程簡略化を図るとと
もに洗浄設備コストを削減することができる。As described above, in the present embodiment, the mounting of the electronic component 3 for bonding the solder bumps 4 to the electrodes 2 has conventionally been performed for the purpose of temporarily fixing the electronic component 3 and ensuring the solder bonding property. The flux application is replaced by ultrasonic pressure welding performed prior to reflow. As a result, it is possible to omit the step of applying flux to the electrode 2 or to transfer the flux to the solder bumps 4 which has been conventionally performed, so that the conventionally required cleaning step after solder bonding becomes unnecessary. The simplification can be achieved and the cost of the cleaning equipment can be reduced.
【００１４】なお本実施の形態１で示す超音波圧接は、
仮固定と酸化膜除去を目的として行われるものであるた
め、従来の超音波圧接のみで完全な接合を行うために必
要とされるような厳密な接合条件を満たす必要はない。
すなわち半田バンプの高さ寸法精度も多少のばらつきは
許容され、接合時間も短くてよく、また設備的にも高機
能なものは必要とされず簡便なものでよい。したがっ
て、従来超音波接合を行う場合に接合対象の電子部品や
実装装置に求められた条件が緩和され、総合的な実装コ
ストの削減が実現できる。The ultrasonic pressure welding shown in the first embodiment is
Since it is performed for the purpose of temporary fixing and removal of the oxide film, it is not necessary to satisfy strict bonding conditions required for performing complete bonding only by conventional ultrasonic pressure welding.
That is, the height dimension accuracy of the solder bumps may be slightly varied, the bonding time may be short, and a high-performance device is not required, and a simple device may be used. Therefore, when performing conventional ultrasonic bonding, the conditions required for the electronic components to be bonded and the mounting apparatus are relaxed, and a total reduction in mounting cost can be realized.
【００１５】（実施の形態２）図２（ａ），（ｂ），
（ｃ），（ｄ），（ｅ）は、本発明の実施の形態２の電
子部品の実装方法の工程説明図である。本実施の形態２
は、電子部品に形成された金属の突出電極である金属バ
ンプを、基板の電極上に形成された半田の突出電極とし
ての半田バンプ（半田プリコートとも呼ばれる）に接合
することにより、電子部品を基板に実装するものであ
る。(Embodiment 2) FIGS. 2 (a), (b),
(C), (d), and (e) are process explanatory views of the electronic component mounting method according to the second embodiment of the present invention. Embodiment 2
Is a method for joining an electronic component to a substrate by bonding a metal bump, which is a metal projecting electrode formed on the electronic component, to a solder bump (also referred to as solder precoat) as a solder projecting electrode formed on the electrode of the substrate. Is to be implemented.
【００１６】図２（ａ）において、基板１１上面の電極
１２の表面には半田バンプの一種である半田プリコート
１２ａが形成されている。基板１１上には、金属バンプ
１４が形成された電子部品１３が搭載されている。金属
バンプ１４は、金などの半田接合性の良い金属材質で形
成されている。In FIG. 2A, a solder precoat 12a, which is a kind of solder bump, is formed on the surface of the electrode 12 on the upper surface of the substrate 11. The electronic component 13 on which the metal bumps 14 are formed is mounted on the substrate 11. The metal bumps 14 are formed of a metal material having good solder bonding properties, such as gold.
【００１７】金属バンプ１４は電極１２に位置合わせさ
れており、この状態で実施の形態１と同様に電子部品１
３には振動付与手段である振動子を備えた圧着ツール５
により水平方向の超音波振動が付与されるとともに、金
属バンプ１４は半田プリコート１２ａに対して押圧され
る。このときの押圧荷重や押圧時間および超音波振動の
条件は、金属バンプ１４が半田プリコート１２ａに対し
て摩擦されて半田プリコート１２ａ表面の酸化膜が部分
的に破壊され、金属バンプ１４の幾つかが半田プリコー
ト１２ａと接合されるような条件に設定される。すなわ
ち本実施の形態２においても、この超音波圧接は半田プ
リコート１２ａ表面の酸化膜の部分的除去および電子部
品１３の基板１１への仮固定を目的として行われるもの
である。The metal bump 14 is aligned with the electrode 12, and in this state, the electronic component 1
Reference numeral 3 denotes a crimping tool 5 having a vibrator as a vibration imparting means.
As a result, ultrasonic vibration in the horizontal direction is applied, and the metal bumps 14 are pressed against the solder precoat 12a. At this time, the conditions of the pressing load, the pressing time, and the ultrasonic vibration are such that the metal bump 14 is rubbed against the solder precoat 12a, the oxide film on the surface of the solder precoat 12a is partially broken, and some of the metal bumps 14 The conditions are set so as to be joined to the solder precoat 12a. That is, also in the second embodiment, the ultrasonic pressure welding is performed for the purpose of partially removing the oxide film on the surface of the solder precoat 12a and temporarily fixing the electronic component 13 to the substrate 11.
【００１８】図２（ｂ）は、この超音波圧接により電子
部品１３の両端の金属バンプ１４のみが半田プリコート
１２ａに部分的に接合された状態を示している。この超
音波圧接を行う過程は、実施の形態１において述べたよ
うに、電子部品１３の基板１１への搭載後に行ってもよ
く、また搭載時に同時に行ってもよい。FIG. 2B shows a state in which only the metal bumps 14 at both ends of the electronic component 13 are partially joined to the solder precoat 12a by the ultrasonic pressure welding. The process of performing the ultrasonic pressure welding may be performed after the electronic component 13 is mounted on the substrate 11 as described in the first embodiment, or may be performed simultaneously with the mounting.
【００１９】次に基板１１はリフロー工程に送られ、加
熱により半田プリコート１２ａを溶融させて金属バンプ
１４を電極１２と半田接合する。このとき、フラックス
を使用する必要がないことおよびその効果については実
施の形態１と同様である。なお、本実施の形態２に示す
ように、電子部品として金属バンプ１４が形成されたも
のを採用することにより、金属バンプ形成に際しワイヤ
ボンディングなど簡略な工程手段によりバンプ形成が行
え、したがって低コストで前述の効果を備えた電子部品
の実装を行うことができるという利点を有している。ま
た電子部品１３に設けられた電極として本実施の形態２
では金属バンプ１４を用いているが、半田接合性の良い
材質であれば、これ以外の一般の形状の電極であっても
よい。Next, the substrate 11 is sent to a reflow process, in which the solder precoat 12a is melted by heating, and the metal bumps 14 are soldered to the electrodes 12. At this time, there is no need to use a flux and the effect is the same as in the first embodiment. As shown in the second embodiment, by adopting an electronic component on which the metal bumps 14 are formed, the bumps can be formed by a simple process such as wire bonding when forming the metal bumps. There is an advantage that an electronic component having the above-described effects can be mounted. In the second embodiment, an electrode provided on the electronic component 13 is used.
Although the metal bumps 14 are used in this embodiment, any other material having a general shape may be used as long as the material has good solder bonding properties.
【００２０】[0020]
【発明の効果】本発明によれば、電子部品の搭載に際し
て振動を付与して半田バンプを仮止めし、その後リフロ
ー工程で加熱して半田バンプを半田接合するようにした
ので、半田接合による電子部品の実装をフラックスを使
用することなく効率よく行うことができる。According to the present invention, when mounting electronic components, vibration is applied to temporarily fix the solder bumps, and then the solder bumps are soldered by heating in a reflow process. Components can be mounted efficiently without using flux.
【図１】（ａ）本発明の実施の形態１の電子部品の実装
方法の工程説明図 （ｂ）本発明の実施の形態１の電子部品の実装方法の工
程説明図 （ｃ）本発明の実施の形態１の電子部品の実装方法の工
程説明図 （ｄ）本発明の実施の形態１の電子部品の実装方法の工
程説明図 （ｅ）本発明の実施の形態１の電子部品の実装方法の工
程説明図FIG. 1A is a process explanatory view of an electronic component mounting method according to a first embodiment of the present invention. FIG. 1B is a process explanatory view of an electronic component mounting method according to a first embodiment of the present invention. Process description diagram of electronic component mounting method according to Embodiment 1 (d) Process description diagram of electronic component mounting method according to Embodiment 1 of the present invention (e) Electronic component mounting method according to Embodiment 1 of the present invention Process description diagram
【図２】（ａ）本発明の実施の形態２の電子部品の実装
方法の工程説明図 （ｂ）本発明の実施の形態２の電子部品の実装方法の工
程説明図 （ｃ）本発明の実施の形態２の電子部品の実装方法の工
程説明図 （ｄ）本発明の実施の形態２の電子部品の実装方法の工
程説明図 （ｅ）本発明の実施の形態２の電子部品の実装方法の工
程説明図FIG. 2A is a process explanatory view of an electronic component mounting method according to a second embodiment of the present invention. FIG. 2B is a process explanatory view of an electronic component mounting method according to a second embodiment of the present invention. Process explanatory diagram of the electronic component mounting method of the second embodiment (d) Process explanatory diagram of the electronic component mounting method of the second embodiment of the present invention (e) Electronic component mounting method of the second embodiment of the present invention Process description diagram
【符号の説明】 １、１１ 基板 ２、１２ 電極 ３、１３ 電子部品 ４ 半田バンプ ５ 圧着ツール ６ 振動子 １２ａ 半田プリコート １４ 金属バンプ[Description of Signs] 1,11 Substrate 2,12 Electrode 3,13 Electronic Component 4 Solder Bump 5 Crimping Tool 6 Vibrator 12a Solder Precoat 14 Metal Bump
Claims (2)
子部品を基板に実装する電子部品の実装方法であって、
前記電子部品を前記基板に搭載する際または搭載後に振
動付与手段により電子部品に振動を付与する工程と、こ
の電子部品が搭載された前記基板を加熱して前記半田バ
ンプを溶融させるリフロー工程とを含むことを特徴とす
る電子部品の実装方法。An electronic component mounting method for mounting an electronic component on a substrate by bonding a solder bump to an electrode,
A step of applying vibration to the electronic component by vibration applying means when or after mounting the electronic component on the substrate, and a reflow step of heating the substrate on which the electronic component is mounted and melting the solder bumps. A method for mounting an electronic component, comprising:
ることを特徴とする請求項１記載の電子部品の実装方
法。2. The method according to claim 1, wherein the reflow step is performed in a reducing atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10350092A JP2000174059A (en) | 1998-12-09 | 1998-12-09 | Method of mounting electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10350092A JP2000174059A (en) | 1998-12-09 | 1998-12-09 | Method of mounting electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000174059A true JP2000174059A (en) | 2000-06-23 |
Family
ID=18408188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10350092A Pending JP2000174059A (en) | 1998-12-09 | 1998-12-09 | Method of mounting electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000174059A (en) |
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| JP2007128982A (en) * | 2005-11-01 | 2007-05-24 | Nec Corp | Semiconductor bump connection structure and its manufacturing method |
| WO2008041484A1 (en) * | 2006-09-26 | 2008-04-10 | Alps Electric Co., Ltd. | Elastic contact and method for bonding between metal terminals using the same |
| JP2008218528A (en) * | 2007-02-28 | 2008-09-18 | Fujitsu Ltd | Method for mounting electronic part and production device |
| JP2009123918A (en) * | 2007-11-15 | 2009-06-04 | Fujitsu Ltd | Semiconductor device and manufacturing method for the semiconductor device |
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| JP2011077193A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Method for manufacturing semiconductor device |
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- 1998-12-09 JP JP10350092A patent/JP2000174059A/en active Pending
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| JP2011077193A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Method for manufacturing semiconductor device |
| CN103477424A (en) * | 2011-02-02 | 2013-12-25 | 派克泰克封装技术有限公司 | Method and device for the electrical bonding of connection areas of two substrates by laser soldering using a gaseous flux medium |
| US9649711B2 (en) | 2011-02-02 | 2017-05-16 | Pac Tech-Packaging Technologies Gmbh | Method and device for electrically contacting terminal faces of two substrates by laser soldering using a gaseous flux medium |
| JP2018516460A (en) * | 2015-05-29 | 2018-06-21 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ | Optoelectronic component and method of manufacturing optoelectronic component |
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