JP2007134489A - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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JP2007134489A
JP2007134489A JP2005325952A JP2005325952A JP2007134489A JP 2007134489 A JP2007134489 A JP 2007134489A JP 2005325952 A JP2005325952 A JP 2005325952A JP 2005325952 A JP2005325952 A JP 2005325952A JP 2007134489 A JP2007134489 A JP 2007134489A
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semiconductor chip
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Mitsuhiro Nakao
光博 中尾
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Toshiba Corp
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which, after a flip-chip connection is completed, an underfill resin layer is formed between a semiconductor chip and a wiring board, and even after this layer is cured, the wiring board and the semiconductor chip are warked less or a connection is broken less. <P>SOLUTION: The method for manufacturing a semiconductor device comprises the steps of: sucking a board 9 which comprises a plurality of wiring boards having a chip mounting area 14 to an upper face of a stage 1 having the upper face as a vacuum sucking face; mounting the semiconductor chip to the chip mounting area 14 of the board 9 retained by the stage 1, so that the semiconductor chip is connected to the board 9 by a flip-chip condition; thereafter, pouring a liquid-like resin 12 into between the board 9 and the semiconductor chip on the stage 1, in a state that the board 9 is retained by vacuum sucking and heating and curing the liquid-like resin 12 poured on the stage 1, in a state that the board 9 is retained by vacuum sucking to form an underfill resin layer 15. Thereafter, a lamination of chips, a bonding wire and a resin sealing, etc. are performed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、一つの半導体パッケージの中に半導体チップを複数個積層した半導体装置の製造方法及びこの製造方法により製造された半導体装置に関するものである。   The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked in one semiconductor package, and a semiconductor device manufactured by this manufacturing method.

従来のチップ積層型半導体装置は、チップサイズの比較的大きなメモリチップを複数段積み重ねた構造が多く、これらの構造は、配線基板との接続方法として全てワイヤボンディングを用いていた。しかし、近年ではロジックチップとメモリチップを混載させて積層する半導体装置が出現してきた。ロジックチップの場合は、電極パッド数が３００〜５００パッドと非常に多く、ワイヤボンディングで接続すると、配線基板側にそのパッド数と同じ数のインナーリードが必要となる。そうなると、半導体装置の外形サイズが大型化してしまうのでロジックチップのみフリップチップボンディング法を用いて接続させ、他のチップはワイヤボンディング法を用いて接続する方法がとられている。しかも、半導体チップを一つのパッケージに積層するのでそれぞれの半導体チップの厚さが１００μｍ以下と非常に薄くなっている。同時に配線基板の厚さも２００μｍ程度と薄くなっているのが現状である。フリップチップ接続において、半導体チップが薄いと言うのは、さまざまな面で問題が生じ製造面での難易度も高い。   Many conventional chip-stacked semiconductor devices have a structure in which a plurality of memory chips having a relatively large chip size are stacked, and these structures all use wire bonding as a connection method with a wiring board. However, in recent years, a semiconductor device in which a logic chip and a memory chip are mixed and stacked has appeared. In the case of a logic chip, the number of electrode pads is as large as 300 to 500 pads, and when connected by wire bonding, the same number of inner leads as the number of pads is required on the wiring board side. In this case, since the outer size of the semiconductor device is increased, only the logic chip is connected using the flip chip bonding method, and the other chips are connected using the wire bonding method. In addition, since the semiconductor chips are stacked in one package, the thickness of each semiconductor chip is as very thin as 100 μm or less. At the same time, the thickness of the wiring board is as thin as about 200 μm. In flip chip connection, the fact that the semiconductor chip is thin has problems in various aspects and is difficult to manufacture.

そのうちの一つが、半導体チップや配線基板の剛性不足によって生ずる反りである。フリップチップ接続時には配線基板は平坦なステージ上に真空吸着によって固定され、半導体チップもボンディングツールによって平坦に吸着固定されている。この状態で接続時に２００℃以上の温度が加わっても、お互いが平坦であるため正常に接続が行われる。しかし、接続が終了しボンディングステージによる真空吸着から配線基板を開放した瞬間に配線基板や半導体チップが反り上がり、接続部が破断してしまうという問題が生じている。
この問題が解決されないと、半導体チップの厚さを薄くすることができず、その結果半導体パッケージの厚さが顧客の要求する寸法に納められないという問題が生ずる。また、半導体チップの積み重ね枚数も減少するため高機能な半導体装置を生み出すことが出来ない。従来技術として特許文献１が開示されている。特許文献１には、回路基板を基板保持具により平坦に固定し、素子を該回路基板にフェイスダウン接続することが記載されている。更にアンダーフィル剤を充填し硬化させた後に回路基板を基板保持具から取り外す半導体装置の製造方法が記載されている。
特開平９−２１３７３８号公報 One of them is warpage caused by insufficient rigidity of the semiconductor chip or the wiring board. At the time of flip chip connection, the wiring board is fixed on a flat stage by vacuum suction, and the semiconductor chip is also fixed by vacuum bonding with a bonding tool. Even if a temperature of 200 ° C. or higher is applied at the time of connection in this state, the connection is normally performed because the two are flat. However, at the moment when the connection is completed and the wiring board is released from the vacuum suction by the bonding stage, the wiring board and the semiconductor chip are warped and the connection portion is broken.
If this problem is not solved, the thickness of the semiconductor chip cannot be reduced, resulting in a problem that the thickness of the semiconductor package cannot be accommodated in the dimensions required by the customer. In addition, since the number of stacked semiconductor chips is reduced, a highly functional semiconductor device cannot be produced. Patent document 1 is disclosed as a prior art. Patent Document 1 describes that a circuit board is fixed flat by a board holder and elements are face-down connected to the circuit board. Further, there is described a method for manufacturing a semiconductor device in which a circuit board is removed from a substrate holder after filling and curing an underfill agent.
JP-A-9-213738

本発明は、フリップチップ接続が終了した後において半導体チップと配線基板間にアンダーフィル樹脂層を形成し、これを硬化させた後でも配線基板や半導体チップの反り上がり、接続部の破断が少ない半導体装置の製造方法及びこの方法により形成された半導体装置を提供する。   The present invention is a semiconductor in which an underfill resin layer is formed between a semiconductor chip and a wiring board after flip chip connection is completed, and the wiring board and the semiconductor chip are warped and the connection portion is less broken even after this is cured. An apparatus manufacturing method and a semiconductor device formed by the method are provided.

本発明の半導体装置の製造方法の一態様は、チップ搭載エリアを有する配線基板の複数個から構成された基板を上面が真空吸着面となるステージ上面に吸着させる工程と、前記ステージにより保持された基板の前記チップ搭載エリアに半導体チップを搭載して前記基板に前記半導体チップをフリップチップ接続する工程と、前記基板を真空吸着により保持した状態でステージ上で前記基板と前記半導体チップ間に液状樹脂を流し込む工程と、前記基板を真空吸着により保持した状態でステージ上で前記流し込んだ液状樹脂を加熱硬化させてアンダーフィル樹脂層を形成する工程とを備えたことを特徴としている。   According to one aspect of the method for manufacturing a semiconductor device of the present invention, a substrate composed of a plurality of wiring substrates having chip mounting areas is adsorbed on an upper surface of a stage whose upper surface is a vacuum adsorption surface, and held by the stage Mounting a semiconductor chip in the chip mounting area of the substrate and flip-chip connecting the semiconductor chip to the substrate; and a liquid resin between the substrate and the semiconductor chip on the stage while the substrate is held by vacuum suction And a step of forming an underfill resin layer by heat-curing the poured liquid resin on a stage while the substrate is held by vacuum suction.

また、本発明の半導体装置の一態様は、少なくとも２層積層された複数の半導体チップと、外部接続端子を備え、前記積層された複数の半導体チップを搭載する配線基板とを備え、前記配線基板に直接接続される第１層の半導体チップは、前記配線基板にフリップチップ接続され、且つ前記第１層の半導体チップと前記配線基板との間隙にアンダーフィル樹脂層が形成され、前記第１層の半導体チップに積層される第２層以上の半導体チップは、ボンディングワイヤにより前記配線基板に電気的に接続され、前記第１層の半導体チップの膜厚は１００μｍ以下であり、前記配線基板は２００μｍを越えない膜厚を有することを特徴としている。   According to another aspect of the semiconductor device of the present invention, the wiring board includes a plurality of semiconductor chips stacked at least in two layers, and a wiring board that includes an external connection terminal and mounts the plurality of stacked semiconductor chips. The first-layer semiconductor chip directly connected to the wiring board is flip-chip connected to the wiring board, and an underfill resin layer is formed in a gap between the first-layer semiconductor chip and the wiring board. The semiconductor chips of the second layer and higher layers stacked on the semiconductor chip are electrically connected to the wiring board by bonding wires, the thickness of the semiconductor chip of the first layer is 100 μm or less, and the wiring board is 200 μm. It is characterized by having a film thickness that does not exceed.

フリップチップ接続が終了した後において半導体チップと配線基板間にアンダーフィル樹脂層を形成し、これを硬化させた後でも配線基板や半導体チップの反り上がりや接続部の破断が少ない。   After the flip-chip connection is completed, an underfill resin layer is formed between the semiconductor chip and the wiring board, and even after this is cured, there is little warping of the wiring board or the semiconductor chip and breakage of the connection portion.

以下、実施例を参照して発明の実施の形態を説明する。   Hereinafter, embodiments of the invention will be described with reference to examples.

図１乃至図９を参照して実施例１を説明する。
図１は、基板を搭載させるステージの平面図及び断面図、図２及び図３は、フリップチップ接続を説明する部分工程断面図、図４及び図５は、半導体チップと基板間に液状樹脂を流し込む部分工程断面図、図６は、ステージに基板を搭載してからアンダーフィル樹脂層を形成するまでの工程斜視図、図７は、図６の工程を処理する半導体製造装置の概略斜視図、図８は、半導体装置の製造工程を説明するフロー図、図９は、半導体装置の断面図である。 Embodiment 1 will be described with reference to FIGS.
FIG. 1 is a plan view and a cross-sectional view of a stage on which a substrate is mounted, FIGS. 2 and 3 are partial process cross-sectional views for explaining flip-chip connection, and FIGS. 4 and 5 are liquid resins between a semiconductor chip and a substrate. FIG. 6 is a perspective view of a process from mounting a substrate on the stage to forming an underfill resin layer, and FIG. 7 is a schematic perspective view of a semiconductor manufacturing apparatus for processing the process of FIG. FIG. 8 is a flowchart for explaining a manufacturing process of the semiconductor device, and FIG. 9 is a cross-sectional view of the semiconductor device.

この実施例で説明する半導体装置（図９参照）は、図８に示すように、次のような工程で製造される。まず、配線基板の複数個から構成された基板を真空吸着面となるステージ上面に吸着させる（工程（１））。次に、前記ステージにより保持された基板の前記チップ搭載エリアに半導体チップを搭載して前記基板に前記半導体チップをフリップチップ接続する（工程（２））。次に、前記基板を真空吸着により保持した状態でステージ上で前記基板と前記半導体チップ間に液状樹脂を流し込む（工程（３））。次に、前記基板を真空吸着により保持した状態でステージ上で前記流し込んだ液状樹脂を加熱硬化させてアンダーフィル樹脂層を形成する（工程４））。アンダーフィル樹脂層を形成してから基板をステージから外す（工程（５））。その後、２層以上の半導体チップをフリップチップ接続した半導体チップ上に積層し、これらと基板との電気的接続をボンディングワイヤにより行う（工程（６））。次に、基板上に積層形成された半導体チップを樹脂封止すべく、基板上にモールド樹脂封止体を形成する（工程（７））。その後、配線基板単位に基板ダイシングを行って、図９に示す半導体パッケージ（半導体装置）が形成される（工程（８））。   The semiconductor device described in this embodiment (see FIG. 9) is manufactured by the following process as shown in FIG. First, a substrate composed of a plurality of wiring substrates is adsorbed on the upper surface of the stage serving as a vacuum adsorption surface (step (1)). Next, a semiconductor chip is mounted on the chip mounting area of the substrate held by the stage, and the semiconductor chip is flip-chip connected to the substrate (step (2)). Next, a liquid resin is poured between the substrate and the semiconductor chip on the stage with the substrate held by vacuum suction (step (3)). Next, in a state where the substrate is held by vacuum suction, the poured liquid resin is heated and cured on a stage to form an underfill resin layer (step 4). After forming the underfill resin layer, the substrate is removed from the stage (step (5)). Thereafter, two or more layers of semiconductor chips are stacked on the flip-chip connected semiconductor chips, and these are electrically connected to the substrate by bonding wires (step (6)). Next, a molded resin sealing body is formed on the substrate in order to resin-seal the semiconductor chip laminated on the substrate (step (7)). Thereafter, substrate dicing is performed for each wiring substrate to form the semiconductor package (semiconductor device) shown in FIG. 9 (step (8)).

このような半導体装置を形成する工程において、工程（２）乃至工程（４）にこの実施例の特徴がある。以下、図１及び図７、図２乃至図５を参照しながら図６の工程斜視図に基づいて工程（２）乃至工程（４）を詳細に説明する。
この工程は、図７の半導体製造装置を用いて処理される。この半導体製造装置は、フリップチップ接続を行うＦＣ部、アンダーフィル樹脂層の材料である液状樹脂を基板上に流し込むアンダーフィル部及び液状樹脂を加熱して硬化させるアフターキュア炉から構成されており、各部は、ステージ搬送レールによって連絡がつけられている。ステージ搬送レールは、基板を真空吸着したステージを各部に適宜搬送するように構成されている。
図１は、この実施例で用いられるステージ１の一例である。ステージ１上面には複数の８の字形状の吸着溝３が形成されており、吸着溝３はステージ１内部の吸着孔２に繋がり、吸着孔２は、真空ポンプ（図示しない）に繋がるパイプ１３に接続されている。吸着溝３は、真空ポンプに引かれて真空４になり、基板を吸着する吸着力を有するようになる。この時、チップ搭載エリアには吸着孔及び吸着溝が重ならないようにする。もし重ねると、この部分の吸着孔もしくは吸着溝に吸着されて基板から半導体チップが離れる恐れがあるからである。 In the process of forming such a semiconductor device, the steps (2) to (4) are characterized by this embodiment. Hereinafter, the process (2) to the process (4) will be described in detail based on the process perspective view of FIG. 6 with reference to FIGS. 1, 7, and 2 to 5.
This step is processed using the semiconductor manufacturing apparatus of FIG. This semiconductor manufacturing apparatus is composed of an FC section for flip-chip connection, an underfill section for pouring a liquid resin, which is a material for the underfill resin layer, onto the substrate, and an after cure furnace for heating and curing the liquid resin. Each part is connected by a stage transport rail. The stage transport rail is configured to appropriately transport a stage on which the substrate is vacuum-sucked to each part.
FIG. 1 is an example of a stage 1 used in this embodiment. A plurality of 8-shaped suction grooves 3 are formed on the upper surface of the stage 1, the suction grooves 3 are connected to the suction holes 2 inside the stage 1, and the suction holes 2 are pipes 13 connected to a vacuum pump (not shown). It is connected to the. The suction groove 3 is pulled by a vacuum pump to become a vacuum 4 and has a suction force for sucking the substrate. At this time, the suction hole and the suction groove should not overlap with the chip mounting area. If they are stacked, the semiconductor chip may be separated from the substrate by being adsorbed by the adsorbing holes or adsorbing grooves in this portion.

図６（ａ）に示すように、複数のチップ搭載エリア１４を有する（この実施例では、例えば、１２エリアである）基板９を真空ポンプによりパイプを介して真空４引きされた吸着溝３の吸着力により基板サイズに合わせた形状のステージ１上面に固定する。基板９は、ステージ１より一回り小さくなるように構成されている。吸着溝も基板の形状や半導体チップのサイズに合わせて最適な場所に設置する。
次に、図６（ｂ）に示すように、フリップチップボンディングツール１０を用いて半導体チップ５を基板９のチップ搭載エリア１４にフリップチップ接続する。その詳細は図２及び図３に示される。ステージ１上の基板９には基板インナーリード（配線）８が形成され、その上には接続用の金属７、例えば、Ｓｎ−Ａｇが形成されている。一方、半導体チップ５は、表面の接続電極（図示しない）の上にバンプ電極６が設けられている。 As shown in FIG. 6A, the substrate 9 having a plurality of chip mounting areas 14 (in this embodiment, for example, 12 areas) is formed in the suction groove 3 in which the substrate 9 is vacuum-evacuated 4 through a pipe by a vacuum pump. It is fixed to the upper surface of the stage 1 having a shape matched to the substrate size by an adsorption force. The substrate 9 is configured to be slightly smaller than the stage 1. The suction groove is also installed at an optimum location according to the shape of the substrate and the size of the semiconductor chip.
Next, as shown in FIG. 6B, the semiconductor chip 5 is flip-chip connected to the chip mounting area 14 of the substrate 9 using the flip chip bonding tool 10. The details are shown in FIGS. A substrate inner lead (wiring) 8 is formed on the substrate 9 on the stage 1, and a connection metal 7, for example, Sn—Ag is formed thereon. On the other hand, the semiconductor chip 5 is provided with a bump electrode 6 on a connection electrode (not shown) on the surface.

半導体チップ５は、フリップチップボンディングツール１０によって保持され、ステージ１上に搬送される（図２）。フリップチップボンディングツール１０は、複数の吸着孔２′を有し、これを真空４′にすることにより吸着力を得ている。フリップチップボンディングツール１０により保持された半導体チップ５は、自動認識によって基板インナーリード（配線）８と位置合せを行い圧着を行ってバンプ電極６と接続用の金属７とを接合する（図３）。この際、接続部の金属同士を接合させるために最適な温度と荷重と時間を加える。また、ステージ１は、基板９全体を加熱するヒータを兼ねるようにすることができる。この工程は図７のＦＣ部で行われる。
次に、図６（ｃ）に示すように、基板９をステージ１に真空吸着した状態で、エポキシ樹脂などの液状封止樹脂１２を半導体チップ５の側面から流し込む。その詳細は図４に示される。即ち、液状樹脂１２は、液状封止樹脂塗布用ノズル１１を半導体チップ５に近接させて、半導体チップ５とステージ１に真空吸着された基板９との間であって、フリップチップ接続されたバンプ電極６と基板インナーリード８上の接続用の金属７との接続により形成された間隙に流し込まれる。この工程は、図７のアンダーフィル部で行われる。 The semiconductor chip 5 is held by the flip chip bonding tool 10 and transferred onto the stage 1 (FIG. 2). The flip chip bonding tool 10 has a plurality of suction holes 2 ', and obtains suction force by making them vacuum 4'. The semiconductor chip 5 held by the flip chip bonding tool 10 is aligned with the substrate inner lead (wiring) 8 by automatic recognition, and is crimped to join the bump electrode 6 and the connecting metal 7 (FIG. 3). . At this time, an optimum temperature, load, and time are added to join the metals in the connection portion. Further, the stage 1 can also serve as a heater for heating the entire substrate 9. This process is performed in the FC section of FIG.
Next, as shown in FIG. 6C, a liquid sealing resin 12 such as an epoxy resin is poured from the side surface of the semiconductor chip 5 in a state where the substrate 9 is vacuum-adsorbed on the stage 1. The details are shown in FIG. That is, the liquid resin 12 is a bump which is flip-chip connected between the semiconductor chip 5 and the substrate 9 vacuum-adsorbed to the stage 1 by bringing the liquid sealing resin coating nozzle 11 close to the semiconductor chip 5. It is poured into the gap formed by the connection between the electrode 6 and the connecting metal 7 on the substrate inner lead 8. This step is performed at the underfill portion in FIG.

次に、図６（ｄ）に示すように、基板９をステージ１に真空吸着した状態で、液状封止樹脂１２が硬化するまでステージ１上に保持する。その詳細は図５に示される。液状樹脂１２は、半導体チップ５とステージ１に真空吸着された基板９との間に充填され、バンプ電極６と基板インナーリード８上の接続用の金属７との接続部を被覆している。この状態で図７のアフターキュア炉で加熱されて硬化してアンダーフィル樹脂層１５が形成される。
その後、基板９はステージ１から下され、後工程である工程（６）乃至工程（８）を実施して図９に示す半導体装置が形成される。基板をダイシングして得られた配線基板１６は、配線（基板インナーリード）８を有し、裏面にはんだボールなどの外部接続端子１８が形成されている。配線８と外部接続端子１８とは内部配線１７により接続されている。配線基板１６に直接接続された第１層の半導体チップ（チップＡ）５は、前述の工程（２）乃至工程（４）により形成されたものである。半導体チップ５の上には第２層の半導体チップ（チップＢ）が接着剤により接着され積層されている。 Next, as shown in FIG. 6D, the substrate 9 is held on the stage 1 until the liquid sealing resin 12 is cured in a state where the substrate 9 is vacuum-adsorbed on the stage 1. The details are shown in FIG. The liquid resin 12 is filled between the semiconductor chip 5 and the substrate 9 vacuum-adsorbed on the stage 1, and covers the connecting portion between the bump electrode 6 and the connecting metal 7 on the substrate inner lead 8. In this state, the underfill resin layer 15 is formed by heating and curing in the after-curing furnace of FIG.
Thereafter, the substrate 9 is lowered from the stage 1, and the subsequent steps (6) to (8) are performed to form the semiconductor device shown in FIG. The wiring substrate 16 obtained by dicing the substrate has wiring (substrate inner leads) 8 and external connection terminals 18 such as solder balls are formed on the back surface. The wiring 8 and the external connection terminal 18 are connected by an internal wiring 17. The first-layer semiconductor chip (chip A) 5 directly connected to the wiring board 16 is formed by the above-described steps (2) to (4). On the semiconductor chip 5, a second layer semiconductor chip (chip B) is adhered and laminated with an adhesive.

チップＢに形成された接続電極（図示しない）と配線基板１６の配線８とはボンディングワイヤ１９により電気的に接続されている。チップＢの上には第３層の半導体チップ（チップＣ）が接着剤により接着され積層されている。これは、スペーサチップといわれ、配線及び素子が形成されない単なるシリコンチップである。これは、チップＢのワイヤボンディングスペースを設けるために形成されたものである。チップＣの上には第４層の半導体チップ（チップＤ）が接着剤により接着され積層されている。チップＤに形成された接続電極（図示しない）と配線基板１６の配線８とはボンディングワイヤ１９′により電気的に接続されている。配線基板１６上には積層された半導体チップ及びボンディングワイヤ等を含めて樹脂封止体２０により樹脂封止されている。チップＡには、電極数の多い、例えば、２００パッド以上の、例えば、ロジックチップなどが適用される。チップＢ及びチップＤには、例えば、メモリチップが用いられる。チップＡの膜厚は１００μｍ以下であり、配線基板の膜厚は、２００μｍより薄く形成されている。   Connection electrodes (not shown) formed on the chip B and the wiring 8 of the wiring board 16 are electrically connected by bonding wires 19. On the chip B, a third-layer semiconductor chip (chip C) is bonded and laminated with an adhesive. This is called a spacer chip, which is a simple silicon chip in which no wiring and elements are formed. This is formed to provide a wire bonding space for the chip B. On the chip C, a fourth layer semiconductor chip (chip D) is bonded and laminated with an adhesive. A connection electrode (not shown) formed on the chip D and the wiring 8 of the wiring board 16 are electrically connected by a bonding wire 19 ′. The wiring board 16 is resin-sealed with a resin sealing body 20 including the stacked semiconductor chips and bonding wires. For the chip A, for example, a logic chip having a large number of electrodes, for example, 200 pads or more is applied. As the chip B and the chip D, for example, a memory chip is used. The film thickness of the chip A is 100 μm or less, and the film thickness of the wiring board is formed to be thinner than 200 μm.

１００μｍ以下の半導体チップをフリップチップ接続により搭載しても、アンダーフィル樹脂層を硬化させた後での配線基板や半導体チップの反り上がりや接続部の破断が少なく、その結果、多数の半導体チップを一つのパッケージに積層することが可能になる。また、パッケージの厚さも薄くする事が可能となる。また、半導体チップと基板をお互い平坦なツールやステージで固定しているため、高い位置精度のフリップチップ接続が可能となり、位置ズレ不良などの品質不良が減少可能になる。また、フリップチップ接続終了後も基板をステージ上で保持し続けるので、熱収縮などによる基板の反りを防止して接続部の破断を防ぐことが可能となる。また、この状態で液状封止樹脂を流し込んでいるので樹脂の均等な流動により安定した封止が可能となる。また、配線基板や半導体チップの反り上がりや接続部の破断が少ないので、２００μｍより薄い配線基板を用いることが可能になって半導体パッケージの一層の薄膜化が可能になる。   Even when a semiconductor chip of 100 μm or less is mounted by flip chip connection, there is little warping of the wiring board or semiconductor chip after the underfill resin layer is cured and breakage of the connection portion. It can be stacked in one package. Further, the thickness of the package can be reduced. Further, since the semiconductor chip and the substrate are fixed to each other with a flat tool or stage, flip chip connection with high positional accuracy is possible, and quality defects such as misalignment can be reduced. Further, since the substrate is continuously held on the stage even after the flip chip connection is completed, the warpage of the substrate due to heat shrinkage or the like can be prevented, and the breakage of the connection portion can be prevented. In addition, since the liquid sealing resin is poured in this state, stable sealing is possible by the uniform flow of the resin. Further, since there is little warping of the wiring board or semiconductor chip or breakage of the connecting portion, it is possible to use a wiring board thinner than 200 μm, and the semiconductor package can be made thinner.

次に、図１０を参照して実施例２を説明する。
図１０は、基板の平面図及びステージの上面に設けた基板吸着面を示す平面図である。この実施例では、ステージの基板吸着面に特徴がある。この実施例で説明する基板２１は、複数のチップ搭載エリア２２を備え、ダイシングにより複数の配線基板に個片化される。基板２１は、ステージに完全に載ることができるようにこれらステージより一回り小さいものが用いられる（図１０（ａ））。
実施例１ではステージ上面の吸着面は、８の字を複数配列した形状の吸着溝を用いたが、この実施例の第１の例ではステージ２３上面の吸着溝２４は、Ｈの字を複数配列した形状になっている。吸着孔（図示しない）は、各Ｈの字に少なくとも１つ設けられている（図１０（ｂ））。
第２の例では、ステージ２５上面の吸着面には吸着溝が形成されていない。所定の間隔で吸着孔２６がならんでいるのみである（図１０（ｃ））。 Next, Example 2 will be described with reference to FIG.
FIG. 10 is a plan view of a substrate and a substrate suction surface provided on the upper surface of the stage. This embodiment is characterized by the substrate suction surface of the stage. The substrate 21 described in this embodiment includes a plurality of chip mounting areas 22 and is separated into a plurality of wiring substrates by dicing. A substrate 21 that is slightly smaller than these stages is used so that it can be completely mounted on the stages (FIG. 10A).
In the first embodiment, the suction surface on the upper surface of the stage uses a suction groove having a shape in which a plurality of 8 characters are arranged. In the first example of this embodiment, the suction groove 24 on the upper surface of the stage 23 has a plurality of H characters. It has an arrayed shape. At least one suction hole (not shown) is provided for each H-shape (FIG. 10B).
In the second example, no suction groove is formed on the suction surface of the upper surface of the stage 25. Only the suction holes 26 are lined up at a predetermined interval (FIG. 10C).

以上の通り、吸着面の構造は、実施例に限定されず様々な構造が考えられる。しかし、基板に設けられたチップ搭載エリアにはステージの吸着孔及び吸着溝が重ならないようにすることが必要である。何故なら、ステージの吸着孔もしくは吸着溝の上にチップ搭載エリアが載置されると、この部分の吸着孔もしくは吸着溝に基板が吸着されて基板から半導体チップが離れる恐れがあるからである。チップが基板から離れることによって接続部の破断が発生する恐れが大きくなるのである。   As described above, the structure of the suction surface is not limited to the embodiment, and various structures are conceivable. However, it is necessary to prevent the suction holes and suction grooves of the stage from overlapping the chip mounting area provided on the substrate. This is because if the chip mounting area is placed on the suction hole or suction groove of the stage, the substrate may be sucked into the suction hole or suction groove of this part and the semiconductor chip may be separated from the substrate. The risk of breakage of the connection portion increases as the chip moves away from the substrate.

本発明の一実施例である実施例１の基板を搭載させるステージの平面図及び断面図。The top view and sectional drawing of the stage which mounts the board | substrate of Example 1 which is one Example of this invention. 本発明の一実施例である実施例１のフリップチップ接続を説明する部分工程断面図。FIG. 3 is a partial process cross-sectional view illustrating flip chip connection according to the first embodiment which is an embodiment of the present invention. 本発明の一実施例である実施例１のフリップチップ接続を説明する部分工程断面図。FIG. 3 is a partial process cross-sectional view illustrating flip chip connection according to the first embodiment which is an embodiment of the present invention. 本発明の一実施例である実施例１の半導体チップと基板間に液状樹脂を流し込む部分工程断面図。1 is a partial process cross-sectional view in which a liquid resin is poured between a semiconductor chip and a substrate of Example 1 which is an embodiment of the present invention. 本発明の一実施例である実施例１の半導体チップと基板間に液状樹脂を流し込む部分工程断面図。1 is a partial process cross-sectional view in which a liquid resin is poured between a semiconductor chip and a substrate of Example 1 which is an embodiment of the present invention. 本発明の一実施例である実施例１のステージに基板を搭載してからアンダーフィル樹脂層を形成するまでの工程斜視図。The process perspective view after mounting a board | substrate on the stage of Example 1 which is one Example of this invention until it forms an underfill resin layer. 図６の工程を処理する半導体製造装置の概略斜視図。The schematic perspective view of the semiconductor manufacturing apparatus which processes the process of FIG. 本発明の一実施例である半導体装置の製造工程を説明するフロー図。The flowchart explaining the manufacturing process of the semiconductor device which is one Example of this invention. 本発明の一実施例である実施例１の半導体装置の断面図。Sectional drawing of the semiconductor device of Example 1 which is one Example of this invention. 本発明の一実施例である実施例２の基板の平面図及びステージの上面に設けた基板吸着面を示す平面図。The top view which shows the board | substrate adsorption | suction surface provided in the top view of the board | substrate of Example 2 which is one Example of this invention, and the upper surface of the stage.

符号の説明Explanation of symbols

１、２３、２５・・・ステージ ２、２６・・・吸着孔
３、２４・・・吸着溝 ４・・・真空 ５・・・半導体チップ
６・・・バンプ電極 ７・・・接続用の金属
８・・・配線又は基板インナーリード ９、２１・・・基板
１０・・・フリップチップボンディングツール
１１・・・液状封止樹脂塗布用ノズル １２・・・液状封止樹脂
１３・・・パイプ １４、２２・・・チップ搭載エリア
１５・・・アンダーフィル樹脂層 １６・・・配線基板
１７・・・内部配線 １８・・・外部接続端子
１９・・・ボンディングワイヤ ２０・・・樹脂封止体

1, 23, 25 ... Stage 2, 26 ... Suction hole 3, 24 ... Suction groove 4 ... Vacuum 5 ... Semiconductor chip 6 ... Bump electrode 7 ... Metal for connection 8 ... Wiring or substrate inner lead 9, 21 ... Substrate 10 ... Flip chip bonding tool 11 ... Nozzle for applying liquid sealing resin 12 ... Liquid sealing resin 13 ... Pipe 14, DESCRIPTION OF SYMBOLS 22 ... Chip mounting area 15 ... Underfill resin layer 16 ... Wiring board 17 ... Internal wiring 18 ... External connection terminal 19 ... Bonding wire 20 ... Resin sealing body

Claims (5)

チップ搭載エリアを有する配線基板の複数個から構成された基板を上面が真空吸着面となるステージ上面に吸着させる工程と、
前記ステージにより保持された基板の前記チップ搭載エリアに半導体チップを搭載して前記基板に前記半導体チップをフリップチップ接続する工程と、
前記半導体チップをフリップチップ接続する工程の後に、前記基板を真空吸着により保持した状態でステージ上で前記基板と前記半導体チップ間に液状樹脂を流し込む工程と、
前記基板を真空吸着により保持した状態でステージ上で前記流し込んだ液状樹脂を加熱硬化させてアンダーフィル樹脂層を形成する工程とを備えたことを特徴とする半導体装置の製造方法。 Adsorbing a substrate composed of a plurality of wiring substrates having a chip mounting area on a stage upper surface whose upper surface is a vacuum adsorption surface;
Mounting a semiconductor chip on the chip mounting area of the substrate held by the stage and flip-chip connecting the semiconductor chip to the substrate;
After the step of flip-chip connecting the semiconductor chip, a step of pouring a liquid resin between the substrate and the semiconductor chip on the stage with the substrate held by vacuum suction;
And a step of forming an underfill resin layer by heat-curing the poured liquid resin on a stage while the substrate is held by vacuum suction. 前記ステージ上面には少なくとも１つの点状もしくは線状の吸着部が設けられていることを特徴とする請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein at least one point-like or line-like adsorption portion is provided on the upper surface of the stage. 前記基板の前記吸着部が設けられている領域上には前記チップ搭載エリアを載置しないようにすることを特徴とする請求項１又は請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the chip mounting area is not placed on an area of the substrate where the suction portion is provided. 4. 前記アンダーフィル樹脂層を形成する工程の後工程において、前記半導体チップ上に少なくとも１層の半導体チップを積層し、この少なくとも１層の半導体チップは、前記配線基板の配線とボンディングワイヤにより接続されていることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置の製造方法。 In a subsequent process of forming the underfill resin layer, at least one semiconductor chip is stacked on the semiconductor chip, and the at least one semiconductor chip is connected to the wiring of the wiring board by bonding wires. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. 少なくとも２層積層された複数の半導体チップと、
外部接続端子を備え、前記積層された複数の半導体チップを搭載する配線基板とを備え、
前記配線基板に直接接続される第１層の半導体チップは、前記配線基板にフリップチップ接続され、且つ前記第１層の半導体チップと前記配線基板との間隙にアンダーフィル樹脂層が形成され、前記第１層の半導体チップに積層される第２層以上の半導体チップは、ボンディングワイヤにより前記配線基板に電気的に接続され、前記第１層の半導体チップの膜厚は１００μｍ以下であり、前記配線基板は２００μｍを越えない膜厚を有することを特徴とする半導体装置。


A plurality of semiconductor chips laminated at least two layers;
An external connection terminal, and a wiring board on which the plurality of stacked semiconductor chips are mounted,
The first layer semiconductor chip directly connected to the wiring board is flip-chip connected to the wiring board, and an underfill resin layer is formed in the gap between the first layer semiconductor chip and the wiring board, The semiconductor chips of the second layer or higher stacked on the semiconductor chip of the first layer are electrically connected to the wiring board by bonding wires, and the film thickness of the semiconductor chip of the first layer is 100 μm or less, and the wiring A semiconductor device, wherein the substrate has a thickness not exceeding 200 μm.


JP2005325952A 2005-11-10 2005-11-10 Semiconductor device and method for manufacturing same Pending JP2007134489A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130141948A (en) * 2012-06-18 2013-12-27 삼성전자주식회사 Method for fabricating a semiconductor device and underfill equipment for the method
JP2015053347A (en) * 2013-09-05 2015-03-19 株式会社村田製作所 Method for mounting component on aggregate substrate and aggregate substrate
CN109872958A (en) * 2017-12-04 2019-06-11 美光科技公司 Semiconductor tools and the method for being used to form semiconductor device assemblies

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130141948A (en) * 2012-06-18 2013-12-27 삼성전자주식회사 Method for fabricating a semiconductor device and underfill equipment for the method
KR102008316B1 (en) * 2012-06-18 2019-08-08 삼성전자주식회사 method for fabricating a semiconductor device and underfill equipment for the method
JP2015053347A (en) * 2013-09-05 2015-03-19 株式会社村田製作所 Method for mounting component on aggregate substrate and aggregate substrate
CN109872958A (en) * 2017-12-04 2019-06-11 美光科技公司 Semiconductor tools and the method for being used to form semiconductor device assemblies

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