TWI626723B - Package structure - Google Patents
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- TWI626723B TWI626723B TW106107143A TW106107143A TWI626723B TW I626723 B TWI626723 B TW I626723B TW 106107143 A TW106107143 A TW 106107143A TW 106107143 A TW106107143 A TW 106107143A TW I626723 B TWI626723 B TW I626723B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一種封裝結構，其包括封裝基板、電子元件、多個導電膠及封裝膠體。封裝基板包括載板、多個接墊及絕緣層。接墊與絕緣層配置於載板上，絕緣層具有多個開口以暴露出接墊，且各接墊包括連接部及突起部。電子元件設置於封裝基板上。各接墊的突起部由連接部往電子元件的方向延伸。導電膠設置於絕緣層的開口內。電子元件藉導電膠與突起部電性連接。封裝膠體包覆電子元件、導電膠與封裝基板。封裝膠體填入電子元件與封裝基板之間。電子元件與封裝基板之間具有間隙，介於30微米至110微米之間。封裝膠體填入間隙。A packaging structure includes a packaging substrate, electronic components, a plurality of conductive adhesives, and a packaging gel. The package substrate includes a carrier board, a plurality of pads, and an insulating layer. The pads and the insulation layer are disposed on the carrier board, the insulation layer has a plurality of openings to expose the pads, and each pad includes a connecting portion and a protruding portion. The electronic component is disposed on the package substrate. The protruding portion of each pad extends from the connecting portion toward the electronic component. The conductive adhesive is disposed in the opening of the insulating layer. The electronic component is electrically connected to the protruding portion through a conductive adhesive. The packaging colloid covers the electronic components, the conductive adhesive and the packaging substrate. The packaging gel is filled between the electronic component and the packaging substrate. There is a gap between the electronic component and the package substrate, between 30 microns and 110 microns. The encapsulant fills the gap.
Description
本發明是有關於一種半導體元件，且特別是有關於一種封裝結構。The present invention relates to a semiconductor device, and more particularly, to a packaging structure.
系統級封裝（System-in-Package, SiP）是指將一個系統或子系統的全部或大部分電子元件接合於線路載板上。此外，在將電子元件組裝於線路載板之後，還須清洗殘留於線路載板上的助焊劑（flux），以避免影響封裝結構的可靠度。然而，由於電子元件與線路載板之間的間隙甚小，在進行迴焊（reflow）時，焊料可能會流入電子元件與線路載板之間的間隙並相互連接，造成接墊之間發生短路，而導致橋接（solder bridge）問題。另外，在進行迴焊製程之後，也無法有效地清除殘留於所述間隙中的助焊劑，導致進行信賴度測試時，容易產生分離（delamination）的情形，影響產品的良率。System-in-Package (SiP) refers to bonding all or most of the electronic components of a system or subsystem to a circuit board. In addition, after the electronic components are assembled on the circuit carrier board, the flux remaining on the circuit carrier board must be cleaned to avoid affecting the reliability of the package structure. However, because the gap between the electronic component and the circuit carrier board is very small, during reflow, solder may flow into the gap between the electronic component and the circuit carrier board and be connected to each other, causing a short circuit between the pads. , Which causes a bridge problem (solder bridge). In addition, after the reflow process is performed, the flux remaining in the gap cannot be effectively removed, which leads to delamination when the reliability test is performed, which affects the yield of the product.
本發明的實施例提供一種封裝結構，其可增加封裝基板與電子元件之間的間隙，以利於後續製程並增加產品良率。An embodiment of the present invention provides a packaging structure that can increase a gap between a packaging substrate and an electronic component, so as to facilitate subsequent processes and increase product yield.
本發明的實施例提供的一種封裝結構，其包括封裝基板、電子元件、多個導電膠以及封裝膠體。封裝基板包括載板、多個接墊以及絕緣層。接墊與絕緣層配置於載板上，絕緣層具有多個開口以暴露出接墊，且各個接墊包括連接部以及突起部。電子元件設置於封裝基板上。各個接墊的突起部由連接部往電子元件的方向延伸。導電膠設置於絕緣層的開口內。電子元件藉由導電膠與突起部電性連接。封裝膠體包覆電子元件、導電膠與封裝基板。封裝膠體填入電子元件與封裝基板之間。A packaging structure provided by an embodiment of the present invention includes a packaging substrate, an electronic component, a plurality of conductive adhesives, and a packaging gel. The package substrate includes a carrier board, a plurality of pads, and an insulating layer. The pads and the insulation layer are disposed on the carrier board, the insulation layer has a plurality of openings to expose the pads, and each pad includes a connecting portion and a protruding portion. The electronic component is disposed on the package substrate. The protruding portion of each pad extends from the connecting portion toward the electronic component. The conductive adhesive is disposed in the opening of the insulating layer. The electronic component is electrically connected to the protruding portion through a conductive adhesive. The packaging colloid covers the electronic components, the conductive adhesive and the packaging substrate. The packaging gel is filled between the electronic component and the packaging substrate.
本發明的實施例提供的一種封裝結構，其包括封裝基板、電子元件以及封裝膠體。封裝基板包括載板以及多個接墊。接墊配置於載板上。各個接墊包括連接部以及突起部。電子元件設置於封裝基板上。各個接墊的突起部由連接部往電子元件的方向延伸。電子元件藉由接墊的突起部與封裝基板電性連接。封裝膠體包覆電子元件與封裝基板。電子元件與封裝基板之間具有間隙，介於30微米至110微米之間。封裝膠體填入間隙。A packaging structure provided by an embodiment of the present invention includes a packaging substrate, an electronic component, and a packaging gel. The package substrate includes a carrier board and a plurality of pads. The pads are arranged on the carrier board. Each pad includes a connecting portion and a protruding portion. The electronic component is disposed on the package substrate. The protruding portion of each pad extends from the connecting portion toward the electronic component. The electronic component is electrically connected to the package substrate through the protruding portion of the pad. The packaging colloid covers the electronic component and the packaging substrate. There is a gap between the electronic component and the package substrate, between 30 microns and 110 microns. The encapsulant fills the gap.
基於上述，在本發明的實施例的封裝結構中，接墊的突起部能夠支撐電子元件，以增加電子元件與封裝基板之間的間隙。因此，能夠有效地清除間隙中的助焊劑，以避免影響封裝結構的可靠度，並且能夠避免在進行迴焊製程時，焊料流入間隙而導致橋接問題，進而增加產品的良率。Based on the above, in the package structure of the embodiment of the present invention, the protruding portion of the pad can support the electronic component to increase the gap between the electronic component and the package substrate. Therefore, the flux in the gap can be effectively removed to avoid affecting the reliability of the package structure, and the solder can flow into the gap during the reflow process to cause bridging problems, thereby increasing the yield of the product.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
圖1A至圖1C是依照本發明一實施例的一種封裝結構的製造流程剖面示意圖，圖2是圖1A的封裝結構的俯視示意圖。請參照圖1A至圖2，首先，提供一封裝基板110。封裝基板110包括一載板112、多個接墊114以及一絕緣層116。接墊114以及絕緣層116設置於載板112上。此外，絕緣層116具有多個開口116a，以暴露出接墊114。各個接墊114具有一連接部114a與一突起部114b。封裝基板110具有一第一表面110a與相對於第一表面110a的一第二表面110b。各個接墊114的突起部114b由封裝基板110的第二表面110b往封裝基板110的第一表面110a延伸。在本實施例中，絕緣層116也可以設置於相鄰的兩個接墊114之間的一區域A中。在其他實施例中，絕緣層116也可以不設置於區域A中，以暴露載板112，而關於此類型的封裝基板110的細節會在後述的實施例中描述。1A to 1C are schematic cross-sectional views of a manufacturing process of a packaging structure according to an embodiment of the present invention, and FIG. 2 is a schematic top view of the packaging structure of FIG. 1A. Please refer to FIGS. 1A to 2. First, a package substrate 110 is provided. The package substrate 110 includes a carrier board 112, a plurality of pads 114, and an insulation layer 116. The pads 114 and the insulating layer 116 are disposed on the carrier board 112. In addition, the insulating layer 116 has a plurality of openings 116 a to expose the pads 114. Each pad 114 has a connecting portion 114a and a protruding portion 114b. The package substrate 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. The protruding portion 114 b of each pad 114 extends from the second surface 110 b of the package substrate 110 to the first surface 110 a of the package substrate 110. In this embodiment, the insulating layer 116 may also be disposed in a region A between two adjacent pads 114. In other embodiments, the insulating layer 116 may not be provided in the area A to expose the carrier board 112, and details about this type of packaging substrate 110 will be described in the embodiments described later.
舉例來說，載板112可以是玻璃基板、聚亞醯胺（Polyimide）樹脂或其他類似的聚合物所形成的芯層。然而，本發明不限於此，其他合適的芯層材料也可以作為載板100，只要所述材料能夠承載在其之上所形成的封裝結構，並且能夠承受後續的製程即可。另外，在一實施例中，載板112也可以具有導電通孔，以電性連接設置於載板112第一表面110a的接墊114與設置於第二表面110b的外部端子，而關於此類型的封裝基板110的細節會在後述的實施例中描述。再者，接墊114例如是藉由導電金屬，如鋁、銅、鋁合金或與銅合金而製成，惟本發明不以此為限。For example, the carrier plate 112 may be a core layer formed of a glass substrate, a polyimide resin, or other similar polymers. However, the present invention is not limited to this, and other suitable core layer materials can also be used as the carrier plate 100 as long as the material can bear the packaging structure formed thereon and can withstand subsequent processes. In addition, in an embodiment, the carrier board 112 may also have conductive through holes to electrically connect the pads 114 provided on the first surface 110a of the carrier board 112 and external terminals provided on the second surface 110b. Details of the package substrate 110 will be described in the embodiments described later. Furthermore, the pad 114 is made of, for example, a conductive metal, such as aluminum, copper, an aluminum alloy, or a copper alloy, but the present invention is not limited thereto.
此外，在本實施例中，接墊114的突起部114b例如是多個導電柱，藉由電鍍（electroplating）、蒸鍍（evaporation）或沉積（deposition）等方式製成。以電鍍為例，在進行黃光製程（lithography）後，利用圖案化薄膜定義出突起部114b的預定位置，再經由電鍍製程於所述的預定位置上製作導電柱。突起部114b例如是方塊狀、圓柱狀、細柱狀或其他圖案，其材質例如是單一金屬或是合成金屬，惟本發明並不限於此。各個接墊114的突起部114b可以具有相同的材質、高度與外型。因此，突起部114b在製程中可以同時形成，以節省製造成本。可以理解的是，各個接墊114的突起部114b也可以具有不同的材質、高度與外型，視設計需求而定，惟本發明並不限於此。另外，突起部114b可以由其他可能的形式呈現或為其他可能的形狀，而關於其他類型的突起部114b的細節會在後述的實施例中描述。In addition, in this embodiment, the protruding portion 114b of the pad 114 is, for example, a plurality of conductive pillars, and is made by electroplating, evaporation, or deposition. Taking electroplating as an example, after performing a yellow light process (lithography), a predetermined position of the protruding portion 114b is defined by using a patterned thin film, and then a conductive pillar is formed at the predetermined position through the electroplating process. The protruding portion 114b is, for example, a block shape, a column shape, a thin column shape, or other patterns, and the material thereof is, for example, a single metal or a synthetic metal, but the present invention is not limited thereto. The protruding portions 114b of the pads 114 may have the same material, height, and appearance. Therefore, the protruding portions 114b can be formed at the same time in the manufacturing process to save manufacturing costs. It can be understood that the protruding portions 114b of each of the pads 114 may also have different materials, heights, and shapes, depending on design requirements, but the present invention is not limited thereto. In addition, the protruding portions 114b may be presented in other possible forms or have other possible shapes, and details about other types of protruding portions 114b will be described in embodiments described later.
在本實施例中，絕緣層116例如包括環氧樹脂（epoxy resin）或感光樹脂，利用塗佈或網版印刷等方式形成於載板112上，以絕緣保護載板112並防止內部導線外露而造成短路。然而，本發明並不限制絕緣層116的材質與形成的方式。另外，各個接墊114的突起部114b的高度H可以是大於絕緣層116的開口116a的深度D。舉例來說，開口116a可以利用光阻（photoresist）包覆於絕緣層116上，再進行曝光、顯影與蝕刻等方式加以圖案化而形成。然而，本發明並不限於此。In this embodiment, the insulating layer 116 includes, for example, epoxy resin or photosensitive resin, and is formed on the carrier plate 112 by coating or screen printing to protect the carrier plate 112 from insulation and prevent internal wires from being exposed. Cause a short circuit. However, the present invention does not limit the material and the manner of forming the insulating layer 116. In addition, the height H of the protruding portion 114 b of each pad 114 may be greater than the depth D of the opening 116 a of the insulating layer 116. For example, the opening 116 a may be formed by covering the insulating layer 116 with a photoresist, and then patterning the exposed layer 116 a through exposure, development, and etching. However, the present invention is not limited to this.
接著，將多個導電膠130設置於絕緣層116的開口116a內，並將電子元件120設置於封裝基板110上，進行迴焊（reflow）製程。電子元件120藉由導電膠130與封裝基板110電性連接。詳細來說，導電膠130包覆接墊114的突起部114b，電子元件120則藉由導電膠130與接墊114的突起部114b電性連接。另外，在本實施例中，導電膠130部分地包覆封裝基板110的絕緣層116與電子元件120的導電端子122。導電膠130例如是焊料（solder paste），經由焊接的方式接合並電性連接於封裝基板110與電子元件120之間，進而防止電子元件120在後續製程中產生位移。然而，導電膠也可以是其他導電黏著材料，其形成方式與材質並不限於此。Next, a plurality of conductive adhesives 130 are disposed in the opening 116 a of the insulating layer 116, and the electronic component 120 is disposed on the package substrate 110, and a reflow process is performed. The electronic component 120 is electrically connected to the packaging substrate 110 through the conductive adhesive 130. In detail, the conductive adhesive 130 covers the protruding portion 114b of the pad 114, and the electronic component 120 is electrically connected to the protruding portion 114b of the pad 114 through the conductive adhesive 130. In addition, in this embodiment, the conductive paste 130 partially covers the insulating layer 116 of the package substrate 110 and the conductive terminal 122 of the electronic component 120. The conductive paste 130 is, for example, a solder paste, and is bonded and electrically connected between the packaging substrate 110 and the electronic component 120 through soldering, thereby preventing the electronic component 120 from being displaced in a subsequent process. However, the conductive adhesive may also be other conductive adhesive materials, and the formation method and material thereof are not limited thereto.
此外，根據電性及性能上的需求，電子元件120例如是主動元件、被動元件或其組合者。舉例來說，主動元件可以是積體電路、光電元件或是微機電元件等。被動元件例如為電容器、電阻器或是電感器等。然而，本發明並不限於此。另外，電子元件120與封裝基板110之間具有一間隙C。In addition, according to electrical and performance requirements, the electronic component 120 is, for example, an active component, a passive component, or a combination thereof. For example, the active device may be an integrated circuit, a photovoltaic device, or a micro-electro-mechanical device. The passive element is, for example, a capacitor, a resistor, or an inductor. However, the present invention is not limited to this. In addition, there is a gap C between the electronic component 120 and the package substrate 110.
進一步來說，電子元件120具有多個導電端子122。導電端子122分別對應於接墊114的其中之一。接墊114的突起部114b的數量為至少三個，以支撐導電端子122。舉例來說，對應於導電端子122的接墊114中，一者可以是具有單一導電柱，另一者可以是具有一對導電柱。也就是說，對應於導電端子122的接墊114一共具有三個導電柱，以最少的導電柱數量來支撐導電端子122，且這些導電柱不共線而是排列為三角形，以達到三點平衡的條件進而穩固地支撐電子元件120，並使電子元件120能夠保持平衡不致傾倒。接墊114的突起部114b面對導電端子122的表面是位於同一平面上，由連接部114a往電子元件120的導電端子122方向延伸，以支撐導電端子122。可以理解的是，圖式繪示為一對導電端子及一對接墊，且各個接墊具有三個導電柱，但本發明並不以此為限。舉例來說，這些導電柱的尺寸至少是30微米。可以理解的是，導電柱的尺寸越大，越能穩固地支撐電子元件120，也能夠減少導電柱的數量。然而，本發明並不限制導電柱的數量或是排列方式，只要突起部114b能夠支撐電子元件120，以使電子元件120與封裝基板110之間具有間隙C即可。Further, the electronic component 120 has a plurality of conductive terminals 122. The conductive terminals 122 respectively correspond to one of the pads 114. The number of the protruding portions 114 b of the pads 114 is at least three to support the conductive terminals 122. For example, one of the pads 114 corresponding to the conductive terminals 122 may have a single conductive post, and the other may have a pair of conductive posts. That is, the pads 114 corresponding to the conductive terminals 122 have a total of three conductive pillars, and the conductive terminals 122 are supported with a minimum number of conductive pillars. These conductive pillars are not aligned but arranged in a triangle to achieve a three-point balance The conditions further support the electronic component 120 firmly, and enable the electronic component 120 to maintain balance and prevent it from falling over. The surface of the protruding portion 114 b of the pad 114 facing the conductive terminal 122 is located on the same plane, and the connecting portion 114 a extends in the direction of the conductive terminal 122 of the electronic component 120 to support the conductive terminal 122. It can be understood that the drawings are shown as a pair of conductive terminals and a pair of pads, and each pad has three conductive posts, but the invention is not limited thereto. For example, these conductive pillars are at least 30 microns in size. It can be understood that the larger the size of the conductive pillars, the more stable the electronic component 120 can be supported, and the number of conductive pillars can also be reduced. However, the present invention does not limit the number or arrangement of the conductive pillars, as long as the protruding portion 114b can support the electronic component 120 so that there is a gap C between the electronic component 120 and the package substrate 110.
最後，將封裝膠體140包覆電子元件120、導電膠130以及封裝基板110，並將封裝膠體140填入電子元件120與封裝基板110之間，以形成封裝結構100。也就是說，將封裝膠體140填入間隙C中形成絕緣屏障，以避免接墊114之間產生橋接（solder bridge）問題而影響產品的良率。此外，填入間隙C中的封裝膠體140的厚度介於30微米至110微米之間。舉例來說，封裝膠體140可以是非導電性的材料，如環氧樹脂、環氧模封化合物（epoxy molding compound, EMC）或其他聚合物的模封材料，利用模壓（molding）、層壓（lamination）或其他適當的方式形成於電子元件120及封裝基板110上，以保護電子元件120及封裝基板110。然而，本發明並不限制封裝膠體140的材質與形成方式。Finally, the packaging gel 140 covers the electronic component 120, the conductive adhesive 130, and the packaging substrate 110, and the packaging gel 140 is filled between the electronic component 120 and the packaging substrate 110 to form a packaging structure 100. In other words, the encapsulation gel 140 is filled into the gap C to form an insulation barrier, so as to avoid the problem of a solder bridge between the pads 114 and affect the yield of the product. In addition, the thickness of the encapsulant 140 filled in the gap C is between 30 μm and 110 μm. For example, the encapsulant 140 may be a non-conductive material, such as epoxy resin, epoxy molding compound (EMC), or other polymer molding materials. Molding and lamination are used. ) Or other suitable methods are formed on the electronic component 120 and the package substrate 110 to protect the electronic component 120 and the package substrate 110. However, the present invention does not limit the material and forming method of the encapsulant 140.
圖3A至圖3C是依照本發明另一實施例的一種封裝結構的製造流程剖面示意圖、圖4是圖3A的封裝結構的俯視示意圖。請參照圖3A至圖4，本實施例的封裝結構200的製造流程類似於封裝結構100的製造流程，其中相同或相似的元件採用相同或相似的標號，在此不再贅述。封裝結構200與封裝結構100之間的差異例如在於，接墊214的突起部214b可以是圖釘狀。舉例來說，藉由打線（wire bonding）的方式在連接部214a上形成打線凸塊（stud bump）或是焊球凸塊作為突起部214b。然而，本發明的實施例並不限制突起部214b的製作方式、材質與外型，只要突起部214b能夠在電子元件220與封裝基板210之間發揮良好的間隔維持作用即可。再者，在封裝結構200中，突起部214b的高度H小於或等於絕緣層216的開口216a的深度D。此外，電子元件220可以是經由導電膠230而與接墊214的突起部214b連接。舉例來說，在進行迴焊製程時，可視所需導電膠的高度而調整導電膠的熔融程度，並藉此調整電子元件220與封裝基板210之間的間隙C，以使電子元件220設置於封裝基板210上。3A to 3C are schematic cross-sectional views of a manufacturing process of a packaging structure according to another embodiment of the present invention, and FIG. 4 is a schematic top view of the packaging structure of FIG. 3A. Please refer to FIGS. 3A to 4. The manufacturing process of the packaging structure 200 in this embodiment is similar to the manufacturing process of the packaging structure 100. The same or similar components are denoted by the same or similar reference numerals, and details are not described herein. The difference between the packaging structure 200 and the packaging structure 100 is, for example, that the protruding portion 214 b of the pad 214 may be in a pin shape. For example, a stud bump or a solder ball bump is formed on the connection portion 214a as a protrusion 214b by wire bonding. However, the embodiment of the present invention does not limit the manufacturing method, material, and shape of the protruding portion 214b, as long as the protruding portion 214b can play a good space maintaining function between the electronic component 220 and the package substrate 210. Furthermore, in the package structure 200, the height H of the protruding portion 214b is less than or equal to the depth D of the opening 216a of the insulating layer 216. In addition, the electronic component 220 may be connected to the protruding portion 214 b of the pad 214 via the conductive adhesive 230. For example, during the reflow process, the melting degree of the conductive adhesive can be adjusted according to the height of the required conductive adhesive, and the gap C between the electronic component 220 and the packaging substrate 210 can be adjusted by this, so that the electronic component 220 is disposed at On the package substrate 210.
此外，在封裝結構200中，在對應於電子元件220的接墊214之間的一區域A，暴露載板212。也就是說，在區域A中不設置絕緣層216，以增加在區域A中，電子元件220與封裝基板210之間的間隙C。另外，封裝結構200還可以在封裝基板210的第二表面210b設置絕緣層216以及導電圖案217。在封裝基板210的第一表面210a的接墊214以及第二表面210b的導電圖案217彼此相互對應，並且利用載板212的導電通孔218電性連接位於第一表面210a的接墊214與第二表面210b的導電圖案217。再者，封裝基板210的第二表面210b還設置多個導電接點219。導電接點219例如是導電球體（如焊球、銅球或鎳球等），利用植球（ball placement）製程與迴焊製程接合於導電圖案217，惟本發明並不限於此。藉由在封裝基板210的第二表面210b上形成導電圖案217以及導電接點219，以增加封裝結構產品的變化性。In addition, in the package structure 200, a carrier board 212 is exposed in an area A between the pads 214 corresponding to the electronic components 220. That is, the insulating layer 216 is not provided in the region A to increase the gap C between the electronic component 220 and the package substrate 210 in the region A. In addition, the packaging structure 200 may further include an insulating layer 216 and a conductive pattern 217 on the second surface 210 b of the packaging substrate 210. The pads 214 on the first surface 210a and the conductive patterns 217 on the second surface 210b of the package substrate 210 correspond to each other, and the conductive vias 218 of the carrier board 212 are used to electrically connect the pads 214 and the first The conductive pattern 217 on the two surfaces 210b. Furthermore, the second surface 210b of the package substrate 210 is further provided with a plurality of conductive contacts 219. The conductive contact 219 is, for example, a conductive ball (such as a solder ball, a copper ball, or a nickel ball), and is bonded to the conductive pattern 217 by using a ball placement process and a reflow process, but the present invention is not limited thereto. By forming a conductive pattern 217 and a conductive contact 219 on the second surface 210b of the package substrate 210, the variability of the package structure product is increased.
綜上所述，本發明藉由接墊的突起部支撐電子元件，以增加封裝基板與電子元件之間的間隙。藉此，能夠有效地清除間隙中的助焊劑，以避免影響封裝結構的可靠度，並且能夠避免橋接問題。另外，增加封裝基板與電子元件之間的間隙能夠容易地將封裝膠體填入間隙中，以減少電子元件與封裝基板之間因熱膨脹差異所產生的熱應力而導致分離（delamination）的問題。此外，藉由在對應於電子元件的接墊之間的區域中，不設置絕緣層，進一步增加填入封裝基板與電子元件之間的封裝膠體的最大厚度，以避免接墊之間產生不當的電性橋接，進而增加產品的良率。In summary, the present invention supports the electronic component by the protruding portion of the pad to increase the gap between the package substrate and the electronic component. Thereby, the flux in the gap can be effectively removed to avoid affecting the reliability of the package structure, and the bridging problem can be avoided. In addition, increasing the gap between the packaging substrate and the electronic component can easily fill the packaging gel into the gap, so as to reduce the problem of delamination caused by the thermal stress caused by the difference in thermal expansion between the electronic component and the packaging substrate. In addition, by not providing an insulating layer in the area between the pads corresponding to the electronic components, the maximum thickness of the packaging gel filled between the packaging substrate and the electronic components is further increased, so as to avoid erroneous Electrical bridging, which increases the yield of the product.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
100、200‧‧‧封裝結構
110、210‧‧‧封裝基板
110a、210a‧‧‧第一表面
110b、210b‧‧‧第二表面
112、212‧‧‧載板
114、214‧‧‧接墊
114a、214a‧‧‧連接部
114b、214b‧‧‧突起部
116、216‧‧‧絕緣層100, 200‧‧‧ package structure
110, 210‧‧‧ package substrate
110a, 210a‧‧‧First surface
110b, 210b‧‧‧Second surface
112, 212‧‧‧ Carrier
114, 214‧‧‧ pads
114a, 214a‧‧‧ Connection
114b, 214b‧‧‧‧protrusions
116, 216‧‧‧ Insulation
116a、216a‧‧‧開口 116a, 216a‧‧‧ opening
120、220‧‧‧電子元件 120, 220‧‧‧Electronic components
122、222‧‧‧導電端子 122, 222‧‧‧ conductive terminals
130、230‧‧‧導電膠 130, 230‧‧‧ conductive adhesive
140、240‧‧‧封裝膠體 140, 240‧‧‧ encapsulated colloid
217‧‧‧導電圖案 217‧‧‧ conductive pattern
218‧‧‧導電通孔 218‧‧‧ conductive via
219‧‧‧導電接點 219‧‧‧Conductive contact
A‧‧‧區域 A‧‧‧Area
C‧‧‧間隙 C‧‧‧ Clearance
D‧‧‧深度 D‧‧‧ Depth
H‧‧‧高度 H‧‧‧ height
圖1A至圖1C是依照本發明一實施例的一種封裝結構的製造流程剖面示意圖。 圖2是圖1A的封裝結構的俯視示意圖。 圖3A至圖3C是依照本發明另一實施例的一種封裝結構的製造流程剖面示意圖。 圖4是圖3A的封裝結構的俯視示意圖。1A to 1C are schematic cross-sectional views illustrating a manufacturing process of a packaging structure according to an embodiment of the present invention. FIG. 2 is a schematic top view of the package structure of FIG. 1A. 3A to 3C are schematic cross-sectional views illustrating a manufacturing process of a packaging structure according to another embodiment of the present invention. FIG. 4 is a schematic top view of the package structure of FIG. 3A.
Claims (10)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106107143A TWI626723B (en) | 2017-03-06 | 2017-03-06 | Package structure |
| CN201710223076.4A CN108538800B (en) | 2017-03-06 | 2017-04-07 | Packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106107143A TWI626723B (en) | 2017-03-06 | 2017-03-06 | Package structure |
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| TWI626723B true TWI626723B (en) | 2018-06-11 |
| TW201834172A TW201834172A (en) | 2018-09-16 |
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| TW (1) | TWI626723B (en) |
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| DE2450172A1 (en) * | 1974-10-22 | 1976-04-29 | Siemens Ag | Semiconductor device with pressure contacting - has contact design permitting punctiform connection between chip surface and contact |
| JP2000156386A (en) * | 1998-11-20 | 2000-06-06 | Sharp Corp | Connection structure and connection method of semiconductor device and semiconductor device package using the same |
| JP2000223649A (en) * | 1999-01-28 | 2000-08-11 | United Microelectronics Corp | Chip scale ic package for multichip |
| JP2002076587A (en) * | 2000-08-24 | 2002-03-15 | Citizen Watch Co Ltd | Method for manufacturing semiconductor device and its mounting method |
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| US9203005B2 (en) * | 2013-03-06 | 2015-12-01 | Samsung Electronics Co., Ltd. | Light-emitting diode (LED) package having flip-chip bonding structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4533248B2 (en) * | 2005-06-03 | 2010-09-01 | 新光電気工業株式会社 | Electronic equipment |
| CN102931109B (en) * | 2012-11-08 | 2015-06-03 | 南通富士通微电子股份有限公司 | Method for forming semiconductor devices |
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2017
- 2017-03-06 TW TW106107143A patent/TWI626723B/en active
- 2017-04-07 CN CN201710223076.4A patent/CN108538800B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2450172A1 (en) * | 1974-10-22 | 1976-04-29 | Siemens Ag | Semiconductor device with pressure contacting - has contact design permitting punctiform connection between chip surface and contact |
| JP2000156386A (en) * | 1998-11-20 | 2000-06-06 | Sharp Corp | Connection structure and connection method of semiconductor device and semiconductor device package using the same |
| JP2000223649A (en) * | 1999-01-28 | 2000-08-11 | United Microelectronics Corp | Chip scale ic package for multichip |
| JP2002076587A (en) * | 2000-08-24 | 2002-03-15 | Citizen Watch Co Ltd | Method for manufacturing semiconductor device and its mounting method |
| JP2002134541A (en) * | 2000-10-23 | 2002-05-10 | Citizen Watch Co Ltd | Semiconductor device and its fabrication method and packaging structure of the device |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108538800B (en) | 2020-03-31 |
| TW201834172A (en) | 2018-09-16 |
| CN108538800A (en) | 2018-09-14 |
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