WO2017043480A1

WO2017043480A1 - Semiconductor package

Info

Publication number: WO2017043480A1
Application number: PCT/JP2016/076166
Authority: WO
Inventors: 楠本　馨一
Original assignee: 株式会社ソシオネクスト
Priority date: 2015-09-09
Filing date: 2016-09-06
Publication date: 2017-03-16

Abstract

This semiconductor package is provided with: a semiconductor chip which is held on a package substrate and has an element formation surface on the reverse side of the package substrate-side surface; and a film substrate which is held on the element formation surface of the semiconductor chip and the upper surface of the package substrate and covers the semiconductor chip. The element formation surface of the semiconductor chip is provided with a chip connection part; the upper surface of the package substrate is provided with a substrate connection part; and the film substrate comprises a wiring line that is provided on a surface facing the semiconductor chip. The chip connection part of the semiconductor chip is electrically connected to the wiring line of the film substrate; the film substrate and the wiring line extend to the outside of the semiconductor chip; and the wiring line is electrically connected to the substrate connection part.

Description

Semiconductor package

The present invention relates to a semiconductor package.

For example, Patent Document 1 discloses a semiconductor package that can relieve external stress and can be mounted on a mounting board (motherboard) having a curved mounting surface.

As shown in FIG. 8 of Patent Document 1, an interposer 30 made of a flexible resin film provided with wiring and bent with a support block 20 sandwiched is formed on an element forming surface 10b which is the lower surface of the semiconductor chip 10. Electrically connected. The surface of the interposer 30 opposite to the semiconductor chip 10 is electrically connected to the mounting substrate 50 with a plurality of solder balls 40 interposed therebetween.

As described above, the element formation surface 10b of the semiconductor chip 10 faces the substrate 50 and is flip-chip mounted. The arrangement area of the plurality of solder balls 40 in the interposer 30 is substantially equal to the area where the element formation surface 10b of the semiconductor chip 10 faces. The interval between the bent portions of the interposer 30, that is, the thickness of the support block 20 is smaller than the thickness of the semiconductor chip 10. Further, the support block 20 is disposed along the inside of a portion where the interposer 30 is bent, and this portion is limited to the edge portions of the two opposing sides of the semiconductor chip 10.

International Publication No. 2007/058134 (Figure 8)

However, in the conventional flexible semiconductor package, first, as the number of signal lines drawn from the semiconductor chip increases, the arrangement pitch of the solder balls decreases. For this reason, since the wiring pitch of a board | substrate becomes small similarly, there exists a problem that the structure and manufacture of a board | substrate become complicated.

Second, when the semiconductor package is mounted on the substrate, the semiconductor chip on the interposer made of a flexible resin film is pressed, and the semiconductor chip is broken by the pressure at the time of pressing.

Third, since the element formation surface of the semiconductor chip is the lower surface, there is a problem that it is difficult to align the semiconductor chip in the process of connecting to the interposer.

Fourth, the wiring formed on the interposer made of a bent film is easy to cut. Furthermore, the flexible resin film which comprises an interposer also has the problem that it is difficult to maintain a bending shape by a restoring force depending on the composition. In addition, the height of the upper surface of the semiconductor chip becomes higher than the surface of the mounting substrate due to the interposer formed of the bent film with the support block interposed.

In view of this point, the present invention does not complicate the structure of the substrate even when the number of signal lines from the semiconductor chip increases, and the semiconductor chip does not break during manufacturing, and the alignment is easy. An object of the present invention is to obtain a semiconductor package in which the wiring in the film substrate) does not break, the bent shape of the interposer can be maintained, and the height from the mounting substrate is suppressed.

It should be noted that at least one of the above-described plural objectives may be achieved.

In order to solve the above-mentioned problems, the present invention covers a semiconductor substrate and a package substrate on a main surface of a package substrate or lead frame on which a semiconductor chip with an element formation surface facing up is mounted by a film substrate having wiring. And it is set as the structure electrically connected mutually.

Specifically, according to a first aspect of the present invention, there is provided a package substrate, a first semiconductor chip held on a main surface of the package substrate and having an element formation surface on the opposite side to the package substrate, and a first semiconductor A film substrate that covers the chip and is held on the element forming surface of the first semiconductor chip and the upper surface of the package substrate is provided. A first connection portion is provided on the element forming surface of the first semiconductor chip, and a second connection portion is provided on the upper surface of the package substrate. The film substrate has wiring provided on the side facing the first semiconductor chip, and the first connection portion of the first semiconductor chip is electrically connected to the wiring of the film substrate. The film substrate and the wiring are extended to the outside of the first semiconductor chip, and the wiring is electrically connected to the second connection portion of the package substrate.

According to a second aspect of the present invention, there is provided a lead frame, a first semiconductor chip that is held on a main surface of the lead frame and has an element forming surface on the opposite side to the lead frame, and covers the first semiconductor chip and the first semiconductor chip. And a film substrate held on the element formation surface of the first semiconductor chip and the upper surface of the lead frame. A first connection portion is provided on the element forming surface of the first semiconductor chip, and a second connection portion is provided on the upper surface of the lead frame. The film substrate has wiring provided on the side facing the first semiconductor chip, and the first connection portion of the first semiconductor chip is electrically connected to the wiring of the film substrate. The film substrate and the wiring are extended to the outside of the first semiconductor chip, and the wiring is electrically connected to the second connection portion of the lead frame.

According to the semiconductor package of the present invention, even if the number of signal lines from the semiconductor chip increases, the configuration of the substrate does not become complicated, the semiconductor chip does not break at the time of manufacture, and alignment is easy. In addition, it is possible to obtain a semiconductor package in which the wiring in the interposer (film substrate) does not break, the bent shape of the interposer can be maintained, and the height from the mounting substrate is suppressed.

FIG. 1 is a plan view showing a semiconductor package according to the first embodiment of the present disclosure. FIG. 2 is a sectional view taken along line II-II in FIG. FIG. 3 is a bottom view and a partially enlarged view showing the semiconductor package according to the first embodiment of the present disclosure. FIG. 4 is a plan view showing the semiconductor package manufacturing method according to the first embodiment, and shows a chip connection region and a partially enlarged view of the semiconductor chip in a wafer state. FIG. 5 is a cross-sectional view taken along line VV of the partially enlarged view of FIG. FIG. 6 is a plan view showing a film substrate and a partial enlarged view thereof, which is a method for manufacturing a semiconductor package according to the first embodiment. FIG. 7 is a partial cross-sectional view taken along line VII-VII in FIG. FIG. 8 is a plan view showing a package substrate in a board state and a partially enlarged view thereof, which is a method for manufacturing a semiconductor package according to the first embodiment. FIG. 9 is an enlarged plan view showing a substrate connecting portion in the package substrate of FIG. FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing the method of manufacturing the semiconductor package according to the first embodiment. FIG. 11 is a partial cross-sectional view showing a connection portion between a film substrate and a semiconductor chip, which is a method for manufacturing a semiconductor package according to the first embodiment. FIG. 12 is a partial cross-sectional view showing the connection portion between the film substrate and the package substrate in the semiconductor package manufacturing method according to the first embodiment. FIG. 13 is a plan view showing a one-step package substrate in a semiconductor package according to a third modification of the manufacturing method of the first embodiment. FIG. 14A to FIG. 14C are cross-sectional views in order of steps showing the main part of the semiconductor package manufacturing method according to the third modification of the manufacturing method of the first embodiment. FIG. 15A and FIG. 15B are cross-sectional views in order of steps showing the main part of the semiconductor package manufacturing method according to the fourth modification of the manufacturing method of the first embodiment. FIG. 16A to FIG. 16C are cross-sectional views in order of steps showing the main part of the semiconductor package manufacturing method according to the fifth modification of the manufacturing method of the first embodiment. FIG. 17 is a plan view showing a first modification of the film substrate constituting the semiconductor package according to the first embodiment. FIG. 18 is a plan view showing a second modification of the film substrate constituting the semiconductor package according to the first embodiment. FIG. 19 is a plan view showing a third modification of the film substrate constituting the semiconductor package according to the first embodiment. FIG. 20 is a plan view showing a fourth modification of the film substrate constituting the semiconductor package according to the first embodiment. FIG. 21 is a cross-sectional view illustrating a semiconductor package according to the second embodiment of the present disclosure. FIG. 22 is a plan view showing a film substrate constituting a semiconductor package according to the second embodiment, a first semiconductor chip and a second semiconductor chip, and an enlarged view of an inter-chip connection region of each semiconductor chip. 23 is a partial cross-sectional view taken along line XXIII-XXIII in the enlarged view of FIG. FIG. 24A to FIG. 24C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor package according to the second embodiment. FIG. 25 is a plan view showing a semiconductor package according to the third embodiment of the present disclosure. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. FIG. 27 is a plan view showing a lead frame in a board (aggregate) state and a partially enlarged view thereof, which is a semiconductor package manufacturing method according to the third embodiment. FIG. 28A to FIG. 28C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor package according to the third embodiment. FIG. 29A and FIG. 29B are cross-sectional views in order of steps showing the main part of the semiconductor package manufacturing method according to the third embodiment. FIG. 30 is a cross-sectional view showing a semiconductor package according to the fourth embodiment of the present disclosure. FIG. 31A to FIG. 31C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor package according to the fourth embodiment.

Embodiments of the present disclosure will be described based on the drawings. The following description of preferred embodiments is merely exemplary in nature and is not intended to limit the present disclosure, its application, or its application.

(First embodiment)
A semiconductor package according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 3. FIG. 1 shows a planar configuration of the semiconductor package according to the first embodiment, FIG. 2 shows a cross-sectional configuration taken along line II-II in FIG. 1, and FIG. 3 shows a bottom configuration of the semiconductor package.

As shown in FIGS. 1 and 2, a semiconductor package 90 according to the present embodiment includes a package substrate 100 configured as a wiring substrate having a plurality of wiring layers therein, and a silver plate on the main surface of the package substrate 100. Alternatively, the semiconductor chip 200 is fixed or bonded by an adhesive such as resin and has an element formation surface 200a on the opposite side of the package substrate 100, and covers the semiconductor chip 200 and straddles the element formation surface 200a and the upper surface of the package substrate 100. The film substrate 300 is fixed or bonded.

The package substrate 100 has, for example, a plurality of laminated insulating resin layers, and a plurality of wirings 110 selectively disposed along the plurality of insulating resin layers. As the insulating resin, a known resin material can be used. For example, an epoxy (glass epoxy) resin or a bismaleidotriazine monomer (BT) resin can be used.

On the element formation surface 200a of the semiconductor chip 200, a chip connection part 200b as a first connection part is provided. On the main surface of the package substrate 100, a plurality of wirings 110 are selectively formed, and a substrate connection portion 100a as a second connection portion is provided. A plurality of wirings 110 are also selectively formed on the bottom surface of the package substrate 100, and the wirings 110 of different layers are connected to each other by vias or vias 111.

As shown in FIG. 2, the film substrate 300 is provided with a wiring layer 320 on the side facing the element formation surface 200 a of the semiconductor chip 200 and the main surface of the package substrate 100. Thereby, the chip connection part 200b of the semiconductor chip 200 can be easily electrically connected to the wiring layer 320 of the film substrate 300. Further, the film substrate 300 and the wiring layer 320 are extended to the outside of the semiconductor chip 200, and the electrical connection between the substrate connecting portion 100a of the package substrate 100 and the wiring layer 320 is facilitated.

In the semiconductor package 90 according to the present embodiment, the wiring layer 320 is provided on the side of the film substrate 300 facing the element formation surface 200a of the semiconductor chip 200, but the wiring layer 320 is provided on both the front and back surfaces of the film substrate 300. It is possible to provide it. However, in this case, it is necessary to provide vias penetrating the front and back surfaces of the film substrate 300 in the chip connection part 200b and the substrate connection part 100a so as to establish conduction with the wiring layer on the upper surface.

As shown in FIG. 3, on the bottom surface of the package substrate 100, for example, a plurality of solder balls 120 are arranged in a matrix. As shown in the partial enlarged view of FIG. 3, each solder ball 120 is electrically connected to a wiring 110 connected to a via 111 provided on the package substrate 100.

Specifically, the film substrate 300 includes a film body 310 having flexibility or rigid flexibility, the above-described wiring layer 320, and an anisotropic conductive film (ACF) 330. Is done. For example, the film main body 310 has a thickness of 15 μm to 120 μm, preferably about 30 μm, and can use thermosetting polyimide, thermoplastic polyimide, polyamide, polyester, or the like as a main composition. Details of the wiring layer 320 will be described later.

The anisotropic conductive film 330 is formed by mixing conductive particles such as metal in an insulating thermoplastic resin material, and is conductive only in a region where pressure is partially applied in the film thickness direction, that is, selectively applied. It is a film that produces Here, although the thickness of the anisotropic conductive film 330 is not specifically limited, For example, it can be 20 micrometers.

As described above, in the semiconductor package 90 according to this embodiment, the film substrate 300 including the wiring layer 320 is provided on the main surface of the package substrate 100 so as to spread outside the periphery of the semiconductor chip 200. As a result, even when the number of signal lines from the semiconductor chip 200 increases, the wiring layer 320 of the film substrate 300 has a minimum wiring pitch in the substrate connection part 100a of the package substrate 100, and the chip connection part of the semiconductor chip 200. It can be made larger than the minimum wiring pitch in the region facing 200b.

For example, when the arrangement area of the solder balls on the back surface of the interposer is substantially the same as the area facing the semiconductor chip as in the above cited reference 1, the minimum arrangement pitch of the solder balls is set on the semiconductor chip. It is difficult to make it larger than the minimum wiring pitch. As a result, although it is necessary to increase the number of wiring layers provided in the interposer, it is not easy to form a multilayer wiring structure in a film-like interposer.

On the other hand, since the semiconductor package 90 according to the present embodiment can increase the minimum wiring pitch in the substrate connection portion 100a, the number of wiring layers of the package substrate 100 can be reduced. As a result, the package substrate 100 can be easily manufactured, and the manufacturing cost of the semiconductor package 90 can be suppressed.

In addition, the wiring layer 320 of the film substrate 300 is provided only on the side facing the element forming surface 200 a of the semiconductor chip 200 and the side facing the main surface of the package substrate 100. That is, the wiring layer 320 of the film substrate 300 is formed only on the surface facing the semiconductor chip 200 and the package substrate 100. Thereby, the formation of the wiring layer 320 is facilitated, that is, the production of the film substrate 300 is facilitated.

In addition, the thickness of the semiconductor chip 200 including the silver pod mounted on the package substrate 100 is the height from the main surface of the package substrate 100. In addition, the semiconductor chip 200 with the element formation surface 200a facing upward is generally smaller in thickness than a semiconductor chip to be flip-chip mounted. As a result, the amount of bending of the film substrate 300 on the package substrate 100 can be made extremely small. Moreover, it does not wrap completely as in Patent Document 1. As a result, damage due to bending of the wiring layer 320 of the film substrate 300, that is, cutting, can be prevented, and the bending process itself of the film substrate 300 is facilitated. Furthermore, in the present embodiment, the semiconductor chip 200 is mounted on the package substrate 100. For this reason, since it is hard to receive the stress by the restoring force of the film substrate 300, or the external stress by flexibility, the damage, ie, a crack, of the semiconductor chip 200 by the film substrate 300 can be prevented. In addition, since the semiconductor package 90 according to the present embodiment can suppress the height from the bottom surface of the package substrate 100 to the top surface of the film substrate 300, it can suppress interference with other components during mounting on the mounting substrate. Can be made compact.

In this embodiment, the semiconductor chip 200 is mounted upward with respect to the main surface of the package substrate 100. Therefore, the alignment of the semiconductor chip 200 on the main surface of the package substrate 100 can be easily and highly accurately performed using the alignment mark on the element formation surface of the semiconductor chip 200.

(Production method)
The semiconductor package manufacturing method according to the first embodiment will be described below with reference to FIGS.

Here, the semiconductor chip 200 is a semiconductor chip including a logic system circuit, for example. However, the semiconductor chip 200 is not limited to a logic chip. As shown in FIG. 4, a plurality of chip connection part regions 210 are provided at the periphery of each semiconductor chip region 200 B in a semiconductor wafer 200 A partitioned into a plurality of semiconductor chip regions 200 B. As shown in FIG. 5 which is a partial enlarged view of the chip connection portion area 210 of FIG. 4 and a cross-sectional view taken along the line VV of the partial enlarged view, A protective (passivation) film 211 made of (Si ₂ N ₃ ) is formed.

Subsequently, regions corresponding to the external electrodes (not shown) of the semiconductor chip region 200B in the protective film 211 are etched by lithography and etching methods to expose a plurality of external electrodes. Thereafter, for example, in a state where only the protective film 211 is masked, electrode pads 212 made of aluminum (Al) are formed by, eg, sputtering, and the mask film is removed. Subsequently, solder bumps 213 are formed on the electrode pads 212 by, for example, a transfer method. Here, instead of the solder bumps 213, copper (Cu) pillars 213 may be used. In the case of the copper pillar, it can be formed with a finer pitch than the solder bump. The Cu pillar 213 is formed by, for example, forming a new resist mask that exposes the central portion of each electrode pad 212 and forming columnar copper plating by electroplating. Subsequently, solder bumps are formed on the upper surface of the copper plating, and the resist mask is removed. Thereafter, a predetermined reflow process is performed to form the Cu pillar 213.

Next, as shown in FIG. 6 and FIG. 7 which is a cross-sectional view taken along the line VII-VII of FIG. 6, a film substrate 300 is produced.

First, a copper foil is bonded on one surface of the film body 310. At this time, after using the roll-shaped film main body 310 and bonding a copper foil, it is good also as a roll shape again. Thereafter, as shown in the partially enlarged plan view of FIG. 6 and FIG. 7, for example, a plurality of wirings (wiring patterns) 320a and a plurality of connection terminals 320b are formed from the bonded copper foil by a known subtractive method. . The plurality of connection terminals 320 b are electrically connected to the chip connection part 200 b of the semiconductor chip 200 or the substrate connection part 100 a of the package substrate 100.

Subsequently, a protective film 325 made of an insulating resin or the like for protecting the wiring 320a is formed on the film main body 310, and is again formed into a roll shape. Then, the anisotropic conductive film 330 is bonded so that the protective film 325 and each connection terminal 320b may be covered. Subsequently, the film main body 310 on which the wiring 320a, the connection terminal 320b, the protective film 325, and the anisotropic conductive film 330 are formed is cut into a plurality of film substrates 300 to be separated into pieces.

As shown in FIG. 6, a chip covering region 300 A that is a region covering the semiconductor chip 200 is provided on the individual film substrate 300. Each wiring 320a and each connection terminal 320b overlaps a chip connection region 300B that overlaps the chip coating region 300A, a substrate narrow pitch connection portion 300C1 that overlaps a narrow pitch portion in the package substrate 100, and a wide pitch portion in the package substrate 100. It is included in any one of the board wide pitch connection portions 300C2.

In the present embodiment, in each wiring 320a and each connection terminal 320b, the wiring pitch of the substrate wide pitch connection portion 300C2 that is separated from the chip connection region 300B, that is, disposed at the peripheral edge of the film substrate 300, is the chip connection region 300B. Is larger than the wiring pitch of the substrate narrow pitch connection portion 300C1 adjacent to the substrate. Thereby, the wiring 320a in the film substrate 300 can be wired so as to expand toward the outside, and the overhanging length of the film substrate 300 can be shortened, so that the manufacturing cost of the film substrate 300 can be suppressed.

Note that the substrate wide pitch connection portion 300C2 is not necessarily provided, and may be configured by only the substrate narrow pitch connection portion 300C1. In this case, the extending distance to the outside of the film substrate 300 is longer than that in the case where the substrate wide pitch connection portion 300C2 is provided.

Next, as shown in FIG. 8 and FIG. 9 which is a partially enlarged plan view of FIG. 8, a package substrate 100 is manufactured.

First, as shown in FIG. 8, a package substrate board 100A including a plurality of package substrate 100 formation regions arranged in a matrix is prepared. As the package substrate board 100A, a substrate board for producing a ball grid array (BGA) or the like can be used. As shown in the partially enlarged plan view, one package substrate 100 is provided with a chip mounting region 100B for mounting the semiconductor chip 200 at the center thereof, and the film substrate 300 is mounted so as to cover the chip mounting region 100B. A film substrate mounting area 100C to be mounted is provided. In addition, a plurality of substrate connection portions 100 a that extend linearly over the main surface of the film substrate mounting region 100 C and the package substrate 100 are provided outside the peripheral portion of the chip mounting region 100 B.

FIG. 9 shows an enlarged view of one of the plurality of substrate connecting portions 100a. As shown in FIG. 9, one substrate connection portion 100 a arranged so as to extend outward from the chip mounting region 100 B of the package substrate 100 includes a wiring 110 connected to each of the plurality of through holes 111, and a wiring 110 of each wiring 110. And a substrate connecting portion 100a connected to the end portion. The substrate connection portion 100 a is composed of an electrode pad 112 made of Al and solder bumps or Cu pillars 113 formed on the electrode pad 112. However, there may be a case where the substrate connecting portion 100a does not include the electrode pad 112. Each solder bump or Cu pillar 113 is electrically connected to each corresponding connection terminal 320b shown in FIG. Therefore, the arrangement pitch of the substrate connection portions 100a is larger in the region connected to the substrate wide pitch connection portion 300C2 than in the region connected to the substrate narrow pitch connection portion 300C1 of the film substrate 300.

Next, a process of assembling the semiconductor package 90 from the semiconductor chip 200, the film substrate 300, and the package substrate 100 manufactured as described above will be described with reference to FIGS. 10 (a) to 10 (d).

First, as shown in FIG. 10A, the semiconductor chip 200 is provided on the element formation surface on the main surface of the package substrate board 100A on which the wiring (not shown) and the substrate connection portion 100a are formed. Secure using the alignment mark. At this time, a silver candy or a resin-based adhesive can be used as the adhesive 201. Here, the main surface of the package substrate board 100A is covered with the protective film 125 except for the substrate connection portion 100a.

Next, as shown in FIG. 10B, the separated film substrate 300 is placed by being aligned with the semiconductor chip 200 and the package substrate board 100A.

Next, as shown in FIG. 10C, the film substrate 300 and the semiconductor chip 200, and the film substrate 300 and the package are used by using the heating / pressurizing head 400 to which the special elastic body head 410 having thermal conductivity is attached. The substrate board 100A is held together and heated and pressurized. Thereby, the wiring layer (connection terminal) 320 of the film substrate 300 and the connection terminal of the semiconductor chip 200, and the wiring layer 320 of the film substrate 300 and the substrate connection portion 100a of the package substrate board 100A are joined.

Next, as shown in FIG. 10D, a plurality of solder balls 120 are formed on the back surface of the package substrate board 100A. Thereafter, the package substrate board 100A is singulated to obtain a desired semiconductor package 90.

FIG. 11 shows a cross-sectional configuration of electrical connection between the film substrate 300 and the semiconductor chip 200. As shown in FIG. 11, the connection terminal 320 b formed on the film substrate 300 is electrically connected to the chip connection part 200 b exposed from the protective film 211 formed on the element formation surface 200 a of the semiconductor chip 200. More specifically, solder bumps or gold (Au) bumps or Cu pillars 213 constituting the chip connection part 200b selectively compress the anisotropic conductive film 330 constituting the film substrate 300 in the film thickness direction. Accordingly, the connection terminal 320b of the film substrate 300 is electrically connected.

FIG. 12 shows a cross-sectional configuration of electrical connection between the film substrate 300 and the package substrate 100. As shown in FIG. 12, the connection terminal 320 b formed on the film substrate 300 is electrically connected to the substrate connection part 100 a exposed from the protective film 125 formed on the main surface of the package substrate 100. More specifically, the solder bumps or Au bumps or Cu pillars 113 constituting the substrate connection part 100a selectively compress the anisotropic conductive film 330 constituting the film substrate 300 in the film thickness direction, thereby It is electrically connected to the connection terminal 320b of the film substrate 300.

Hereinafter, various modified examples of the manufacturing method will be described with appropriate drawings.

(First Modification of Manufacturing Method)
As a first modification of the manufacturing method, the film substrate 300 including the anisotropic conductive film 330 is formed in advance into a shape connected to the semiconductor chip 200 and the package substrate 100 using an upper mold and a lower mold. Also good. In this way, it is possible to prevent the displacement of the bonding position when the film substrate 300 is bonded to the package substrate 100, so that the defect rate in the bonding process can be reduced.

(Second Modification of Manufacturing Method)
As a second modification of the manufacturing method, instead of forming solder bumps, Au bumps or Cu pillars 113 on the element formation surface 200a of the semiconductor chip 200 and the main surface of the package substrate 100, a wiring layer constituting the film substrate 300 Solder bumps, Au bumps, or Cu pillars 113 may be formed on 320. In this way, solder bumps, Au bumps, or Cu pillars 113 can be collectively formed on the wiring layer 320 of the film substrate 300, and the manufacturing process can be simplified.

(Third Modification of Manufacturing Method)
In the third modified example of the manufacturing method, as in the second modified example, any of solder bumps, Au bumps, and Cu pillars 113 is provided on the element formation surface 200a of the semiconductor chip 200 and the main surface of the package substrate 100. Not provided. Furthermore, the anisotropic conductive film 330 constituting the film substrate 300 is used only on the element forming surface 200a of the semiconductor chip 200 and the region covering the substrate connecting portion 100a in the package substrate 100.

That is, first, the anisotropic conductive film 330 is bonded to the area on the chip which is the element formation surface 200a of the semiconductor chip 200.

Subsequently, solder bumps, Au bumps, or Cu pillars 113 are formed on the wiring layers 320 constituting the film substrate 300 in regions corresponding to the chip connection portion 200b and the substrate connection portion 100a, respectively.

Subsequently, as shown in FIG. 13, the wiring 110 is formed on the main surface of the package substrate board 100A, while none of the solder bumps, Au bumps, and Cu pillars 113 are formed. Thereafter, for example, the anisotropic conductive film 330 separated into four pieces is bonded to the region on the substrate which is the substrate connecting portion 100a connected to the film substrate 300 on the main surface of the package substrate board 100A.

Subsequently, as shown in FIG. 14A, the semiconductor chip 200 is aligned and fixed to the chip mounting region on the main surface of the package substrate board 100A.

Subsequently, as shown in FIG. 14B, the individualized film substrate 300 is placed by being aligned with the semiconductor chip 200 and the package substrate board 100A.

Subsequently, as shown in FIG. 14C, the film substrate 300 and the semiconductor chip 200, and the film substrate 300 and the package substrate board 100A are bundled using the heating and pressurizing head having the special elastic body head described above. Hold and heat and pressurize. Thereby, the wiring layer 320 of the film substrate 300, the connection terminal of the semiconductor chip 200, and the substrate connection part 100a of the package substrate board 100A are bonded to each other. Subsequently, a plurality of solder balls 120 are formed on the back surface of the package substrate board 100A, and then the package substrate board 100A is singulated to obtain a desired semiconductor package 90.

As described above, according to the third modification, the anisotropic conductive film 330 is divided into the chip connection portion of the semiconductor chip 200 and the substrate connection portion of the package substrate 100. The amount used can be reduced.

(Fourth Modification of Manufacturing Method)
As a fourth modification of the manufacturing method, the semiconductor chip 200 may be bonded to the film substrate 300, and then the film substrate 300 bonded to the semiconductor chip 200 may be bonded to the package substrate 100.

Specifically, as shown in FIG. 15A, the film substrate 300 and the semiconductor chip 200 are bonded using a support base 420 and a heating / pressurizing head 401 whose surfaces facing each other are flat. Can do. At this time, if the elastic film 202 is provided on the back surface of the semiconductor chip 200 supported by the support base 420, the occurrence rate of chip cracking can be suppressed.

Further, as shown in FIG. 15B, the film substrate 300 and the package substrate 100 are joined using a heating / pressurizing head 401 having a planar shape that presses only the substrate connection portion 100 a in the package substrate 100. be able to.

As described above, the bonding between the film substrate 300 and the semiconductor chip 200 and the bonding between the film substrate 300 and the package substrate 100 are performed in separate steps, whereby the mutual alignment can be performed in each step. As a result, since the accuracy of the alignment can be relaxed, the defect rate at the time of assembly can be reduced.

(Fifth Modification of Manufacturing Method)
As a fifth modification of the manufacturing method, a solder bump or a solder film melted and attached instead of the solder bump for bonding the film substrate 300 and the semiconductor chip 200 and bonding the film substrate 300 and the package substrate 100 is used. It may be used. If it does in this way, since it can form cheaper than Cu pillar, manufacturing cost can be reduced.

Specifically, first, a solder bump or a solder film is formed on the element forming surface of the semiconductor chip 200 by a transfer method or the like.

Next, as shown in FIG. 16A, the film substrate 300 and the semiconductor chip 200 are joined using the support table 420 and the heating and pressing head 401 described above. In the fifth modified example, since the anisotropic conductive film 330 is not used, the solder bump formed on the semiconductor chip 200 is sealed with the resin material 203. Thereafter, the film substrate 300 to which the semiconductor chip 200 is bonded is placed in alignment with the package substrate 100.

Next, as shown in FIG. 16B, the film substrate 300 is bonded to the package substrate board 100A using the heating and pressing head 401 described above.

Next, as shown in FIG. 16C, the solder bumps 113 and the electrode pads 112 formed on the package substrate board 100A may be sealed with a resin material 203. Thereafter, solder balls are formed on the back surface of the package substrate board 100A and separated into individual pieces.

(Modified example of film substrate)
-First modification-
FIG. 17 shows a planar shape according to a first modification of the film substrate 300. As shown in FIG. 17, the film substrate 300 according to this modification is provided with notches 300a that reach the four corners of the chip covering region 300A of the semiconductor chip. In this way, the difference between the height of the semiconductor chip connecting portion 200a in the film substrate 300 and the height of the substrate connecting portion 100a of the package substrate 100 in the film substrate 300 causes the film substrate 300 to be bonded to the package substrate 100. Twist can be prevented.

In this modification, the notch 300a is provided in all four corners of the chip covering region 300A. However, if at least one notch 300a is provided, an effect can be obtained.

Further, the notch 300a does not necessarily reach the corner of the chip covering region 300A.

-Second modification-
FIG. 18 shows a planar shape according to a second modification of the film substrate 300. As shown in FIG. 18, the film substrate 300 according to the present modified example is a notch that is notched with a narrower width than the first modified example from its four corners toward each corner of the chip covering region 300A. A portion 300a is provided. In this way, the film substrate 300 can form wirings in directions other than the direction perpendicular to the boundary line of the chip covering region 300A. For this reason, the pitch of the wiring from the chip connection portion of the semiconductor chip 200 to the substrate connection portion of the package substrate 100 can be increased.

In addition, also in this modification, an effect can be acquired if at least 1 notch part 300a is provided.

-Third modification-
FIG. 19 shows a planar shape according to a third modification of the film substrate 300. As shown in FIG. 19, in this modified example, in addition to the notched portion 300a provided as the second modified example, a narrow notched portion that reaches from each side of the film substrate 300 to the opposite side of the chip covering region 300A. A portion 300b is provided. In this way, even when the element formation surface, which is the upper surface of the semiconductor chip 200, and the main surface of the package substrate 100 are not parallel, twisting during bonding of the film substrate 300 to the package substrate 100 is prevented. be able to.

In this modification as well, it is effective to provide at least one

notch

300a, 300b.

Further, the

notches

300a and 300b do not necessarily need to reach the chip covering region 300A.

-Fourth modification-
FIG. 20 shows a planar shape according to a fourth modification of the film substrate 300.

As shown in FIG. 20, in this modified example, the

cutout portions

300a and 300b are the same as in the third modified example, but the film substrate 300 is provided with two chip covering regions 300A. That is, a semiconductor package in which two semiconductor chips 200 are mounted side by side on the main surface of the package substrate 100 is assumed.

In this way, since the wiring provided on the film substrate 300 has a wiring pitch smaller than that of the package substrate 100, the number of wirings that can be connected between the two semiconductor chips 200 can be easily increased. Thereby, a coplanar waveguide can be provided, and a signal including a high frequency can be easily transmitted.

In addition, each modification of the planar shape of the film substrate mentioned above is not restricted to 1st Embodiment, In any of the semiconductor package which concerns on 2nd Embodiment, 3rd Embodiment, and 4th Embodiment mentioned later. Is also applicable.
(Second Embodiment)
A semiconductor package according to the second embodiment of the present disclosure will be described with reference to FIGS. FIG. 21 shows a cross-sectional configuration of a semiconductor package according to the second embodiment, and FIG. 22 shows a connection portion between two stacked semiconductor chips, an enlarged plan view thereof, and a plan configuration of an opening portion of a film substrate passing therethrough. FIG. 23 shows a cross-sectional configuration along the line XXIII-XXIII in FIG. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 21, the semiconductor package 91 according to the second embodiment is formed by interposing a film substrate 300 on a semiconductor chip 200 (hereinafter referred to as the first semiconductor chip 200 in the present embodiment). 2 A configuration in which a semiconductor chip 250 is mounted is adopted. The second semiconductor chip 250 is bonded to the film substrate 300 with an adhesive 201 such as a thermosetting resin.

When the first semiconductor chip 200 is a logic chip, for example, the second semiconductor chip 250 is assumed to be a memory chip. However, the first semiconductor chip 200 is not limited to a logic chip, and the second semiconductor chip 250 is not limited to a memory chip.

As shown in FIG. 22, an inter-chip connection region 210a is formed at the center of the element formation surface 200a of the first semiconductor chip 200 and the center of the element formation surface 250a of the second semiconductor chip 250 according to the present embodiment. Is provided. The film substrate 300 is provided with an opening 300c that exposes the inter-chip connection region 210a. Accordingly, the second semiconductor chip 250 is a chip-on-chip that is flip-chip mounted on the first semiconductor chip 200.

Next, as shown in the enlarged view of the inter-chip connection region 210a in FIG. 22, a plurality of inter-chip connection portions 200c are arranged in a matrix, for example. As shown in FIG. 23, each inter-chip connecting portion 200c includes, for example, an electrode pad 212 made of Al, a Cu pillar 213 formed thereon, and a solder bump 214 formed on the top surface of the Cu pillar 213. It consists of. In addition, each inter-chip connection unit 200 c corresponds to a third connection unit in the first semiconductor chip 200.

According to the second embodiment, the same effects as those of the first embodiment can be obtained, and even if the second semiconductor chip 250 is stacked on the first semiconductor chip 200, the heat dissipation of the first semiconductor chip 200 is achieved. Can be secured by the wiring layer 320 of the film substrate 300.

(Production method)
The main part of the semiconductor package manufacturing method according to the second embodiment will be described below with reference to FIGS. 24 (a) to 24 (c).

First, in addition to the chip connection part 200b with the film substrate 300, the inter-chip connection part 200c with the second semiconductor chip 250 is formed for the first semiconductor chip 200. Here, the chip connection part 200b and the inter-chip connection are formed. The part 200c includes a Cu pillar 213 and a solder bump 214 shown in FIG. Also, the inter-chip connection portion 200 c including the Cu pillar 213 and the solder bump 214 is formed also for the inter-chip connection region 210 a in the second semiconductor chip 250. In addition, an opening 300c corresponding to the inter-chip connection region 210a is provided at the center of the chip mounting region 300A in the film substrate 300.

Subsequently, similarly to the manufacturing method of the first embodiment, the first semiconductor chip 200 and the film substrate 300 are bonded onto the package substrate 100.

Next, as shown in FIG. 24A, the second semiconductor chip 250 is positioned and placed on the film substrate 300, and the second semiconductor chip 250 is heated and pressed by the heating and pressing head 401. The second semiconductor chip 250 is bonded to the first semiconductor chip 200.

Next, as shown in FIG. 24B, an adhesive 201 made of a resin or the like is injected between the second semiconductor chip 250 and the film substrate 300 and bonded to each other.

Next, as shown in FIG. 24C, a plurality of solder balls 120 are formed on the back surface of the package substrate board 100A, and then the package substrate board 100A is singulated to obtain a desired semiconductor package 91.

(Third embodiment)
A semiconductor package according to the third embodiment of the present disclosure will be described with reference to FIGS. 25 and 26. FIG. 25 illustrates a planar configuration of the semiconductor package according to the third embodiment, and FIG. 26 illustrates a cross-sectional configuration taken along line XXVI-XXVI in FIG. Also in the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIGS. 25 and 26, the semiconductor package 92 according to the third embodiment uses a lead frame 500 shown in FIG. 27 as a package substrate. As the lead frame 500, for example, QFP (Quad Flat Package), TQFP (Thin Quad Flat Package), QFN (Quad Flat Non-Leaded Package), or the like can be used.

On the die pad 500B of the lead frame 500, the semiconductor chip 200 is fixed by an adhesive material 201 such as silver candy. The configuration of the chip connection part 200b in the semiconductor chip 200 is the same as that of the first embodiment.

As shown in FIG. 26, solder bumps, Au bumps, or Cu pillars 513 are provided in the lead connection portions 500a that are electrical connection portions with the film substrate 300 in the respective leads 500c. A holding frame 550 made of a planar rectangular resin material is bonded to the periphery of the film substrate 300 in each lead 500 c so as to surround the film substrate 300. The holding frame 550 is used for holding the individual leads 500c when the lead frame 500 is singulated, and when the outer end of each lead 500c is cut off, and the outer end is used as the external connection portion 500b. As a supporting member for the jig when bent.

According to the third embodiment, the same effects as those of the first embodiment can be obtained, and a low-cost lead frame 550 such as QFP can be used as a package substrate. Therefore, the manufacturing cost of the semiconductor package 92 can be reduced. Can be reduced.

Further, normally, the semiconductor chip mounted on the lead frame 550 is sealed with ceramic or sealing resin, but in this embodiment, since it is covered with the thin film substrate 300, it has excellent heat dissipation characteristics, In addition, noise mixed in the electric signal is also reduced.

In the present specification, the plate-like metal member including the lead 500c with the periphery cut off and the die pad 500B is also referred to as a lead frame for convenience.

Also in this embodiment, two or more semiconductor chips 200 may be mounted on one die pad 500B.

(Production method)
The main part of the semiconductor package manufacturing method according to the third embodiment will be described below with reference to FIGS.

First, as shown in FIG. 27, for example, a lead frame aggregate 500A is prepared in which a plurality of lead frames 500 in a state before the QFP lead frame 500 is singulated are included in a matrix. As shown in the partial enlarged plan view, each lead frame 500 has a die pad 500B, which is a chip mounting area, at the center, and a plurality of lead frames 500 arranged radially extending from the periphery of the die pad 500B to the outside. A lead 500c.

The lead frame 500 is provided with a film substrate mounting area 500C for mounting the film substrate 300 so as to cover the die pad 500B. The film substrate mounting area 500C is disposed inside a dam bar 500d provided in the vicinity of the outer end of each lead 500c. Note that the dam bar 500d is provided for holding the leads in the lead frame state between adjacent ones, and usually for preventing the sealing resin from flowing out when the sealing resin is injected.

Subsequently, solder bumps, Au bumps, or Cu pillars 513 are formed on the periphery of the film substrate mounting area 500C on each lead 500c. Alternatively, a solder film melted and attached instead of the solder bump may be used. In this case, since it can be formed at a lower cost than any of the solder bump, Au bump, and Cu pillar 513, the manufacturing cost can be reduced.

Next, as shown in FIG. 28A, the semiconductor chip 200 is fixed on the lead frame aggregate 500A with an adhesive 201 such as a silver candy using an alignment mark provided on the element formation surface 200a. To do.

Next, as shown in FIG. 28 (b), the separated film substrate 300 is placed by being aligned with the semiconductor chip 200 and the lead frame assembly 500A.

Next, as shown in FIG. 28 (c), the film substrate 300 and the semiconductor chip 200, and the film substrate 300 and the leads are read using the heating / pressurizing head 400 to which the special elastic body head 410 having thermal conductivity is attached. The frame aggregate 500A is held together and heated and pressurized. Thereby, the wiring layer 320 of the film substrate 300 and the connection terminal of the semiconductor chip 200, and the wiring layer 320 of the film substrate 300 and the lead connection portion 500a of the lead frame assembly 500A are joined.

Next, as shown in FIG. 29A, for each lead frame 500 in the lead frame assembly 500A, a holding frame made of resin around the film substrate 300 using the upper mold 430 and the lower mold 431. 550 is placed and glued.

Next, as shown in FIG. 29 (b), the peripheral portion of the lead frame 500 is cut off to separate each lead 500c, and then the outside of each lead 500c is bent downward. As a result, a desired individual semiconductor package 92 can be obtained from the lead frame assembly 500A.

(Fourth embodiment)
A semiconductor package according to the fourth embodiment of the present disclosure will be described with reference to FIG. FIG. 30 illustrates a cross-sectional configuration of the semiconductor package according to the fourth embodiment. In the fourth embodiment, the same components as those in the first to third embodiments are denoted by the same reference numerals.

As shown in FIG. 30, the semiconductor package 93 according to the fourth embodiment uses a lead frame 500 such as QFP shown in FIG. 27 as a package substrate, as in the third embodiment. On the semiconductor chip 200 (hereinafter, referred to as the first semiconductor chip 200 in the present embodiment), Cu pillars 213 exposed from the opening 300c provided in the film substrate 300 are disposed, as in the second embodiment. A connected second semiconductor chip 250 is mounted. The second semiconductor chip 250 is bonded to the film substrate 300 with an adhesive 201 such as a thermosetting resin.

The first semiconductor chip 200 is assumed to be a logic chip, for example, and the second semiconductor chip 250 is assumed to be a memory chip, for example. However, the combination of the first semiconductor chip 200 and the second semiconductor chip 250 is not limited to this.

According to the fourth embodiment, the same effects as those of the second embodiment and the third embodiment can be obtained.
Since the thin film substrate 300 is interposed, a chip-on-chip structure can be easily performed.

(Production method)
The main part of the semiconductor package manufacturing method according to the fourth embodiment will be described below with reference to FIGS. 31 (a) to 31 (c).

First, in addition to the chip connection portion with the film substrate 300, an interchip connection portion with the second semiconductor chip 250 is formed for the first semiconductor chip 200. Here, the chip connection portion and the interchip connection portion are: The structure includes the Cu pillar 213 and the solder bump 214 shown in FIG. Further, an inter-chip connection portion including the Cu pillar 213 and the solder bump 214 is also formed in the inter-chip connection region in the second semiconductor chip 250. Further, an opening corresponding to the inter-chip connection region is provided at the center of the chip mounting region 300A in the film substrate 300.

Subsequently, as in the first embodiment, the first semiconductor chip 200 and the film substrate 300 are bonded onto the lead frame 500.

Next, as shown in FIG. 31A, the second semiconductor chip 250 is positioned and placed on the film substrate 300, and the second semiconductor chip 250 is heated and pressed by the heating and pressing head 401. The second semiconductor chip 250 is bonded to the first semiconductor chip 200.

Next, as shown in FIG. 31 (b), an adhesive 201 made of resin or the like is injected between the second semiconductor chip 250 and the film substrate 300 to adhere to each other.

Next, as shown in FIG. 31 (c), for each lead frame 500 in the lead frame assembly 500A, a holding frame made of resin around the film substrate 300 using the upper mold 430 and the lower mold 431. 550 is placed and glued.

Next, the periphery of the lead frame 500 is cut off to separate each lead 500c, and then the outside of each lead 500c is bent downward. As a result, a desired individual semiconductor package 93 can be obtained from the lead frame assembly 500A.

The semiconductor package according to the present invention is useful as a semiconductor package having a package substrate with high resistance to external stress and a simple structure.

90, 91, 92, 93 Semiconductor package 100 Package substrate 100A Package substrate board 100B Chip mounting region 100a Substrate connection portion (second connection portion)
100C Film substrate mounting region 110 Wiring 111 Through hole 112 Electrode pad 113 Solder bump / copper (Cu) pillar / gold (Au) bump / solder film 120 Solder ball 200 Semiconductor chip (first semiconductor chip)
200A Semiconductor wafer 200B Semiconductor chip region 200a Element formation surface 200b Chip connection part (first connection part)
200c Chip-to-chip connection (third connection)
201 Adhesive Material 202 Elastic Film 203 Resin Material 210 Chip Connection Area 210a Interchip Connection Area 211 Protective Film 212 Electrode Pad 213 Solder Bump / Copper (Cu) Pillar 214 Solder Bump 250 Second Semiconductor Chip 250a Element Forming Surface 300 Film Substrate 300A Chip covering region 300B Chip connecting region 300C1 Substrate narrow pitch connecting portion 300C2 Substrate wide

pitch connecting portion

300a, 300b Notch portion 300c Opening portion 310 Film body 320 Wiring layer 320a Wiring (wiring pattern)
320b Connection terminal 330 Anisotropic conductive film (AFC)
500 Lead frame 500A Lead frame assembly 500B Die pad (chip mounting area)
500C Film substrate mounting area 500a Lead connection part (second connection part)
500b External connection portion 500c Lead 513 Solder bump / copper (Cu) pillar / gold (Au) bump / solder film

Claims

A package substrate;
A first semiconductor chip held on a main surface of the package substrate and having an element formation surface on the opposite side to the package substrate;
A film substrate that covers the first semiconductor chip and is held on the element formation surface of the first semiconductor chip and the upper surface of the package substrate;
A first connection portion is provided on the element formation surface of the first semiconductor chip,
A second connection portion is provided on the upper surface of the package substrate,
The film substrate has wiring provided on the side facing the first semiconductor chip,
The first connection portion of the first semiconductor chip is electrically connected to the wiring of the film substrate;
The film substrate and the wiring are extended to the outside of the first semiconductor chip,
The wiring is a semiconductor package that is electrically connected to the second connection portion of the package substrate.
The semiconductor package according to claim 1,
The semiconductor package, wherein the wiring of the film substrate is provided only on a side facing the first semiconductor chip.
The semiconductor package according to claim 1 or 2,
The wiring of the film substrate is a semiconductor package in which a wiring pitch in a peripheral region of the second connection portion of the package substrate is larger than a wiring pitch in a peripheral region of the first connection portion of the first semiconductor chip.
The semiconductor package according to any one of claims 1 to 3,
The wiring of the film substrate is covered with an anisotropic conductive film,
In the semiconductor package, electrical connection between the first connection part and the second connection part in the wiring is selective anisotropic connection in the anisotropic conductive film.
The semiconductor package according to claim 4,
The anisotropic conductive film is divided into an on-chip region disposed on the element formation surface of the first semiconductor chip and an on-substrate region disposed on the second connection portion of the package substrate. Semiconductor package.
The semiconductor package according to any one of claims 1 to 3,
The wiring of the film substrate is a semiconductor package connected to the first connection part and the two connection parts by solder.
The semiconductor package according to any one of claims 1 to 6,
At least two of the first semiconductor chips are arranged on the main surface of the package substrate,
The film substrate and the wiring are a semiconductor package extended to the outside of the at least two first semiconductor chips.
The semiconductor package according to any one of claims 1 to 7,
A second semiconductor chip held on the first semiconductor chip with the film substrate interposed therebetween;
The first semiconductor chip has a third connection portion on the element formation surface,
The second semiconductor chip is a semiconductor package electrically connected to the third connection part exposed from an opening provided in the film substrate.
The semiconductor package according to any one of claims 1 to 8,
The film substrate is a semiconductor package having a notch at a portion facing at least one corner of the first semiconductor chip.
The semiconductor package according to claim 9.
The film substrate is a semiconductor package having a notch at a portion facing at least one side of the first semiconductor chip.
A lead frame;
A first semiconductor chip held on the main surface of the lead frame and having an element forming surface on the opposite side to the lead frame;
A film substrate that covers the first semiconductor chip and is held on the element formation surface of the first semiconductor chip and the upper surface of the lead frame;
A first connection portion is provided on the element formation surface of the first semiconductor chip,
A second connection portion is provided on the upper surface of the lead frame,
The film substrate has wiring provided on the side facing the first semiconductor chip,
The first connection portion of the first semiconductor chip is electrically connected to the wiring of the film substrate;
The film substrate and the wiring are extended to the outside of the first semiconductor chip,
The wiring is a semiconductor package electrically connected to the second connection portion of the lead frame.
The semiconductor package according to claim 11, wherein
The semiconductor package, wherein the wiring of the film substrate is provided only on a side facing the first semiconductor chip.
The semiconductor package according to claim 11 or 12,
The wiring of the film substrate is a semiconductor package in which a wiring pitch in a peripheral region of the second connection portion of the lead frame is larger than a wiring pitch in a peripheral region of the first connection portion of the first semiconductor chip.
The semiconductor package according to any one of claims 11 to 13,
The wiring of the film substrate is covered with an anisotropic conductive film,
In the semiconductor package, electrical connection between the first connection part and the second connection part in the wiring is selective anisotropic connection in the anisotropic conductive film.
The semiconductor package according to claim 14, wherein
The anisotropic conductive film is divided into an on-chip region disposed on the element formation surface of the first semiconductor chip and an on-substrate region disposed on the second connection portion of the lead frame. Semiconductor package.
The semiconductor package according to any one of claims 11 to 13,
The wiring of the film substrate is a semiconductor package connected to the first connection part and the second connection part by soldering.
The semiconductor package according to any one of claims 11 to 16,
At least two of the first semiconductor chips are disposed on the main surface of the lead frame,
The film substrate and the wiring are a semiconductor package extended to the outside of the at least two first semiconductor chips.
The semiconductor package according to any one of claims 11 to 17,
A second semiconductor chip held on the first semiconductor chip with the film substrate interposed therebetween;
The first semiconductor chip has a third connection portion on the element formation surface,
The second semiconductor chip is a semiconductor package electrically connected to the third connection part exposed from an opening provided in the film substrate.
The semiconductor package according to any one of claims 11 to 18,
The film substrate is a semiconductor package having a notch at a portion facing at least one corner of the first semiconductor chip.
The semiconductor package according to claim 19,
The film substrate is a semiconductor package having a notch at a portion facing at least one side of the first semiconductor chip.