JP4342577B2 - Semiconductor chip mounting structure - Google Patents

Semiconductor chip mounting structure Download PDF

Info

Publication number
JP4342577B2
JP4342577B2 JP2007187328A JP2007187328A JP4342577B2 JP 4342577 B2 JP4342577 B2 JP 4342577B2 JP 2007187328 A JP2007187328 A JP 2007187328A JP 2007187328 A JP2007187328 A JP 2007187328A JP 4342577 B2 JP4342577 B2 JP 4342577B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrode terminal
mounting structure
terminal group
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007187328A
Other languages
Japanese (ja)
Other versions
JP2007266644A (en
Inventor
啓 村山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007187328A priority Critical patent/JP4342577B2/en
Publication of JP2007266644A publication Critical patent/JP2007266644A/en
Application granted granted Critical
Publication of JP4342577B2 publication Critical patent/JP4342577B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

本発明は、配線基板上の配線パターンに半導体チップをフリップチップ接続により搭載した半導体チップの実装構造に関する。   The present invention relates to a semiconductor chip mounting structure in which a semiconductor chip is mounted on a wiring pattern on a wiring board by flip chip connection.

近年、半導体装置の小型化・高集積化による高密度実装の進行に伴い、ＢＧＡ（Ball Grid Array)タイプの半導体装置に代表されるように、配線基板上の配線パターンに半導体チップをフリップチップ接続により搭載した半導体チップの実装構造が用いられている。一般に、配線基板の一方の面に形成された配線パターンに半導体チップがフリップチップ接続により搭載されており、基板の他方の面に、上記配線パターンに電気的に接続された外部接続端子が形成されている。   In recent years, with the progress of high-density packaging due to miniaturization and high integration of semiconductor devices, flip chip connection of semiconductor chips to wiring patterns on a wiring board is typified by BGA (Ball Grid Array) type semiconductor devices. The mounting structure of the semiconductor chip mounted by (1) is used. Generally, a semiconductor chip is mounted on a wiring pattern formed on one surface of a wiring board by flip chip connection, and an external connection terminal electrically connected to the wiring pattern is formed on the other surface of the board. ing.

図１に、従来のＢＧＡタイプの半導体装置の実装構造を示す。
半導体装置１１は、半導体チップ１２、半導体チップの電極端子としてのはんだバンプ１３、配線基板１４、アンダーフィル１９、および配線基板１４の外部接続端子としてのはんだボール１７で基本的に構成されている。この半導体装置１１のはんだボール７を実装基板１８に接合して半導体装置１１を実装することにより実装構造が完成する。 FIG. 1 shows a mounting structure of a conventional BGA type semiconductor device.
The semiconductor device 11 basically includes a semiconductor chip 12, solder bumps 13 as electrode terminals of the semiconductor chip, a wiring board 14, an underfill 19, and solder balls 17 as external connection terminals of the wiring board 14. The mounting structure is completed by bonding the solder balls 7 of the semiconductor device 11 to the mounting substrate 18 and mounting the semiconductor device 11.

半導体チップ１２は配線基板１４の一方の面１４ａに搭載されている。半導体チップ１２の面１２ａ上に電極端子として形成されたはんだバンプ１３は、配線基板１４の面１４ａ上の配線パターン１４ｃに電気的に接続されている。はんだバンプ１３は、例えば、半導体チップ１２の面１２ａにマスクを形成した後にはんだめっきすることにより形成される。これにより、面１２ａ上に、はんだバンプから成る電極端子１３が多数配設される。   The semiconductor chip 12 is mounted on one surface 14 a of the wiring substrate 14. Solder bumps 13 formed as electrode terminals on the surface 12 a of the semiconductor chip 12 are electrically connected to the wiring pattern 14 c on the surface 14 a of the wiring substrate 14. The solder bump 13 is formed, for example, by solder plating after forming a mask on the surface 12a of the semiconductor chip 12. Thereby, a large number of electrode terminals 13 made of solder bumps are disposed on the surface 12a.

半導体チップ１２を配線基板１４の面１４ａ上に載置して、はんだバンプ１３を配線パターン１４ｃに接続した状態では、この接続部以外では半導体チップ１２の面１２ａと配線基板１４の面１４ａとの間には空隙が残っている。アンダーフィル１９は、この空隙に例えばエポキシ系の絶縁性樹脂をディスペンサーにより充填することにより形成されている。   In a state where the semiconductor chip 12 is placed on the surface 14a of the wiring board 14 and the solder bumps 13 are connected to the wiring pattern 14c, the surface 12a of the semiconductor chip 12 and the surface 14a of the wiring board 14 except for this connection portion. There are gaps between them. The underfill 19 is formed by filling the gap with, for example, an epoxy insulating resin with a dispenser.

配線基板１４の他方の面１４ｂ上に形成されているパッド（図示せず）が、配線基板を貫通するスルーホールめっき部（図示せず）を介して、反対側の面１４ａ上の配線パターン１４ｃと電気的に接続している。パッド上には外部接続端子としてのはんだボール１７が接合されている。
上記半導体装置１１のはんだボール１７を実装基板１８上のランド１８ａに当接させた状態で加熱することにより、半導体装置１１が実装基板１８に実装され、図１の実装構造が完成する。 A pad (not shown) formed on the other surface 14b of the wiring substrate 14 is connected to a wiring pattern 14c on the opposite surface 14a via a through-hole plating portion (not shown) penetrating the wiring substrate. And is electrically connected. Solder balls 17 as external connection terminals are joined on the pads.
By heating the solder balls 17 of the semiconductor device 11 in contact with the lands 18a on the mounting substrate 18, the semiconductor device 11 is mounted on the mounting substrate 18, and the mounting structure of FIG. 1 is completed.

一般に配線基板１４と実装基板１８は同種または類似の有機材料（樹脂）で作られているので、両者の熱膨張係数は同等である。半導体チップ１２を直接搭載する配線基板１４としては、フレキシブル基板や両面銅張積層基板等の有機材料系基板が好適であり、多くの場合に用いられる。このような有機材料系基板は一般に剛性が比較的低い。   In general, since the wiring board 14 and the mounting board 18 are made of the same or similar organic material (resin), their thermal expansion coefficients are the same. As the wiring substrate 14 on which the semiconductor chip 12 is directly mounted, an organic material substrate such as a flexible substrate or a double-sided copper-clad laminated substrate is suitable, and is used in many cases. Such an organic material-based substrate generally has a relatively low rigidity.

これら有機材料系基板に対して、配線基板１４上にアンダーフィルで固定されて搭載されている半導体チップ１２は剛性が極めて大きく、一方、熱膨張係数は小さい。
そのため、半導体装置１１を実装基板１８へ実装するために上記加熱を行うと、圧倒的に剛性の大きい半導体チップ１２により自由な変位を拘束されている配線基板１４の熱膨張は半導体チップ１２と同等に小さく、有機材料本来の比較的大きな熱膨張をする実装基板１８との間に見掛け上の熱膨張差が生じる。これにより発生した応力がはんだボール１７の接合部に集中し、配線基板１４上のはんだボール１７と実装基板１８上のパッド１８ａとの接合の信頼性が低下する。配線基板１４と半導体チップ１２との間に充填されて硬化した絶縁性樹脂から成るアンダーフィル１９は、上記熱応力を緩和できない。 With respect to these organic material-based substrates, the semiconductor chip 12 fixed and mounted on the wiring substrate 14 with an underfill has extremely high rigidity, while the coefficient of thermal expansion is small.
Therefore, when the heating is performed to mount the semiconductor device 11 on the mounting substrate 18, the thermal expansion of the wiring substrate 14 in which free displacement is restrained by the semiconductor chip 12 that is overwhelmingly rigid is equivalent to that of the semiconductor chip 12. Therefore, an apparent difference in thermal expansion occurs with respect to the mounting substrate 18 which is relatively small and inherently has a relatively large thermal expansion. The stress generated thereby concentrates on the joint portion of the solder ball 17, and the reliability of the joint between the solder ball 17 on the wiring substrate 14 and the pad 18a on the mounting substrate 18 decreases. The underfill 19 made of an insulating resin that is filled between the wiring substrate 14 and the semiconductor chip 12 and hardened cannot relax the thermal stress.

更に、半導体チップ１２と配線基板１４との熱膨張差により、半導体チップ１２の電極端子としてのはんだバンプ１３と配線基板１４上の配線パターン１４ｃとの接合の信頼性も低下する。
これらの現象は、半導体チップ１２の高集積化に伴って配線基板１４が大型化するほど顕著になる。 Furthermore, due to the difference in thermal expansion between the semiconductor chip 12 and the wiring substrate 14, the reliability of bonding between the solder bumps 13 as electrode terminals of the semiconductor chip 12 and the wiring pattern 14 c on the wiring substrate 14 is also lowered.
These phenomena become more prominent as the wiring substrate 14 becomes larger as the semiconductor chip 12 is highly integrated.

また、半導体チップ１２の電極端子配設面１２ａにはんだバンプ１４を形成するには、面１２ａにＵＢＭ（Under Bump Metal）を形成したりめっきを施したりする煩雑な製造工程を必要とするため、製造コストが高くならざるを得ない。
本発明は、配線基板に加わる熱応力を緩和して、半導体チップと配線基板との接続および配線基板と実装基板との接続の信頼性を高め、かつ安価に製造できる半導体チップの実装構造を提供することを目的とする。 Moreover, in order to form the solder bump 14 on the electrode terminal arrangement surface 12a of the semiconductor chip 12, a complicated manufacturing process of forming UBM (Under Bump Metal) or plating on the surface 12a is required. The manufacturing cost must be high.
The present invention provides a mounting structure of a semiconductor chip that can reduce the thermal stress applied to the wiring board, improve the connection between the semiconductor chip and the wiring board and the connection between the wiring board and the mounting board, and can be manufactured at low cost. The purpose is to do.

上記の目的を達成するために、本発明は下記（１）〜（１０）の半導体チップの実装構造を提供する。
（１）配線基板上の配線パターンに半導体チップをフリップチップ接続により搭載した半導体チップの実装構造において、
前記半導体チップの電極端子配設面上に多数の電極端子が配設されており、
前記電極端子配設面は、周囲領域と該周囲領域に囲まれた芯部領域から成るかまたは１対の側部帯域と該１対の側部帯域に挟まれた中央帯域から成り、
該多数の電極端子のうち、前記周囲領域または前記芯部領域または前記一対の側部帯域または前記中央帯域にある第1の電極端子群は前記配線基板と前記半導体チップとの間に介在するエポキシ樹脂から成る接着剤層により前記配線パターンに機械的に係合され且つ電気的に接続され、前記電極端子配設面の前記第１の電極端子群のある領域もしくは帯域以外の領域もしくは帯域にある第２の電極端子群は前記配線基板と前記半導体チップとの間に介在する室温での弾性率が１００ＭＰａ以下のエラストマー層により前記配線パターンに機械的に係合され且つ電気的に接続されていることを特徴とする半導体チップの実装構造。 In order to achieve the above object, the present invention provides the following semiconductor chip mounting structures (1) to (10).
(1) In a semiconductor chip mounting structure in which a semiconductor chip is mounted on a wiring pattern on a wiring board by flip chip connection,
A large number of electrode terminals are disposed on the electrode terminal disposition surface of the semiconductor chip,
The electrode terminal disposition surface is composed of a peripheral region and a core region surrounded by the peripheral region or a pair of side bands and a central band sandwiched between the pair of side bands,
Of the multiple electrode terminals, the first electrode terminal group in the peripheral region, the core region, the pair of side bands, or the central band is an epoxy interposed between the wiring board and the semiconductor chip. It is mechanically engaged with and electrically connected to the wiring pattern by an adhesive layer made of resin, and is in a region or a band other than a region or a band of the first electrode terminal group on the electrode terminal arrangement surface. The second electrode terminal group is mechanically engaged with and electrically connected to the wiring pattern by an elastomer layer having a modulus of elasticity at room temperature of 100 MPa or less interposed between the wiring substrate and the semiconductor chip. A semiconductor chip mounting structure.

（２）前記半導体チップの電極端子配設面は、周囲領域と、該周囲領域に囲まれた芯部領域とから成り、該周囲領域には前記第１の電極端子群が配設され、該芯部領域には前記第２の電極端子群が配設されていることを特徴とする上記（１）記載の半導体チップの実装構造。
（３）前記半導体チップの電極端子配設面は、周囲領域と、該周囲領域に囲まれた芯部領域とから成り、該周囲領域には前記第２の電極端子群が配設され、該芯部領域には前記第１の電極端子群が配設されていることを特徴とする上記（１）記載の半導体チップの実装構造。 (2) The electrode terminal disposition surface of the semiconductor chip is composed of a peripheral region and a core region surrounded by the peripheral region, and the first electrode terminal group is disposed in the peripheral region, The semiconductor chip mounting structure according to (1), wherein the second electrode terminal group is disposed in the core region.
(3) The electrode terminal disposition surface of the semiconductor chip is composed of a peripheral region and a core region surrounded by the peripheral region, and the second electrode terminal group is disposed in the peripheral region, The semiconductor chip mounting structure according to (1), wherein the first electrode terminal group is disposed in the core region.

（４）前記半導体チップの電極端子配設面は、対向する一対の側部帯域と、該一対の側部領域に挟まれた中央帯域とから成り、該側部帯域には前記第１の電極端子群が配設され、該中央帯域には前記第２の電極端子群が配設されていることを特徴とする上記（１）記載の半導体チップの実装構造。
（５）前記半導体チップの電極端子配設面は、対向する一対の側部帯域と、該一対の側部領域に挟まれた中央帯域とから成り、該側部帯域には前記第２の電極端子群が配設され、該中央帯域には前記第１の電極端子群が配設されていることを特徴とする上記（１）記載の半導体チップの実装構造。 (4) The electrode terminal disposition surface of the semiconductor chip is composed of a pair of opposing side bands and a central band sandwiched between the pair of side areas, and the side electrode includes the first electrode. The semiconductor chip mounting structure according to (1), wherein a terminal group is disposed, and the second electrode terminal group is disposed in the central band.
(5) The electrode terminal mounting surface of the semiconductor chip is composed of a pair of opposing side bands and a central band sandwiched between the pair of side areas, and the second electrode includes the second electrode. The semiconductor chip mounting structure according to (1), wherein a terminal group is provided, and the first electrode terminal group is provided in the central band.

（６）前記接着剤層は、異方導電性接着剤の塗布または異方導電性樹脂シートの貼着により形成されていることを特徴とする上記（１）記載の半導体チップの実装構造。
（７）前記接着剤層は、絶縁性樹脂から成ることを特徴とする上記（１）記載の半導体チップの実装構造。 (6) The semiconductor chip mounting structure according to the above (1), wherein the adhesive layer is formed by applying an anisotropic conductive adhesive or attaching an anisotropic conductive resin sheet.
(7) The semiconductor chip mounting structure according to (1), wherein the adhesive layer is made of an insulating resin.

（８）前記エラストマー層は、接着性を有する絶縁性樹脂から成ることを特徴とする上記（１）記載の半導体チップの実装構造。
（９）前記エラストマー層は、接着性を有する異方導電性樹脂の塗布または異方導電性樹脂シートの貼着により形成されていることを特徴とする上記（１）記載の半導体チップの実装構造。 (8) The semiconductor chip mounting structure according to (1), wherein the elastomer layer is made of an insulating resin having adhesiveness.
(9) The semiconductor chip mounting structure according to the above (1), wherein the elastomer layer is formed by application of an anisotropic conductive resin having adhesion or adhesion of an anisotropic conductive resin sheet. .

（１０）前記配線基板の一方の面に形成された前記配線パターンに前記半導体チップがフリップチップ接続により搭載されており、前記基板の他方の面に、前記配線パターンに電気的に接続された外部接続端子が形成されていることを特徴とする上記（１）から（９）までのいずれかに記載の半導体チップの実装構造。   (10) The semiconductor chip is mounted on the wiring pattern formed on one surface of the wiring substrate by flip chip connection, and the other surface of the substrate is electrically connected to the wiring pattern. 10. The semiconductor chip mounting structure according to any one of (1) to (9), wherein a connection terminal is formed.

半導体装置を構成する半導体チップと配線基板との間にエラストマー層および接着剤層を介在させて接合したので、半導体装置を実装基板に実装する際に両者間の熱膨張差により発生する熱応力が緩和され、はんだボールの接合部の応力集中が緩和され、半導体装置と実装基板との接合の信頼性が向上する。これは特に、半導体チップの高集積化に伴い配線基板が大型化した場合に有利である。   Since an elastomer layer and an adhesive layer are interposed between the semiconductor chip constituting the semiconductor device and the wiring board, the thermal stress generated due to the difference in thermal expansion between the two when the semiconductor device is mounted on the mounting board. As a result, the stress concentration at the joint portion of the solder ball is relaxed, and the reliability of the joint between the semiconductor device and the mounting substrate is improved. This is particularly advantageous when the size of the wiring board increases with the integration of semiconductor chips.

更に、エラストマー層は、半導体チップと配線基板との熱膨張差により半導体チップの電極端子と配線基板の配線パターンとの間に発生する熱応力をも緩和し、バンプ／配線パターン間の電気的接続の信頼性も向上させる。
接着剤層を異方導電性樹脂シートにより形成すれば、テープ状の異方導電性樹脂シートを配線基板に貼着するだけで接着剤層を形成できるので、製造効率が極めて高くなる。 Furthermore, the elastomer layer also relieves the thermal stress generated between the electrode terminal of the semiconductor chip and the wiring pattern of the wiring board due to the difference in thermal expansion between the semiconductor chip and the wiring board, and electrical connection between the bump / wiring pattern. Improve the reliability.
If the adhesive layer is formed of an anisotropic conductive resin sheet, the adhesive layer can be formed simply by sticking the tape-shaped anisotropic conductive resin sheet to the wiring board, so that the production efficiency is extremely high.

スタッドバンプはワイヤボンディングにより形成されるので、特にＵＢＭ工程やめっき工程を必要とするめっきバンプに比べて、製造工程を簡略化でき、製造コスト上有利である。   Since the stud bump is formed by wire bonding, the manufacturing process can be simplified and the manufacturing cost is advantageous as compared with a plating bump that requires a UBM process or a plating process.

以下、添付図面を参照し、本発明の望ましい実施態様を説明する。
図２に、半導体チップを配線基板上に搭載して成る半導体装置を実装基板に実装した、本発明による半導体チップの実装構造を示す。
図２において、本発明によるＢＧＡタイプの半導体装置１は、半導体チップ２、半導体チップ２の電極端子としてのスタッドバンプ３Ａ，３Ｂ、半導体チップ２を搭載する配線基板４、接着剤層５、エラストマー層６、および配線基板４の外部端子としてのはんだボール７で基本的に構成されている。この半導体装置１を実装基板８に接合することにより図２の実装構造が完成する。なお、この例では、チップサイズパッケージのうちＢＧＡタイプの半導体装置の実装構造について説明するが、本発明はこれに限定されるものではない。 Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 2 shows a semiconductor chip mounting structure according to the present invention in which a semiconductor device having a semiconductor chip mounted on a wiring board is mounted on a mounting board.
2, a BGA type semiconductor device 1 according to the present invention includes a semiconductor chip 2, stud bumps 3A and 3B as electrode terminals of the semiconductor chip 2, a wiring board 4 on which the semiconductor chip 2 is mounted, an adhesive layer 5, an elastomer layer. 6 and solder balls 7 as external terminals of the wiring board 4 are basically constituted. The semiconductor device 1 is bonded to the mounting substrate 8 to complete the mounting structure shown in FIG. In this example, a mounting structure of a BGA type semiconductor device in a chip size package will be described, but the present invention is not limited to this.

半導体チップ２の電極端子配設面２ａに、電極端子としての金スタッドバンプ３Ａ，３Ｂが多数配設されている。
図３に電極端子配設面２ａの平面図で示すように（電極端子は図示せず）、半導体チップ２の電極端子配設面２ａは、第１の電極端子群３Ａが配設されている周囲領域Ｐと、この周囲領域Ｐに囲まれ、第２の電極端子群３Ｂが配設されている芯部領域Ｑとから成る。なお、同図には便宜上少数の電極を示したが、実際には各領域Ｐ，Ｑにおいて例えば多数列を成す多数の電極が存在してよい。 A large number of gold stud bumps 3 </ b> A and 3 </ b> B as electrode terminals are arranged on the electrode terminal arrangement surface 2 a of the semiconductor chip 2.
As shown in a plan view of the electrode terminal arrangement surface 2a in FIG. 3 (electrode terminals are not shown), the electrode terminal arrangement surface 2a of the semiconductor chip 2 is provided with the first electrode terminal group 3A. It consists of a surrounding area P and a core area Q surrounded by the surrounding area P and provided with the second electrode terminal group 3B. Although a small number of electrodes are shown in the figure for convenience, in practice, there may be a large number of electrodes in, for example, a large number of rows in each of the regions P and Q.

図４（ａ）に示すように、周囲領域Ｐにある第１の電極端子群３Ａは接着剤層５により配線パターン４ｃに電気的に接続され（同図中「Ｐ（５）」と表示）、芯部領域Ｑにある第２の電極端子群３Ｂはエラストマー層６により配線パターン４ｃに電気的に接続されている（同図中「Ｑ（６）」と表示）。
半導体チップ２の周囲領域Ｐに対面する、配線基板４の面４ａの領域には、接着剤層５が形成されている。この周囲領域Ｐ内にある第１群の金スタッドバンプ３Ａは、接着剤層５内に進入して配線基板４の配線パターンｃと電気的導通を取って接続されている。接着剤層５は、典型的にはエポキシ樹脂から成り、これは従来からアンダーフィル材として用いられているものでよいし、異方導電性樹脂シートの形で用いてもよい。異方導電性シートは、樹脂系接着剤中に金属粒子等の導電性粒子が混入されており、加熱・加圧されることにより硬化・収縮して金スタッドバンプ３が金属粒子を介して配線パターン４ｃに押し当てられ、金スタッドバンプ３と配線パターン４ｃとの電気的接続をより容易にする。 As shown in FIG. 4A, the first electrode terminal group 3A in the peripheral region P is electrically connected to the wiring pattern 4c by the adhesive layer 5 (indicated as “P (5)” in the figure). The second electrode terminal group 3B in the core region Q is electrically connected to the wiring pattern 4c by the elastomer layer 6 (indicated as “Q (6)” in the figure).
An adhesive layer 5 is formed in a region of the surface 4 a of the wiring substrate 4 facing the peripheral region P of the semiconductor chip 2. The first group of gold stud bumps 3 </ b> A in the peripheral region P enters the adhesive layer 5 and is electrically connected to the wiring pattern c of the wiring board 4. The adhesive layer 5 is typically made of an epoxy resin, which may be conventionally used as an underfill material or may be used in the form of an anisotropic conductive resin sheet. The anisotropic conductive sheet has conductive particles such as metal particles mixed in a resin-based adhesive, and is cured and contracted by being heated and pressurized, so that the gold stud bump 3 is wired via the metal particles. The metal stud bump 3 is pressed against the pattern 4c to facilitate electrical connection between the gold stud bump 3 and the wiring pattern 4c.

半導体チップ２の芯部領域Ｑにある第２群の金スタッドバンプ３Ｂも、エラストマー層６内に進入して配線基板４の配線パターン４ｃと電気的導通を取って接続されている。エラストマー層６は、弾性率が１００ＭＰａ以下（室温）のものが好適に用いられ、具体的にはシリコーン樹脂等の弾力性に富みかつ接着性のある絶縁性樹脂あるいはシリコーン樹脂中に金やニッケル等の金属粒子を分散させた異方導電性樹脂で形成されている。   The second group of gold stud bumps 3B in the core region Q of the semiconductor chip 2 also enters the elastomer layer 6 and is electrically connected to the wiring pattern 4c of the wiring board 4. As the elastomer layer 6, one having an elastic modulus of 100 MPa or less (room temperature) is preferably used. Specifically, the elastic layer 6 is a highly elastic and adhesive insulating resin such as a silicone resin, or gold or nickel in the silicone resin. It is formed with an anisotropic conductive resin in which the metal particles are dispersed.

エラストマー層６は、配線基板４の一方の面４ａに印刷または塗布またはシート状エラストマーの接着により形成される。配線基板４の他方の面４ｂには、図示しないパッドが形成されており、その上に外部端子としてのはんだボール７が形成されている。
エラストマー層６を加熱により半硬化させ且つ接着性を有する状態にして、半導体チップを配線基板４上に載置した後、更に加熱しながら半導体チップ２の上面と配線基板４の下面４ｂとから加圧することにより、半導体チップ２の金スタッドバンプ３Ａ，３Ｂをそれぞれ接着剤層５およびエラストマー層６内に進入させ且つ半硬化状態のエラストマー層６を硬化・収縮させ、同時に、接着剤層５を硬化・収縮させる。これにより、半導体チップ２の金スタッドバンプ３Ａ，３Ｂと配線基板４の配線パターン４ｃとが機械的に係合され且つ電気的に接続される。その際、エラストマー層６として例えばシリコーン樹脂中に金属粒子が分散した異方導電性樹脂を用い、かつ／または、接着剤層５として異方導電性樹脂シートを用いると、エラストマー層６および／または接着層５に加圧方向の導電性が付与され、金スタッドバンプ３Ａ，３Ｂと配線パターン４ｃとの電気的接続が促進される。 The elastomer layer 6 is formed on one surface 4a of the wiring board 4 by printing or application or adhesion of a sheet-like elastomer. A pad (not shown) is formed on the other surface 4b of the wiring board 4, and solder balls 7 as external terminals are formed thereon.
After the elastomer layer 6 is semi-cured by heating and has an adhesive property, the semiconductor chip is placed on the wiring board 4 and then heated from the upper surface of the semiconductor chip 2 and the lower surface 4b of the wiring board 4 while being heated. By applying pressure, the gold stud bumps 3A and 3B of the semiconductor chip 2 enter the adhesive layer 5 and the elastomer layer 6, respectively, and the semi-cured elastomer layer 6 is cured and contracted, and at the same time, the adhesive layer 5 is cured.・ Shrink. Thereby, the gold stud bumps 3A and 3B of the semiconductor chip 2 and the wiring pattern 4c of the wiring substrate 4 are mechanically engaged and electrically connected. At that time, for example, when an anisotropic conductive resin in which metal particles are dispersed in a silicone resin is used as the elastomer layer 6 and / or an anisotropic conductive resin sheet is used as the adhesive layer 5, the elastomer layer 6 and / or The adhesive layer 5 is given conductivity in the pressing direction, and electrical connection between the gold stud bumps 3A and 3B and the wiring pattern 4c is promoted.

配線基板４は、従来から用いられているＦＲ−４基板、ＢＴ基板、ポリイミド基板等の絶縁性樹脂基板でよい。ＢＴ基板は、表面に銅箔を張り付けて配線パターンを形成した両面銅張積層基板の形でもよい。ポリイミド基板は、ポリイミドフィルムに銅箔を張り付けて配線パターンを形成したフレキシブル基板の形でもよい。半導体チップ２を搭載する側の、配線基板４の一方の面４ａに形成された配線パターン４ｃと、他方の面４ｂに形成された外部接続端子すなわちはんだボール７とは、配線基板４を板厚方向に貫通するスルーホールの内壁に形成されためっき層により電気的に接続されている。   The wiring substrate 4 may be an insulating resin substrate such as an FR-4 substrate, a BT substrate, or a polyimide substrate that has been conventionally used. The BT substrate may be in the form of a double-sided copper-clad laminate in which a wiring pattern is formed by attaching a copper foil to the surface. The polyimide substrate may be in the form of a flexible substrate in which a wiring pattern is formed by attaching a copper foil to a polyimide film. The wiring pattern 4c formed on one surface 4a of the wiring substrate 4 on the side on which the semiconductor chip 2 is mounted and the external connection terminals, that is, the solder balls 7 formed on the other surface 4b, They are electrically connected by a plating layer formed on the inner wall of the through hole penetrating in the direction.

半導体チップ２の面２ａ上の金スタッドバンプ３Ａ，３Ｂは、後に詳述するように、面２ａに金ワイヤを用いてワイヤボンディングしてから金ワイヤを所定位置で切断することにより形成されている。
上記のように作製した半導体装置１を実装基板８上に載置し、加熱することにより、はんだボール７が実装基板８のランド８ａと接合して、半導体装置１が実装基板８上に実装される。 The gold stud bumps 3A and 3B on the surface 2a of the semiconductor chip 2 are formed by wire bonding using a gold wire on the surface 2a and then cutting the gold wire at a predetermined position, as will be described in detail later. .
The semiconductor device 1 manufactured as described above is placed on the mounting substrate 8 and heated, so that the solder balls 7 are bonded to the lands 8a of the mounting substrate 8, and the semiconductor device 1 is mounted on the mounting substrate 8. The

本発明による半導体チップの実装構造においては、半導体チップ２と配線基板４との間に介在する、弾力性を有するエラストマー層６が、半導体装置１を実装基板８に接合する際に熱膨張差により両者間に発生する熱応力を緩和し、はんだボール７の接合部の応力集中を緩和し、配線基板４のはんだボール７と実装基板８のランド８ａとの接合の信頼性を向上させる。   In the semiconductor chip mounting structure according to the present invention, the elastic elastomer layer 6 interposed between the semiconductor chip 2 and the wiring substrate 4 is caused by a difference in thermal expansion when the semiconductor device 1 is bonded to the mounting substrate 8. The thermal stress generated between them is relieved, the stress concentration at the joint of the solder ball 7 is relieved, and the reliability of the joint between the solder ball 7 of the wiring board 4 and the land 8a of the mounting board 8 is improved.

更に、エラストマー層６は、半導体チップ２と配線基板４との熱膨張差により金スタッドバンプ３Ａ，３Ｂと配線パターン４ｃとの間に発生する熱応力をも緩和し、バンプ／配線パターン間の電気的接続の信頼性も向上させる。
接着剤層５を異方導電性樹脂シートにより形成すれば、テープ状の異方導電性樹脂シートを配線基板４に貼着するだけで接着剤層５を形成できるので、製造効率が極めて高くなる。 Furthermore, the elastomer layer 6 also relieves the thermal stress generated between the gold stud bumps 3A, 3B and the wiring pattern 4c due to the difference in thermal expansion between the semiconductor chip 2 and the wiring substrate 4, and the electric current between the bump / wiring pattern is reduced. The reliability of the connection is also improved.
If the adhesive layer 5 is formed of an anisotropic conductive resin sheet, the adhesive layer 5 can be formed simply by adhering the tape-shaped anisotropic conductive resin sheet to the wiring substrate 4, so that the production efficiency becomes extremely high. .

次に、図５（ａ）〜図５（ｆ）を参照して、図２の実装構造の製造工程を説明する。
先ず、図５（ａ）に示したように、金ワイヤのワイヤボンディングおよび引張破断により、半導体チップ２の電極端子配設面２ａの周囲領域Ｐおよび芯部領域Ｑ（図３）に金バンプ３Ａ，３Ｂを形成する。 Next, a manufacturing process of the mounting structure of FIG. 2 will be described with reference to FIGS.
First, as shown in FIG. 5A, the gold bump 3A is formed on the peripheral region P and the core region Q (FIG. 3) of the electrode terminal disposition surface 2a of the semiconductor chip 2 by wire bonding and tensile fracture of the gold wire. , 3B.

次に、金バンプ３Ａ，３Ｂの破断面ｃをレベラーにより加工して、図５（ｂ）のように平坦でほぼ同等の高さの頂面ｔに調整する。
これとは別に、図５（ｃ）に示したように、配線パターン４ｃが形成されている配線基板４の一方の面４ａの芯部領域（半導体チップ２が搭載されたときに半導体チップ２の芯部領域Ｑと対面する領域）に、エラストマー層６を印刷または貼着して、硬化処理し、エラストマー層６を半硬化状態にしておく。 Next, the fracture surface c of the gold bumps 3A and 3B is processed with a leveler to adjust the top surface t to a flat and substantially equal height as shown in FIG.
Apart from this, as shown in FIG. 5 (c), the core region of one surface 4a of the wiring substrate 4 on which the wiring pattern 4c is formed (when the semiconductor chip 2 is mounted, The elastomer layer 6 is printed or stuck on the core region Q) and cured, and the elastomer layer 6 is in a semi-cured state.

次に、図５（ｄ）に示したように、配線基板４の面４ａの芯部領域を取り囲む周囲領域（半導体チップ２が搭載されたときに半導体チップ２の周囲領域Ｐと対面する領域）に、テープ状の異方導電性樹脂シートの貼着等により接着剤層５を形成する。
次に、図５（ｅ）に示したように、図５（ｄ）の配線基板４上に図５（ｂ）の半導体チップ２を接合する。すなわち、図５（ｂ）のように金スタッドバンプ３Ａ，３Ｂを形成した半導体チップ２を、その面２ａを配線基板４の面４ａと向き合わせて（図５（ｂ）の姿勢に対して裏返して）、接着剤層５およびエラストマー層６の上に載置する。これにより、半導体チップ２の周囲領域Ｐの電極端子３Ａおよび芯部領域Ｑの電極端子３Ｂは、配線基板４上の接着剤層５およびエラストマー層６内にそれぞれ進入した状態になる。この状態で加熱・加圧することにより、接着剤層５およびエラストマー層６が硬化・収縮し、半導体チップ２の金スタッドバンプ３Ａ，３Ｂと配線基板４の配線パターン４ｃとが機械的に押し付けられて電気的に接続される。 Next, as shown in FIG. 5D, a surrounding area surrounding the core area of the surface 4a of the wiring board 4 (area facing the surrounding area P of the semiconductor chip 2 when the semiconductor chip 2 is mounted). In addition, the adhesive layer 5 is formed by sticking a tape-like anisotropic conductive resin sheet or the like.
Next, as shown in FIG. 5E, the semiconductor chip 2 shown in FIG. 5B is bonded onto the wiring substrate 4 shown in FIG. That is, the semiconductor chip 2 on which the gold stud bumps 3A and 3B are formed as shown in FIG. 5B is turned upside down with respect to the posture of FIG. 5B with the surface 2a facing the surface 4a of the wiring board 4. A), and placed on the adhesive layer 5 and the elastomer layer 6. As a result, the electrode terminals 3A in the peripheral region P of the semiconductor chip 2 and the electrode terminals 3B in the core region Q enter the adhesive layer 5 and the elastomer layer 6 on the wiring substrate 4, respectively. By heating and pressing in this state, the adhesive layer 5 and the elastomer layer 6 are cured and contracted, and the gold stud bumps 3A and 3B of the semiconductor chip 2 and the wiring pattern 4c of the wiring board 4 are mechanically pressed. Electrically connected.

周囲領域の接着剤層５を異方導電性樹脂シートで形成し、かつ／または芯部領域のエラストマー層６を異方導電性樹脂で形成してあれば、上記の加圧により異方導電性樹脂シート内および／または異方導電性樹脂内の金属粒子同士が加圧方向に接続され、周囲領域内および／または芯部領域内にある金スタッドバンプ３Ａおよび／または３Ｂと配線パターン４ｃとの電気的接続の上で更に有利である。   If the adhesive layer 5 in the peripheral region is formed of an anisotropic conductive resin sheet and / or if the elastomer layer 6 in the core region is formed of an anisotropic conductive resin, the above-described pressurization causes anisotropic conductivity. Metal particles in the resin sheet and / or anisotropic conductive resin are connected in the pressurizing direction, and the gold stud bumps 3A and / or 3B and the wiring pattern 4c in the peripheral region and / or the core region are connected. It is further advantageous in terms of electrical connection.

芯部領域のエラストマー層６は、硬化後も弾力性を維持しているので、配線基板４と実装基板８との見掛け上の熱膨張差で生ずる熱応力を緩和できる。また、接着剤層５を異方導電性樹脂シートで形成してあれば、異方導電性樹脂シートの弾力性はエラストマー層６に比べれば低いが、熱応力の緩和に寄与できる。
次に、図５（ｆ）に示したように、配線基板４の他方の面４ｂ上に形成されているパッド（図示せず）上に、外部接続端子としてのはんだボール７を載置して加熱することにより、パッドにはんだボール７を接合すると、半導体装置１が完成する。配線基板４には厚さ方向に貫通するスルーホールの内壁にめっき層が形成してあり、これにより面４ｂ上のはんだボール７と面４ａ上の配線パターン４ｃとが電気的に接続し、更に配線パターン４ｃは金スタッドバンプ３Ａ，３Ｂを介して半導体チップ２と電気的に接続する。 Since the elastomer layer 6 in the core region maintains elasticity even after being cured, the thermal stress caused by the apparent thermal expansion difference between the wiring board 4 and the mounting board 8 can be relieved. Further, if the adhesive layer 5 is formed of an anisotropic conductive resin sheet, the elasticity of the anisotropic conductive resin sheet is lower than that of the elastomer layer 6 but can contribute to relaxation of thermal stress.
Next, as shown in FIG. 5 (f), solder balls 7 as external connection terminals are placed on pads (not shown) formed on the other surface 4 b of the wiring board 4. When the solder balls 7 are joined to the pads by heating, the semiconductor device 1 is completed. The wiring board 4 has a plating layer formed on the inner wall of the through hole penetrating in the thickness direction, whereby the solder balls 7 on the surface 4b and the wiring pattern 4c on the surface 4a are electrically connected, and further The wiring pattern 4c is electrically connected to the semiconductor chip 2 through the gold stud bumps 3A and 3B.

最後に、図５（ｆ）の半導体チップ１を図２のように実装基板８上に載置して加熱することにより、はんだボール７が実装基板８のランド８ａと接合され、半導体チップ２が実装基板８上に実装された実装構造が完成する。
半導体装置１を実装基板８上に実装するときに、配線基板４と実装基板８との見掛け上の熱膨張差により配線基板４に加わる熱応力は、半導体チップ２と配線基板４とを接合しているエラストマー層６の弾力性により緩和するので、はんだボール７の接合部の応力集中を緩和し、配線基板４のはんだボール７と実装基板８のランド８ａとの接合の信頼性が向上する。これは特に、半導体チップ２の高集積化に伴い配線基板４が大型化した場合には有利である。 Finally, the semiconductor chip 1 of FIG. 5F is placed on the mounting substrate 8 and heated as shown in FIG. 2, whereby the solder balls 7 are joined to the lands 8 a of the mounting substrate 8. A mounting structure mounted on the mounting substrate 8 is completed.
When the semiconductor device 1 is mounted on the mounting substrate 8, the thermal stress applied to the wiring substrate 4 due to the apparent thermal expansion difference between the wiring substrate 4 and the mounting substrate 8 joins the semiconductor chip 2 and the wiring substrate 4. Since the elasticity of the elastomer layer 6 is relaxed, stress concentration at the joint portion of the solder ball 7 is relaxed, and the reliability of the joint between the solder ball 7 of the wiring substrate 4 and the land 8a of the mounting substrate 8 is improved. This is particularly advantageous when the size of the wiring board 4 increases with the integration of the semiconductor chip 2.

エラストマー層６の弾力性により、半導体チップ２に作用する熱応力も緩和されるので、金スタッドバンプ３Ａ、３Ｂと配線パターン４ｃとの接続の信頼性も高まる。
スタッドバンプ３Ａ，３Ｂはワイヤボンディングにより形成されるので、特にＵＢＭ工程やめっき工程を必要とするめっきバンプに比べて、製造工程を簡略化でき、製造コスト上有利である。ただし、本発明はスタッドバンプに限定する必要はなく、図６（ａ）のように金めっきやはんだめっき等により柱状に形成しためっきバンプでもよいし、図６（ｂ）のようにはんだボールを接合して形成したボールバンプでもよい。 Due to the elasticity of the elastomer layer 6, the thermal stress acting on the semiconductor chip 2 is also alleviated, so that the reliability of the connection between the gold stud bumps 3A and 3B and the wiring pattern 4c is enhanced.
Since the stud bumps 3A and 3B are formed by wire bonding, the manufacturing process can be simplified and the manufacturing cost is advantageous as compared with the plating bump that particularly requires the UBM process and the plating process. However, the present invention need not be limited to stud bumps, and may be plated bumps formed in a columnar shape by gold plating or solder plating as shown in FIG. 6 (a), or solder balls as shown in FIG. 6 (b). A ball bump formed by bonding may be used.

接着剤層５による接合領域とエラストマー層６による接合領域は、前出の図４（ａ）のように周囲領域Ｐ（５）と芯部領域Ｑ（６）という組み合わせに限定する必要はなく、逆に図４（ｂ）のようにエラストマー６による接合領域が周囲領域Ｐ（６）であり、接着剤層５による接合領域が芯部領域Ｑ（５）であってもよい。あるいは、図４（ｃ）のように接着剤層５による接合領域が対向する一対の側部帯域Ｒ（５）であり、エラストマー層６による接合領域が、側部帯域Ｒ（５）に挟まれた中央帯域Ｓ（６）であってもよい。逆に、図４（ｄ）のようにエラストマー層６による接合領域が対向する一対の側部帯域Ｒ（６）であり、接着剤層５による接合領域が、側部帯域Ｒ（６）に挟まれた中央帯域Ｓ（５）であってもよい。接合領域の組み合わせは、上記以外にも種々の変形が可能であり、半導体チップの種類によって適宜選択することができる。   The joining region by the adhesive layer 5 and the joining region by the elastomer layer 6 do not need to be limited to the combination of the surrounding region P (5) and the core region Q (6) as shown in FIG. Conversely, as shown in FIG. 4B, the joining region by the elastomer 6 may be the surrounding region P (6), and the joining region by the adhesive layer 5 may be the core region Q (5). Alternatively, as shown in FIG. 4 (c), a pair of side zones R (5) where the bonding regions by the adhesive layer 5 are opposed to each other, and the bonding regions by the elastomer layer 6 are sandwiched between the side zones R (5). Alternatively, the central band S (6) may be used. On the contrary, as shown in FIG. 4 (d), there are a pair of side zones R (6) in which the bonding regions by the elastomer layer 6 face each other, and the bonding regions by the adhesive layer 5 are sandwiched between the side zones R (6). The central band S (5) may be used. The combination of the bonding regions can be variously modified in addition to the above, and can be appropriately selected depending on the type of the semiconductor chip.

この実施例では、配線基板４上に接着剤層５およびエラストマー層６を両方形成した後に半導体チップ２を搭載する手順を説明したが、他の手順も可能である。すなわち、内側の領域（例えば芯部領域、中央帯域）に接着剤層５またはエラストマー層６の一方のみを形成し、半導体チップ２を搭載し、その後、外側の領域（例えば周囲領域、側部帯域）の半導体チップ２と配線基板４との間の空隙に他方の層をディスペンサー等により充填して封止してもよい。   In this embodiment, the procedure for mounting the semiconductor chip 2 after forming both the adhesive layer 5 and the elastomer layer 6 on the wiring substrate 4 has been described, but other procedures are also possible. That is, only one of the adhesive layer 5 or the elastomer layer 6 is formed in the inner region (for example, the core region, the central band), the semiconductor chip 2 is mounted, and then the outer region (for example, the surrounding region, the side band). The other layer may be filled with a dispenser or the like in the gap between the semiconductor chip 2 and the wiring board 4).

例えば、配線基板４の芯部領域Ｑにエラストマー層６を形成し、その上に半導体チップ２を載置し、半導体チップ２の芯部領域Ｑの電極端子３Ｂを、配線基板４上のエラストマー層６内に進入した状態にする。その後、エラストマー層６の周囲に接着剤層５としてエポキシ系樹脂等を充填して封止する。その後、この樹脂を硬化・収縮させることにより、周囲領域の電極端子３Ａおよび芯部領域の電極端子３Ｂが配線基板４の配線パターン４ｃに押し付けられて電気的に接続される。   For example, the elastomer layer 6 is formed in the core region Q of the wiring substrate 4, the semiconductor chip 2 is placed thereon, and the electrode terminals 3 B in the core region Q of the semiconductor chip 2 are connected to the elastomer layer on the wiring substrate 4. Go into 6 state. Thereafter, an epoxy resin or the like is filled as the adhesive layer 5 around the elastomer layer 6 and sealed. Thereafter, by hardening and shrinking the resin, the electrode terminal 3A in the peripheral region and the electrode terminal 3B in the core region are pressed against the wiring pattern 4c of the wiring substrate 4 to be electrically connected.

半導体装置はこの実施例に記載した構造に限定する必要はなく、例えば配線基板４の配線パターン４ｃに接続された金バンプ３の周囲を、光硬化性樹脂により封止してもよい。   The semiconductor device need not be limited to the structure described in this embodiment. For example, the periphery of the gold bump 3 connected to the wiring pattern 4c of the wiring board 4 may be sealed with a photocurable resin.

図１は、従来の半導体チップの実装構造を示す断面図である。FIG. 1 is a cross-sectional view showing a conventional semiconductor chip mounting structure. 図２は、本発明による半導体チップの実装構造を示す断面図である。FIG. 2 is a sectional view showing a semiconductor chip mounting structure according to the present invention. 図３は、本発明により半導体チップの電極端子配設面上の多数の電極端子を２つの群に区分した一例を示す平面図である。FIG. 3 is a plan view showing an example in which a large number of electrode terminals on the electrode terminal arrangement surface of the semiconductor chip are divided into two groups according to the present invention. 図４（ａ）〜図４（ｄ）は、本発明により半導体チップの電極端子配設面を接着剤層による接合領域とエラストマー層による接合領域に区分した種々の例を示す平面図である。4 (a) to 4 (d) are plan views showing various examples in which the electrode terminal arrangement surface of the semiconductor chip is divided into a bonding region by an adhesive layer and a bonding region by an elastomer layer according to the present invention. 図５（ａ）〜図５（ｆ）は、図２の実装構造を製造する工程の一例を示す断面図である。FIG. 5A to FIG. 5F are cross-sectional views showing an example of a process for manufacturing the mounting structure of FIG. 図６（ａ）および図６（ｂ）は、スタッドバンプ以外の電極端子の例を示す断面図である。6A and 6B are cross-sectional views showing examples of electrode terminals other than stud bumps.

符号の説明Explanation of symbols

１ 本発明によるＢＧＡタイプの半導体装置
２ 半導体チップ
２ａ 電極端子配設面
３Ａ スタッドバンプ（第１の電極端子群）
３Ｂ スタッドバンプ（第２の電極端子群）
４ 配線基板
４ｃ 配線パターン
５ 接着剤層
６ エラストマー層
７ はんだボール
８ 実装基板
Ｐ 周囲領域
Ｑ 芯部領域
Ｒ 側部帯域
Ｓ 中央帯域 DESCRIPTION OF SYMBOLS 1 BGA type semiconductor device by this invention 2 Semiconductor chip 2a Electrode terminal arrangement | positioning surface 3A Stud bump (1st electrode terminal group)
3B Stud bump (second electrode terminal group)
4 Wiring board 4c Wiring pattern 5 Adhesive layer 6 Elastomer layer 7 Solder ball 8 Mounting board P Peripheral area Q Core area R Side band S Central band

Claims (10)

配線基板上の配線パターンに半導体チップをフリップチップ接続により搭載した半導体チップの実装構造において、
前記半導体チップの電極端子配設面上に多数の電極端子が配設されており、
前記電極端子配設面は、周囲領域と該周囲領域に囲まれた芯部領域から成るかまたは１対の側部帯域と該１対の側部帯域に挟まれた中央帯域から成り、
該多数の電極端子のうち、前記周囲領域または前記芯部領域または前記一対の側部帯域または前記中央帯域にある第1の電極端子群は前記配線基板と前記半導体チップとの間に介在するエポキシ樹脂から成る接着剤層により前記配線パターンに機械的に係合され且つ電気的に接続され、前記電極端子配設面の前記第１の電極端子群のある領域もしくは帯域以外の領域もしくは帯域にある第２の電極端子群は前記配線基板と前記半導体チップとの間に介在する室温での弾性率が１００ＭＰａ以下のエラストマー層により前記配線パターンに機械的に係合され且つ電気的に接続されていることを特徴とする半導体チップの実装構造。 In a semiconductor chip mounting structure in which a semiconductor chip is mounted on a wiring pattern on a wiring board by flip chip connection,
A large number of electrode terminals are disposed on the electrode terminal disposition surface of the semiconductor chip,
The electrode terminal disposition surface is composed of a peripheral region and a core region surrounded by the peripheral region or a pair of side bands and a central band sandwiched between the pair of side bands,
Of the multiple electrode terminals, the first electrode terminal group in the peripheral region, the core region, the pair of side bands, or the central band is an epoxy interposed between the wiring board and the semiconductor chip. It is mechanically engaged with and electrically connected to the wiring pattern by an adhesive layer made of resin, and is in a region or a band other than a region or a band of the first electrode terminal group on the electrode terminal arrangement surface. The second electrode terminal group is mechanically engaged with and electrically connected to the wiring pattern by an elastomer layer having a modulus of elasticity at room temperature of 100 MPa or less interposed between the wiring substrate and the semiconductor chip. A semiconductor chip mounting structure. 前記半導体チップの電極端子配設面は、周囲領域と、該周囲領域に囲まれた芯部領域とから成り、該周囲領域には前記第１の電極端子群が配設され、該芯部領域には前記第２の電極端子群が配設されていることを特徴とする請求項１記載の半導体チップの実装構造。   The electrode terminal disposition surface of the semiconductor chip includes a peripheral region and a core region surrounded by the peripheral region, and the first electrode terminal group is disposed in the peripheral region, and the core region 2. The semiconductor chip mounting structure according to claim 1, wherein the second electrode terminal group is disposed on the semiconductor chip. 前記半導体チップの電極端子配設面は、周囲領域と、該周囲領域に囲まれた芯部領域とから成り、該周囲領域には前記第２の電極端子群が配設され、該芯部領域には前記第１の電極端子群が配設されていることを特徴とする請求項１記載の半導体チップの実装構造。   The electrode terminal disposition surface of the semiconductor chip includes a peripheral region and a core region surrounded by the peripheral region, and the second electrode terminal group is disposed in the peripheral region, and the core region 2. The semiconductor chip mounting structure according to claim 1, wherein the first electrode terminal group is disposed on the semiconductor chip. 前記半導体チップの電極端子配設面は、対向する一対の側部帯域と、該一対の側部領域に挟まれた中央帯域とから成り、該側部帯域には前記第１の電極端子群が配設され、該中央帯域には前記第２の電極端子群が配設されていることを特徴とする請求項１記載の半導体チップの実装構造。   The electrode terminal mounting surface of the semiconductor chip is composed of a pair of opposing side bands and a central band sandwiched between the pair of side areas, and the first electrode terminal group is located in the side band. 2. The semiconductor chip mounting structure according to claim 1, wherein the second electrode terminal group is disposed in the central band. 前記半導体チップの電極端子配設面は、対向する一対の側部帯域と、該一対の側部領域に挟まれた中央帯域とから成り、該側部帯域には前記第２の電極端子群が配設され、該中央帯域には前記第１の電極端子群が配設されていることを特徴とする請求項１記載の半導体チップの実装構造。   The electrode terminal mounting surface of the semiconductor chip is composed of a pair of opposing side bands and a central band sandwiched between the pair of side areas, and the second electrode terminal group is formed in the side band. 2. The semiconductor chip mounting structure according to claim 1, wherein the first electrode terminal group is disposed in the central band. 前記接着剤層は、異方導電性接着剤の塗布または異方導電性樹脂シートの貼着により形成されていることを特徴とする請求項１記載の半導体チップの実装構造。   2. The semiconductor chip mounting structure according to claim 1, wherein the adhesive layer is formed by applying an anisotropic conductive adhesive or sticking an anisotropic conductive resin sheet. 前記接着剤層は、絶縁性樹脂から成ることを特徴とする請求項１記載の半導体チップの実装構造。   2. The semiconductor chip mounting structure according to claim 1, wherein the adhesive layer is made of an insulating resin. 前記エラストマー層は、接着性を有する絶縁性樹脂から成ることを特徴とする請求項１記載の半導体チップの実装構造。   2. The semiconductor chip mounting structure according to claim 1, wherein the elastomer layer is made of an insulating resin having adhesiveness. 前記エラストマー層は、接着性を有する異方導電性樹脂の塗布または異方導電性樹脂シートの貼着により形成されていることを特徴とする請求項１記載の半導体チップの実装構造。   2. The semiconductor chip mounting structure according to claim 1, wherein the elastomer layer is formed by applying an anisotropic conductive resin having adhesiveness or sticking an anisotropic conductive resin sheet. 前記配線基板の一方の面に形成された前記配線パターンに前記半導体チップがフリップチップ接続により搭載されており、前記基板の他方の面に、前記配線パターンに電気的に接続された外部接続端子が形成されていることを特徴とする請求項１から９までのいずれか１項記載の半導体チップの実装構造。   The semiconductor chip is mounted on the wiring pattern formed on one surface of the wiring board by flip chip connection, and external connection terminals electrically connected to the wiring pattern are provided on the other surface of the substrate. 10. The semiconductor chip mounting structure according to claim 1, wherein the semiconductor chip mounting structure is formed.
JP2007187328A 1998-04-07 2007-07-18 Semiconductor chip mounting structure Expired - Fee Related JP4342577B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007187328A JP4342577B2 (en) 1998-04-07 2007-07-18 Semiconductor chip mounting structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9489598 1998-04-07
JP2007187328A JP4342577B2 (en) 1998-04-07 2007-07-18 Semiconductor chip mounting structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP08899599A Division JP4030220B2 (en) 1998-04-07 1999-03-30 Semiconductor chip mounting structure

Publications (2)

Publication Number Publication Date
JP2007266644A JP2007266644A (en) 2007-10-11
JP4342577B2 true JP4342577B2 (en) 2009-10-14

Family

ID=38639264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007187328A Expired - Fee Related JP4342577B2 (en) 1998-04-07 2007-07-18 Semiconductor chip mounting structure

Country Status (1)

Country Link
JP (1) JP4342577B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009105320A (en) * 2007-10-25 2009-05-14 Seiko Epson Corp Mounting structure of electronic component and manufacturing method thereof

Also Published As

Publication number Publication date
JP2007266644A (en) 2007-10-11

Similar Documents

Publication Publication Date Title
US6744122B1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
US6621172B2 (en) Semiconductor device and method of fabricating the same, circuit board, and electronic equipment
US5627405A (en) Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer
JP3633559B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US6081038A (en) Semiconductor chip package structure
US6593648B2 (en) Semiconductor device and method of making the same, circuit board and electronic equipment
JP3502776B2 (en) Metal foil with bump, circuit board, and semiconductor device using the same
JP3838331B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
KR100698527B1 (en) Chip stack package having pillar bump using metal bump and manufacturing method thereof
US6720644B2 (en) Semiconductor device using interposer substrate and manufacturing method therefor
JP2000138313A (en) Semiconductor device and its manufacture
JP2000269369A (en) Semiconductor device
JP3565090B2 (en) Method for manufacturing semiconductor device
US6528889B1 (en) Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
JP2000277649A (en) Semiconductor and manufacture of the same
JP4030220B2 (en) Semiconductor chip mounting structure
JP4342577B2 (en) Semiconductor chip mounting structure
JP3582513B2 (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
WO2017043480A1 (en) Semiconductor package
JP2002289735A (en) Semiconductor device
JP4085572B2 (en) Semiconductor device and manufacturing method thereof
JPH08330356A (en) Anisotropic conductive sheet with conductive layer and wiring board using the sheet
JP3320699B2 (en) Semiconductor device and package of semiconductor device
JP3337922B2 (en) Semiconductor device and manufacturing method thereof
JP3912888B2 (en) Package type semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070718

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090609

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090707

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120717

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120717

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130717

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees