JP2005340588A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize the wiring of a narrow pitch without giving a damage to a solder connecting part to a mother circuit board due to a thermal expansion difference of a mold sealing resin and a substrate. <P>SOLUTION: A laminated semiconductor device includes a substrate 3 having a wiring layer and the solder connecting part 12 provided on a lower surface, and at least two or more semiconductor elements including a first semiconductor element 8 and a second semiconductor element 6 laminated on the substrate 3. The semiconductor device further includes a wiring film 14 having at least two or more layers of wiring conductors 17-b, 17-c. The first semiconductor element 8 is connected to the wiring conductor 17-c of the wiring film 14. The second semiconductor element 6 is connected to another wiring conductor 17-b at the opposite side of the wiring film surface connected with the first semiconductor element 8. Furthermore, the wiring conductor 17-b, 17-c are connected to the substrate 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  TECHNICAL FIELD The present invention relates to a method for stacking and packaging semiconductor elements that enables a higher density circuit with a large number of wiring connections, and in particular, facilitates high functionality and downsizing of information communication equipment, office electronic equipment, and the like. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which semiconductor elements to be stacked are stacked, and a semiconductor device having a package configuration that stably secures electrical connection reliability of a semiconductor element by resin sealing that protects an integrated circuit portion of the semiconductor element, and a manufacturing method thereof Is.

  Conventionally, a semiconductor element is manufactured based on a silicon material, and electrode terminal pads are formed on the surface with a fine pitch. The semiconductor element is mounted on a lead frame or a multi-layered interposer substrate. Then, the electrode terminal pads are electrically connected to a wiring land portion on a lead frame or an interposer substrate (hereinafter referred to as a substrate). As a method for this purpose, a wire bonding (hereinafter referred to as WB) method using a gold thin wire or a method in which a gold bump is formed on an electrode pad, and this gold bump and a wiring land portion are directly called a flip chip (hereinafter referred to as FC) bonding. Is used.

  In the case of the WB method for fixing the chip, the chip and the lead frame are connected by an adhesive paste or an adhesive tape. In the case of the FC method, the chip and the interposer substrate are sealed and fixed with an underfill material. Finally, the chip, the entire lead frame, and the chip on the substrate are covered with a sealing resin such as a thermosetting epoxy resin and solidified. This protects the gold wire, the chip, and the connecting portion when the WB method is used.

  In recent years, a stacked semiconductor device in which a plurality of semiconductor elements having a plurality of functions are mounted on a substrate on which circuit wiring is formed (interposer substrate) has been developed. Such a package type semiconductor device has a new structure problem.

  Hereinafter, a conventional stacked semiconductor device and a manufacturing method thereof will be described with reference to the drawings.

  FIG. 11 shows a cross-sectional structure of a package form of a conventional semiconductor device. 1 is a semiconductor element chip (hereinafter referred to as a semiconductor element), 2 is a bump electrode, 3 is a substrate, 4 is a wiring electrode on the substrate, 5 is an FC underfill resin, 6 is a middle semiconductor element (chip), 7 Is an adhesive layer, 8 is an upper semiconductor element, 9 is an adhesive layer, 10 is a bonding wire, 11 is a bonding wire, 12 is a solder ball electrode terminal, and 13 is a mold sealing resin.

  The semiconductor device shown in FIG. 11 is an example of a package structure in which three chips are stacked in a stacked configuration of a plurality of chips realizing a low-cost and high-density circuit. In this example, a bump electrode 2 is formed on the bottom surface of the semiconductor element 1. The wiring electrode 4 and the bump electrode 2 installed on the surface of the substrate facing the substrate 3 are connected to the substrate wiring 4 via the FC underfill resin 5.

  Further, the middle semiconductor element 6 is bonded onto the semiconductor element 1 via the adhesive layer 7, and the electrodes are bonded with the wiring surface facing upward, and are connected to the wiring electrodes 4 of the substrate 3 by bonding wires 11, which are gold thin wires. ing. Further, the upper semiconductor element 8 is also bonded to the semiconductor element 6 via the adhesive layer 7 with the wiring surface facing upward, and the wiring electrode 4 of the substrate 3 is bonded to the bonding wire 11 which is a gold thin wire. It is connected.

  Here, the semiconductor element mounted on the wiring board 3 is a semiconductor element having a plurality of functions such as a logic circuit element and a memory element, and realizes one highly functional semiconductor device.

  Next, a conventional method for manufacturing a semiconductor device will be described with reference to the drawings.

  FIG. 13 is a main cross-sectional view showing a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 13A, the bump electrode 2 is provided on the wiring surface of the semiconductor element 1. This is formed by a plating method or a wire bonding method. The semiconductor element 1 on which the bump electrode 2 is formed is placed opposite to the substrate 3, the wiring electrode 4-a and the bump electrode 2 on the surface of the substrate are placed through the FC underfill resin 5, and the lower chip is flip-chiped. Connect to the interposer board wiring.

  Subsequently, as shown in FIG. 13 (b), the middle semiconductor element 6 is bonded onto the semiconductor element 1 via the adhesive layer 7. Similarly, as shown in FIG. 13C, the upper semiconductor element 8 is bonded onto the semiconductor element 6 via the adhesive layer 9.

  Further, as shown in FIG. 13 (d), the middle semiconductor element 6 and the upper semiconductor element 8 are electrically connected to the wiring electrodes 4-c and 4-d on the substrate 3 by wire bonding. It is.

Finally, as shown in FIG. 13E, the semiconductor element group on the substrate 3 and the exposed gold bonding wire of the wire bonding method are sealed with a mold sealing resin 13 in order to protect and insulate. After these semiconductor elements are mounted on the substrate 3, the semiconductor element group is sealed on the interposer substrate 3 by a transfer molding method or the like using a mold sealing resin 13 made of a component such as an epoxy resin. This sealing portion has a function of protecting the semiconductor element from the influence from the outside. After that, a solder ball electrode terminal 12 is provided for solder mounting on the circuit board of the electronic device on the bottom surface of the substrate. A semiconductor device is manufactured.

  Conventionally, a stacked package type semiconductor device in which three semiconductor elements are mounted on a wiring board has been realized by the processes described above.

Regarding a method related to a conventional wiring portion, there is also a proposal of a technique using film wiring. For example, Patent Document 1 discloses that in a stacked semiconductor device, one film wiring is used for each semiconductor element and flip chip connection is performed. A structure for sealing the whole has been proposed. In this case, film wiring is used for each chip.
Japanese Patent Laid-Open No. 2002-289766

  However, in the structure of the above-described semiconductor device that has been increasing in recent years in the conventional semiconductor device, as a first problem, due to the stress caused by the difference in thermal expansion between the substrate and the mold sealing resin, the circuit board of the electronic device There is a problem that the solder ball joint is broken.

  In the case of the structure of only one semiconductor element, the total thickness of the semiconductor element chip made of hard silicon (Si) with low thermal expansion is small, the thickness of the mold sealing resin layer is small, and the first lowermost surface is the first. Since the mold resin is not required when the chip is mounted on the FC, the warpage deformation of the semiconductor device caused by the difference in thermal expansion between the mold resin and the substrate is small due to the temperature change. As a result, the stress generated at the solder joint on the bottom surface of the substrate Was not a problem.

  However, in the case of the structure of the semiconductor device as shown in FIG. 11, a mold sealing resin and a substrate, which are different materials, exist with a semiconductor element interposed therebetween. Due to this asymmetric structure, warpage deformation of the entire semiconductor device occurs due to a difference in thermal expansion. As the number of semiconductor elements increases. The total thickness of the semiconductor element and the thickness of the mold resin also increase, and as a result, the stress for peeling off the substrate and the solder joint is increased. Therefore, cracks are likely to occur at the outer peripheral solder portion. Furthermore, cracks further develop due to repeated stress due to temperature fluctuations, etc., leading to the final fracture.

  This is a problem that appears particularly conspicuous when the substrate material is particularly hard and is made of a ceramic substrate material having a low thermal expansion coefficient. As a result of the numerical analysis, when the presence or absence of the mold resin and the stress value of the solder joint portion are viewed as shown in FIG. 12, it is confirmed that the stress generated in the solder portion is reduced by decreasing the mold resin.

  In addition, as a second problem, in recent years, the number of electrodes (number of pins) of semiconductor elements has increased, and there has been a tendency toward high-density circuits and narrow pitches. The number of wire bondings that are connected to each other is increasing, and a narrow pitch is required. However, in the wire bonding method, when the pitch is narrow, it is difficult to prevent contact between adjacent gold wires, and there is a concern about the occurrence of a short circuit due to impurities in the sealing resin. Further, there is a problem that the resin flow injecting property is deteriorated, and it is difficult to form a sandwich pitch.

  Further, the method using one film wiring for each semiconductor element has a problem that the material is expensive and the process time is increased. Here, a sealing resin that reduces the filler content, increases the resin component, and improves the resin fluidity is used. As a result of increasing the resin component, the thermal expansion coefficient of the material increases, and the first The stress of the solder joint which is a problem is greatly increased.

  As described above, the conventional stacked semiconductor device has the first problem that the reliability is lowered due to the destruction of the solder joint and the second problem that it is difficult to reduce the pitch.

  Accordingly, an object of the present invention is to solve the above-described conventional problems, and in a stacked semiconductor device in which two or more semiconductor elements are mounted in three dimensions, when a thermal shock is applied during mounting, mold sealing is performed. Due to the difference in thermal expansion between the resin and the substrate, there is no damage to the solder joints to the mother circuit board, the reliability of the solder joints is ensured, and the multilayer semiconductor device that realizes narrow pitch wiring and its It is to provide a manufacturing method.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a substrate having a wiring layer and having a solder joint portion provided on a lower surface thereof, laminated on the substrate, and a first semiconductor element and A stacked semiconductor device comprising at least two or more semiconductor elements including a second semiconductor element, wherein the first semiconductor element has a wiring film in which at least two or more wiring conductors are formed. The second semiconductor element is connected to another wiring conductor on the opposite side of the wiring film surface to which the first semiconductor element is connected, and the wiring is connected to the wiring conductor of the wiring film. A conductor is connected to the substrate.

  A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the wiring film has at least two or more layers of wiring conductors on both front and back surfaces.

  According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the wiring conductor of the wiring film is covered with a film that insulates and protects between the wiring conductors except for the electrode surface.

  According to a fourth aspect of the present invention, in the semiconductor device according to the first, second, or third aspect, only the vicinity of the electrical connection portion between the semiconductor element, the wiring film, and the substrate is sealed with resin.

  The semiconductor device according to claim 5 is the semiconductor device according to claim 1, wherein the semiconductor device has a wiring portion that is electrically connected from each layer of the wiring conductor to the film surface, and an electrode surface from the wiring conductor is exposed on a connection surface side with the substrate. doing.

  The semiconductor device according to claim 6 is the semiconductor device according to claim 1, wherein the protruding electrode portion for connecting to the electrode of the semiconductor element or the wiring electrode on the substrate is an electrode surface on the surface of the wiring conductor of the wiring film. Provided.

  The semiconductor device according to claim 7 is the semiconductor device according to claim 1, wherein the protruding electrode portion for connecting to the wiring conductor of the wiring film is on the electrode surface of the semiconductor element or the wiring electrode surface on the substrate. Provided.

  The semiconductor device according to claim 8 is the semiconductor device according to claim 1, further comprising a wiring film unit in which semiconductor elements are mounted one on each side of the wiring film, and the wiring film unit is electrically connected to the substrate. It is connected.

  A semiconductor device according to a ninth aspect is the semiconductor device according to the eighth aspect, wherein one or more semiconductor elements are mounted on the substrate, and the wiring film unit is installed on the upper part of the semiconductor element.

  The semiconductor device according to claim 10 is the semiconductor device according to claim 8 or 9, wherein the semiconductor device has two or more of the wiring film units.

  A semiconductor device according to an eleventh aspect is the semiconductor device according to the first aspect, wherein the substrate having the wiring layer is made of a ceramic having a conductor wiring.

  According to a twelfth aspect of the present invention, in the semiconductor device according to the first aspect, the upper surface region of the substrate is entirely sealed with a sealing resin.

  A semiconductor device according to a thirteenth aspect is the semiconductor device according to the first aspect, wherein the substrate having a wiring layer is a metal lead frame.

  A semiconductor device according to a fourteenth aspect is the semiconductor device according to the thirteenth aspect, wherein each of the upper and lower surfaces of the lead frame has at least one wiring film on which the semiconductor element is mounted.

  According to a fifteenth aspect of the present invention, in the semiconductor device according to the thirteenth or fourteenth aspect, the upper and lower regions of the lead frame are all sealed with a sealing resin.

  The method for manufacturing a semiconductor device according to claim 16, comprising: preparing a wiring film in which at least two layers of wiring conductors are formed; and connecting the first semiconductor element to the wiring conductor of the wiring film; A second step of connecting the second semiconductor element to another wiring conductor of the wiring film on the opposite side of the wiring film surface to which the first semiconductor element is connected; and a wiring conductor of the wiring film. A third step of connecting to the substrate and a fourth step of resin-sealing the vicinity of the connecting portion with the substrate are included.

  The method for manufacturing a semiconductor device according to claim 17, comprising preparing a wiring film on which at least two or more layers of wiring conductors are formed, and connecting a first semiconductor element to the wiring conductors of the wiring film; A second step of connecting the second semiconductor element to another wiring conductor of the wiring film on the opposite side of the wiring film surface to which the first semiconductor element is connected, and a protruding electrode portion is formed on the surface A third step of flip-chip connecting the third semiconductor element thus formed to a substrate through a resin, and a wiring conductor of the wiring film on which the first and second semiconductor elements are mounted, A fourth step of connecting to the substrate on which the semiconductor element is placed and a fifth step of resin sealing the vicinity of the connecting portion with the substrate.

  A method for manufacturing a semiconductor device according to claim 18 is the method for manufacturing a semiconductor device according to claim 17, wherein the first and second steps are repeated at least twice to mount the first and second semiconductor elements. A plurality of wiring conductors of the wiring film are connected to a substrate on which the third semiconductor element is mounted.

  According to the semiconductor device of the first aspect of the present invention, it has a wiring film in which at least two layers of wiring conductors are formed, the first semiconductor element is connected to the wiring conductor of the wiring film, Since the semiconductor element is connected to another wiring conductor on the opposite side of the wiring film surface to which the first semiconductor element is connected, and the wiring conductor is connected to the substrate, the entire semiconductor device or the entire upper surface is sealed. A semiconductor device can be configured without the need to do so. For this reason, with regard to the reliability improvement of the solder joint, which is the first problem, when a thermal load is applied, such as during mounting or a temperature cycle test, the semiconductor device is affected by the difference in thermal expansion between the mold sealing resin and the substrate. The thermal stress applied to the solder joint to the mother circuit board of the electronic device due to warp deformation can be largely eliminated. This effect becomes remarkable because the stress generated when the substrate is made of ceramic or the like has high rigidity and the difference in thermal expansion from the mold resin is large.

  Further, with respect to the narrowing of the pitch, which is the second problem, it is possible to realize the wiring pitch for mounting the semiconductor element on the semiconductor device at a low cost within a range of 0 to 50 μm, which is difficult with the conventional wire bonding method. I can do it. As a result, it is possible to provide a stacked area array type semiconductor device with improved solder joint reliability while realizing further narrow pitches at low cost.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, it is desirable that the wiring film has at least two layers of wiring conductors formed on both front and back surfaces.

  In Claim 3, since the wiring conductor of a wiring film is covered with the film | membrane which carries out insulation protection between wiring conductors except an electrode surface, it can insulate between wiring conductors.

  According to a fourth aspect of the present invention, in the semiconductor device according to the first, second, or third aspect, it is desirable that only the vicinity of the electrical connection portion between the semiconductor element, the wiring film, and the substrate is sealed with a resin. The thickness of the resin is small, and the warp deformation of the semiconductor device caused by the difference in thermal expansion between the resin and the substrate can be reduced.

  According to a fifth aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, the semiconductor device has a wiring portion that is electrically connected from each layer of the wiring conductor to the film surface, and an electrode surface from the wiring conductor is exposed on a connection surface side with the substrate desirable. The electrode surface of the wiring film can be connected to the substrate.

  According to a sixth aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, it is desirable that the protruding electrode portion for connecting to the electrode of the semiconductor element or the wiring electrode on the substrate is provided on the electrode surface of the wiring conductor surface of the wiring film.

  According to a seventh aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, it is desirable that the protruding electrode portion for connecting to the wiring conductor of the wiring film is provided on the electrode surface of the semiconductor element or the wiring electrode surface on the substrate.

  According to the eighth aspect of the present invention, the wiring film unit includes a wiring film unit in which one semiconductor element is mounted on each side of the wiring film, and the wiring film unit is electrically connected to the substrate. can do.

  According to a ninth aspect of the present invention, in the semiconductor device according to the eighth aspect of the present invention, it is desirable that one or more semiconductor elements are mounted on the substrate, and a wiring film unit is installed on the semiconductor element. As a result, a stacked semiconductor device in which two or more semiconductor elements are three-dimensionally mounted can be configured.

  According to a tenth aspect of the present invention, in the semiconductor device according to the eighth or ninth aspect, it is desirable to have two or more wiring film units.

  According to the eleventh aspect, since the substrate having the wiring layer is made of ceramic having conductor wiring, the thermal expansion coefficient is small, and the semiconductor device is likely to be warped and deformed due to the difference in thermal expansion with the mold resin, which is effective.

  According to a twelfth aspect of the present invention, in the semiconductor device according to the first aspect, it is desirable that the upper surface region of the substrate is entirely sealed with a sealing resin.

  According to a thirteenth aspect of the present invention, in the semiconductor device according to the first aspect, the substrate having the wiring layer is preferably a metal lead frame. The present invention can also be applied to a semiconductor device using a lead frame material as a substrate.

  According to a fourteenth aspect of the present invention, in the semiconductor device according to the thirteenth aspect, it is preferable that at least one wiring film on which the semiconductor element is mounted is provided on each of upper and lower surfaces of the lead frame.

  According to a fifteenth aspect of the present invention, in the semiconductor device according to the thirteenth or fourteenth aspect, it is desirable that the upper and lower regions of the lead frame are all sealed with a sealing resin.

  According to the semiconductor device manufacturing method of the sixteenth aspect of the present invention, a wiring film on which at least two layers of wiring conductors are formed is prepared, and the first semiconductor element is connected to the wiring conductor of the wiring film. 1 step, a second step of connecting the second semiconductor element to another wiring conductor of the wiring film on the opposite side of the wiring film surface to which the first semiconductor element is connected, and a wiring conductor of the wiring film A third step of connecting the substrate to the substrate and a fourth step of resin-sealing the vicinity of the connecting portion with the substrate, so that the entire semiconductor device or the entire upper surface is sealed in a configuration in which semiconductor elements are stacked in two stages. A semiconductor device can be configured without the need to do so. Therefore, when a thermal load is applied during mounting or temperature cycle testing, the semiconductor device warps and deforms due to the difference in thermal expansion between the mold sealing resin and the substrate, and the solder joint to the mother circuit board of the electronic device The thermal stress applied to can be greatly eliminated. In addition, the wiring pitch for mounting the semiconductor element on the semiconductor device can be realized at a low cost with a wiring pitch in the range of 0 to 50 μm, which was difficult with the conventional wire bonding method.

  According to the method for manufacturing a semiconductor device according to claim 17 of the present invention, there is provided a wiring film in which at least two layers of wiring conductors are formed, and the first semiconductor element is connected to the wiring conductor of the wiring film. 1 step, a second step of connecting the second semiconductor element to another wiring conductor of the wiring film on the opposite side of the wiring film surface to which the first semiconductor element is connected, and a protruding electrode portion on the surface A third step of flip-chip connecting the third semiconductor element formed with the substrate to the substrate via a resin, and the wiring conductor of the wiring film on which the first and second semiconductor elements are mounted as the third semiconductor Since the fourth step of connecting to the substrate on which the element is mounted and the fifth step of resin-sealing the vicinity of the connection portion with the substrate are included, the entire semiconductor device or the entire upper surface is formed in a configuration in which the semiconductor elements are stacked in three stages. No need to seal It can constitute a semiconductor device. Therefore, when a thermal load is applied during mounting or temperature cycle testing, the semiconductor device warps and deforms due to the difference in thermal expansion between the mold sealing resin and the substrate, and the solder joint to the mother circuit board of the electronic device The thermal stress applied to can be greatly eliminated. In addition, the wiring pitch for mounting the semiconductor element on the semiconductor device can be realized at a low cost with a wiring pitch in the range of 0 to 50 μm, which was difficult with the conventional wire bonding method.

  In claim 18, the first and second steps are repeated at least twice, and the wiring conductors of the plurality of wiring films on which the first and second semiconductor elements are mounted are placed on the substrate on which the third semiconductor element is mounted. Since the connection is made, the above-described effect can be obtained in a configuration in which semiconductor elements are stacked in a plurality of stages.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 shows a cross-sectional structure of the wiring film in the embodiment of the present invention. FIG. 2A is a cross-sectional view of the entire film in the wiring direction, and FIG.

  1 and 2, 1 is a chip (third semiconductor element) which is a semiconductor element, 6 is a chip which is a middle semiconductor element (second semiconductor element), and 8 is a chip which is an upper semiconductor element (second semiconductor element). 1 semiconductor device).

  2 is a bump electrode, 3 is an interposer substrate, 4 is a chip mounting wiring land on the substrate, 4-a is a wiring electrode on the substrate for the third semiconductor element, and 4-b is a wiring on the substrate for the second semiconductor element. Electrode, 4-c is a wiring electrode on the substrate for the first semiconductor element, 5 is an underfill resin for FC section, 6-b is a bump electrode of the second semiconductor element, 7 is an adhesive layer, and 8-b is the first 1 is a bump electrode of a semiconductor element, 12 is a solder ball electrode terminal (solder joint), 14 is a wiring film, 15 is a sealing resin for FC section, 16 is a sealing resin for FC section, 17-c is a wiring conductor, 17-b is a wiring conductor, 18 is a film substrate, 19 is an insulating resin, 20 is a joint, and 23 is a wiring conductor post.

  As shown in FIG. 1, at least one semiconductor element 1 having a circuit wiring layer is mounted on a substrate 3 having a wiring layer connected to the semiconductor element, and is bonded to each other by an underfill resin 5. ing. The semiconductor element 1 and the wiring land 4 of the substrate 3 are connected by a bump electrode 2 made of gold or solder. Furthermore, on the back surface of the semiconductor element 1, the second-stage semiconductor element 6 is bonded to the back surface by an adhesive layer 7.

  The second-stage semiconductor element 6 has a bump electrode 6-b on the surface with the wiring layer, and is installed upward. The bump electrode 6-b is connected to the electrode portion 21-b of the wiring film 14 via the FC portion sealing resin 15 as shown in FIG. The electrode portion 21-b is connected to a wiring conductor 17-b installed in the wiring film 14.

  Further, the third-stage semiconductor element 8 has a bump electrode 8-b on the surface with the wiring layer, and is placed downward. The bump electrode 8-b is connected to the electrode part 21-c of the wiring film 14 through the FC part sealing resin 16 as shown in FIG. The electrode part 21-c is connected to the wiring conductor 17-c installed in the wiring film.

  In the wiring film 14, two layers of wiring conductors 17-b and 17-c are arranged on both surfaces as described above. The wiring conductor 17-c on the upper surface is connected to the wiring electrodes 4-b and 4-c on the substrate at the end face of the wiring film. The joint 20 is connected by a solder connection method or a Sn-plating and gold-tin bonding method using a gold bump electrode. Only the vicinity of the connection is sealed with the resin sealing material 25. Bonding may be performed by an anisotropic conductive film adhesion method, a bump pressure welding method (NSD method) by heat shrinkage of a non-conductive film, or the like.

  The protruding electrode portion for connecting to the wiring conductor of the wiring film is provided on the electrode surface of the semiconductor element or the wiring electrode surface on the substrate, but the electrode of the semiconductor element or the wiring electrode on the substrate is used. The structure in which the protruding electrode portion for connecting to the electrode surface on the surface of the wiring conductor of the wiring film may be provided.

  Here, details of the wiring film will be described with reference to FIG.

  That is, as shown in FIG. 2, the wiring film 14 has wiring conductors 17-b and 17-c on both surfaces of the film base 18. For connection with a semiconductor element, a semiconductor element-side connection electrode surface 21 is provided on both sides of the film. Here, 21-c is an electrode surface (upper side), and 21-b is an electrode surface (lower side). Further, the surface of the wiring conductors 17-b and 17-c is covered with an insulating resin 19 in order to protect them from an electrical short circuit or an external environment. In addition, the wiring conductor post (wiring portion) 23 allows one wiring conductor 17-c to be electrically connected to the lower surface, and the substrate-side connection electrode surface 22 connected to the electrodes of the first and second semiconductor elements is formed on the lower surface of the wiring film. Exposed on the same side, an electrode surface 22-c (upper wiring) and an electrode surface 22-b (lower wiring) are formed. As a result, a plurality of wirings can be bonded together on the substrate to electrically form circuit wiring. That is, wiring coupling of a plurality of semiconductor elements was realized with a single wiring film. Further, plating 24 is applied to the surfaces of the electrode surfaces 21 and 22. Plating is not always necessary, but it has the effect of preventing the oxidation of copper electrodes, such as gold plating and Sn plating, and improving the bonding quality.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. 3, 4, and 5 show a cross-sectional structure of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  First, as shown in FIG. 3, the first semiconductor element 8 is mounted on the wiring film 14. In implementation, if possible, any one of the first and second semiconductor elements may be mounted first. As shown in FIG. 3A, the bump electrode 8- b is formed by a wire bond method, a plating machine method, or the like. Next, as shown in FIGS. 3B and 3C, the FC portion sealing resin 16 is formed on the wiring film 14, and the semiconductor element 8 is pressed against it. And by heating (for example, to 150 degreeC), resin is softened and the semiconductor element 8 and the wiring film 14 are adhere | attached. When the temperature of the sealing resin 16 for the FC portion drops to normal temperature, the bump electrode 8-b on the surface of the semiconductor element 8 and the semiconductor element side connection electrode surface 21-c on the wiring film 14 are pressed against each other due to thermal contraction. Connection is complete. The FC portion sealing resin 16 may be injected as a liquid after the semiconductor element 8 is disposed on the wiring film 14, and in this case, it penetrates into the gap between the semiconductor element and the wiring film 14 by a capillary phenomenon or the like. Thus, the sealing resin can be applied to the entire lower surface of the semiconductor element.

  Next, as shown in FIG. 4A, the second semiconductor element 6 is mounted on the opposite side surface of the wiring film 14 on which the first semiconductor element 8 is mounted. A bump electrode 6-b is formed on the wiring side surface of the semiconductor element 6 by a wire bond method, a plating method or the like.

  Next, as shown in FIG. 4B, after the semiconductor element 8 is arranged on the wiring film 14, the FC portion sealing resin 15 is formed and the bump electrode 6-b on the surface of the semiconductor element 6 and the wiring are formed. The semiconductor element side connection electrode surface 21-b on the film 14 is electrically connected. In principle, as in the case of mounting the first semiconductor element 8 in FIG. 3, the FC part sealing resin is sealed in the FC part at some point before or after the mounting of the semiconductor element in the process by various flip chip methods. Form a stop resin.

  As described above, the wiring film unit 27 on which the second semiconductor element and the first semiconductor element are mounted is arranged above the third semiconductor element 1 that has already been mounted on the substrate 3 as shown in FIG. To be installed. As shown in FIG. 5A, the third semiconductor element 1 is flip-chip bonded to the substrate 3 via an FC underfill resin 5. An adhesive layer 7 is formed on the back surface (upper surface) of the semiconductor element 1. This may be a method of attaching an adhesive sheet or applying an adhesive paste.

  Next, as shown in FIG. 5B, after the wiring film unit 27 is disposed above the third semiconductor element 1, the electrode surfaces 22-b and 22-c on the end surface of the wiring film 14 are formed on the substrate surface. Bonded to the surfaces 4-b and 4-c. The bonding method may be any method such as a connection using a gold bump and an Ag paste (SBB method) or a bonding method between a gold bump and Sn plating, as in the flip chip method. Similar to the above, the bonding method may be an anisotropic conductive film bonding method or a bump pressure welding method (NSD method) by heat shrinkage of a non-conductive film, or the like, in which electrode bonding and sealing are simultaneously bonded.

  Subsequently, in order to protect the bonding portion 20 of the electrode, only the vicinity of the bonding surface is sealed with the sealing resin 25. Specifically, since the wiring conductors 17-b and 17-c are covered with the insulating resin on the wiring film 14, the semiconductor device is protected from ambient moisture and the like only by partial sealing, Insulation between wires can be maintained. In the above manufacturing method, the third semiconductor element 1 may not be provided.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, the semiconductor device can be configured without the need to seal the entire surface or the entire upper surface of the semiconductor device as in the related art.

  In the semiconductor device described above, the material of the interposer substrate is not selected. However, it has a great effect particularly when the ceramic substrate has a high rigidity and a large thermal expansion coefficient. This is because there is a difference in linear expansion compared to the mold sealing resin mainly composed of resin, and since the rigidity (Young's modulus) is high, the generated stress (= Young's modulus × strain amount) is increased.

  A more specific embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. The same members as those in the embodiment are denoted by the same reference numerals. This semiconductor device has a structure in which three stages of semiconductor elements are stacked as described in the above embodiment, and the lower third semiconductor element 1 is flip-chip bonded downward, and the second stage second semiconductor element 6, The first semiconductor element 8 at the third stage is mounted on the double-sided wiring film 14 so as to face each other, and the two semiconductor elements 6 and 8 are connected to the substrate 3 by the wiring film 14.

  FIG. 6 is a cross-sectional view showing a semiconductor device according to the second embodiment. The same members as those in the embodiment are denoted by the same reference numerals. As shown in FIG. 6, two or more semiconductor elements 26-1 and 26-2 are mounted on the double-sided wiring film 14. Furthermore, it is possible to laminate not only one double-sided wiring film having semiconductor elements on both sides as described above but also a plurality of layers.

  FIG. 7 is a cross-sectional view showing a semiconductor device according to the third embodiment. The same members as those in the embodiment are denoted by the same reference numerals. As shown in FIG. 7, there is no semiconductor element bonded to the substrate alone as in the lowermost semiconductor element 1, and the semiconductor element is composed only of the double-sided wiring film 14 having the semiconductor elements 6 and 8 mounted on both sides as described above. Stack mounting.

  FIG. 8 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. The same members as those in the embodiment are denoted by the same reference numerals. As shown in FIG. 8, by having two double-sided wiring films 14 having semiconductor elements 6 and 8 mounted on both sides, these wiring film units 27-1 and 27-2 are stacked and mounted on the substrate 3, This is a stacked semiconductor device in which a large number of semiconductor elements are stacked and mounted. In this case, two or more sheets may be stacked.

  FIG. 9 is a cross-sectional view showing a semiconductor device of Example 5. The same members as those in the embodiment are denoted by the same reference numerals. As shown in FIG. 9, when the solder part reliability requirement standard is low or the sealing resin solder joint is improved in strength by another means such as injection of underfill material, it is costly but secures reliability. In such a case, the same semiconductor device configuration as that of the first embodiment is adopted for the purpose of narrow pitch only. In this case, the upper surface of the semiconductor device may be covered with the sealing resin 13.

  FIG. 10 is a cross-sectional view showing a semiconductor device of Example 6. The same members as those in the embodiment are denoted by the same reference numerals. As shown in FIG. 10, a lead frame material 30 such as copper is used for a substrate on which a semiconductor element used in the configuration of the semiconductor device is mounted. 30-a is a lead part, and 30-b is a die pad part. In this semiconductor device, the wiring film unit 27 on which the plurality of semiconductor elements 6 and 8 are mounted can be installed on both surfaces of the lead frame 30.

  INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention are useful as a means for providing a stacked semiconductor device in which a plurality of semiconductor elements are packaged to realize a narrow pitch and high density wiring circuit and improve solder joint reliability. It is.

It is sectional drawing which shows the semiconductor device concerning embodiment of this invention. (A) is sectional drawing which shows the wiring film used with the semiconductor device concerning embodiment of this invention, (b) is AA sectional drawing. It is sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the semiconductor device of 3 chip | tip lamination | stacking in Example 2 of this invention. It is sectional drawing which shows the semiconductor device of 2 chip | tip lamination | stacking in Example 3 of this invention. It is sectional drawing which shows the semiconductor device using two wiring films in Example 4 of this invention. It is sectional drawing which shows the semiconductor device concerning Example 5 of this invention. It is sectional drawing which shows the semiconductor device concerning Example 6 of this invention. It is sectional drawing which shows the conventional laminated semiconductor device. It is a stress figure at the time of soldering of the conventional laminated semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional laminated semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 3rd semiconductor element 2 Bump electrode 3 Board | substrate 4 Chip mounting wiring land 4-a On-board wiring electrode 4-b On-board wiring electrode 4-c On-board wiring electrode 5 FC part underfill resin 6 Second semiconductor element 6-b Bump electrode 7 of second semiconductor element Adhesive layer 8 First semiconductor element 8-b Bump electrode 9 of first semiconductor element Adhesive layer 10 Bonding wire 11 Bonding wire 12 Solder ball electrode Terminal 13 Mold sealing resin 14 Wiring film 15 FC part sealing resin 16 FC part sealing resin 17-c Wiring conductor 17-b Wiring conductor 18 Film substrate 19 Insulating resin 20 Junction 21 Semiconductor element side connecting electrode surface 21-c Electrode surface (upper side)
21-b Electrode surface (lower side)
22 Substrate side connection electrode surface 22-c Electrode surface (upper side)
22-b Electrode surface (lower side)
23 Wiring conductor post 24 Bonding member plating 25 Resin sealing material 26-1 Semiconductor element 26-2 Semiconductor element 27 Wiring film 27-1 on which the second semiconductor element and the third semiconductor element are mounted Semiconductor element and semiconductor element First wiring film 27-2 mounted with a semiconductor element A second wiring film 30 mounted with a semiconductor element Lead frame 30-a Lead frame lead part 30-b Lead frame die pad part

Claims (18)

  A stacked type comprising a substrate having a wiring layer and having a solder joint on the lower surface, and at least two or more semiconductor elements stacked on the substrate and including a first semiconductor element and a second semiconductor element A semiconductor device, comprising a wiring film in which at least two layers of wiring conductors are formed, wherein the first semiconductor element is connected to the wiring conductor of the wiring film, and the second semiconductor element is A semiconductor device, wherein the first semiconductor element is connected to another wiring conductor on the opposite side of the wiring film surface to which the first semiconductor element is connected, and the wiring conductor is connected to the substrate.   The semiconductor device according to claim 1, wherein the wiring film has at least two layers of wiring conductors formed on both front and back surfaces.   The semiconductor device according to claim 1, wherein the wiring conductor of the wiring film is covered with a film for insulating and protecting between the wiring conductors except for the electrode surface.   4. The semiconductor device according to claim 1, wherein only the vicinity of an electrical connection portion between the semiconductor element, the wiring film, and the substrate is sealed with resin.   The semiconductor device according to claim 1, further comprising a wiring portion that is electrically connected to the film surface from each layer of the wiring conductor, wherein an electrode surface from the wiring conductor is exposed on a connection surface side with the substrate.   The semiconductor device according to claim 1, wherein a protruding electrode portion for connecting to an electrode of a semiconductor element or a wiring electrode on the substrate is provided on an electrode surface of a wiring conductor surface of the wiring film.   The semiconductor device according to claim 1, wherein the protruding electrode portion for connecting to the wiring conductor of the wiring film is provided on the electrode surface of the semiconductor element or the wiring electrode surface on the substrate.   The semiconductor device according to claim 1, further comprising: a wiring film unit in which one semiconductor element is mounted on each side of the wiring film, and the wiring film unit is electrically connected to the substrate.   9. The semiconductor device according to claim 8, wherein one or more semiconductor elements are mounted on the substrate, and the wiring film unit is installed on the upper part of the semiconductor elements.   The semiconductor device according to claim 8, comprising two or more wiring film units.   The semiconductor device according to claim 1, wherein the substrate having a wiring layer is made of a ceramic having a conductor wiring.   The semiconductor device according to claim 1, wherein the upper surface region of the substrate is entirely sealed with a sealing resin.   The semiconductor device according to claim 1, wherein the substrate having a wiring layer is a metal lead frame.   The semiconductor device according to claim 13, wherein each of the upper and lower surfaces of the lead frame has one or more wiring films on which the semiconductor elements are mounted.   15. The semiconductor device according to claim 13, wherein the upper and lower regions of the lead frame are all sealed with a sealing resin. Preparing a wiring film on which at least two layers of wiring conductors are formed, and connecting the first semiconductor element to the wiring conductor of the wiring film;
A second step of connecting the second semiconductor element to another wiring conductor of the wiring film on the opposite side of the wiring film surface to which the first semiconductor element is connected;
A third step of connecting the wiring conductor of the wiring film to the substrate;
A method for manufacturing a semiconductor device, comprising: a fourth step of resin-sealing the vicinity of a connection portion with the substrate. Preparing a wiring film on which at least two layers of wiring conductors are formed, and connecting the first semiconductor element to the wiring conductor of the wiring film;
A second step of connecting the second semiconductor element to another wiring conductor of the wiring film on the opposite side of the wiring film surface to which the first semiconductor element is connected;
A third step of flip-chip connecting the third semiconductor element having the protruding electrode portion formed on the surface to the substrate via a resin;
A fourth step of connecting the wiring conductor of the wiring film on which the first and second semiconductor elements are mounted to a substrate on which the third semiconductor element is mounted;
And a fifth step of resin-sealing the vicinity of the connecting portion with the substrate.   The first and second steps are repeated at least twice, and the wiring conductors of the plurality of wiring films on which the first and second semiconductor elements are mounted are connected to the substrate on which the third semiconductor element is mounted. A method for manufacturing a semiconductor device according to claim 17.

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