JP4439339B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device which has large number of terminals more than a semiconductor storage element has, and can be further reduced in size and thickness by stabilizing a sealing process in the lamination of semiconductor elements differing in sizes. <P>SOLUTION: The semiconductor element laminated type semiconductor device comprises a 1st substrate 2 having electrodes on its top surface and external electrode terminals on its reverse surface, a 1st semiconductor element 1 which is electrically connected on the 1st substrate 2, a 2nd substrate 6 which is bonded to the top surface of the 1st semiconductor element 1, a 2nd semiconductor element 5 which is electrically connected on the 2nd substrate 6 and smaller than the 1st semiconductor element 1, a metal wire 7 which electrically connects the 1st substrate 2 and 2nd substrate 6, and sealing resin (insulating resin) 8 covering the top surface of the 1st substrate. The 1st and the 2nd semiconductor elements 1 and 5 are connected to the 1st and the 2nd substrate 2 and 6 by a flip chip method, and the 2nd semiconductor element 5 is electrically connected to the 1st substrate 2 through the 2nd substrate 6 and a metal wire 7. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device that protects an integrated circuit portion of a semiconductor element, stably secures an electrical connection between an external device and the semiconductor element, and enables high-density mounting, and a method of manufacturing the semiconductor device. The present invention relates to a chip stacked package using flip chip technology.

  In recent years, a package in which a plurality of semiconductor devices are stacked on a single package has been developed as a method for mounting semiconductor devices at high density. Among them, studies are being made to reduce the size, thickness, and number of pins of stacked packages that use wire bonds to achieve stacking of relatively small pin semiconductor memory elements, and stacked packages that use flip chip connection and wire bond connections. Many have been made.

In the following description, for the sake of convenience, the surface located on the upper side in the drawing is referred to as the upper side surface, and the surface located on the lower side is referred to as the lower side surface.
FIG. 14 shows an example of a stacked package using only the wire bond method. In FIG. 14, semiconductor elements 20 and 21 are laminated upward on a substrate 22 by a non-conductive adhesive 26, and the semiconductor elements 20 and 21 are electrically connected to the substrate 22 by metal wires 23. The entire upper part is covered with a sealing resin 29.

FIG. 15 shows an example of a stacked package using both flip chip mounting and wire bond connection. In FIG. 15, the semiconductor element 20 is flip-chip mounted on a substrate 22 with bumps 24 and encapsulated with a sealing resin 25. In the semiconductor element 20, the semiconductor element 21 is bonded to the upper surface with a nonconductive adhesive 26, the semiconductor element 21 and the 2nd pad 27 of the substrate 22 are electrically connected by the metal wire 23, and the entire upper portion of the substrate 22 is sealed. Covered with resin 29.
JP 2002-368190 A

  In the conventional stacked package described in FIGS. 14 and 15, the upper semiconductor element 21 is electrically connected to the substrate 22 by the metal wire 23, so that the size difference between the stacked semiconductor elements 20 and 21 is large. In this case, the length of the metal wire 23 from the upper semiconductor element 21 to the substrate 22 becomes very long, and the metal wire 23 is short-circuited or pressed by the pressure applied to the metal wire 23 when the sealing resin 29 is injected. There is a problem that a deviation occurs.

  Further, in order to prevent the metal wire 23 connecting the upper semiconductor element 21 and the 2nd pad 27 from contacting the lower semiconductor element 20, the 2nd pad 27 is set at a position farther than the lower semiconductor element 20. Therefore, it is necessary to secure the loop height of the metal wire 23, which is one factor that hinders downsizing of the semiconductor device. Furthermore, with respect to the thickness direction, the entire semiconductor device becomes thicker by the loop height of the metal wire 23, which prevents the semiconductor device from being thinned.

  Further, in the conventional laminated package using only the wire bonding method shown in FIG. 14, since the number of the metal wires 23 is large, when the semiconductor elements 20 and 21 having a large number of terminals are laminated, the short-circuit failure of the metal wires 23. Although it is necessary to widen the pitch of adjacent terminals of the 2nd pad 27 for the reduction, there is a problem that the semiconductor device is increased in size, which is limited to the stacking of relatively small pin semiconductor elements.

    Patent Document 1 discloses a method for solving the problems that occur accompanying the formation of long wires of the metal wires 23 due to the stacking of semiconductor elements having a large size difference as described above. This is as shown in FIG. 16, and by providing a wiring board 28 that relays electrical connection from the upper semiconductor element 21 to the board 22 between the upper and lower semiconductor elements 20, 21, A method of shortening the length to solve the problems of wire short-circuit and wire detachment due to the wire flow (deformation of the metal wire 23 caused by the pressure applied when the sealing resin 29 is injected) and reducing the thickness of the entire apparatus. is suggesting.

  However, in the above method, since the semiconductor element 20 is connected to the substrate 22 by the metal wire 23, when the semiconductor elements 20 and 21 having a larger number of terminals than the semiconductor memory element are stacked, it is unavoidable due to the number of wires. The problem remains that the size increases and wire short-circuiting or disconnection occurs.

  Further, when assembling and stacking semiconductor elements, if one of the semiconductor elements is defective in the electrical characteristic inspection, the other semiconductor element is inevitably discarded. In other words, the final yield is determined by integrating the electrical inspection yield of each chip. For this reason, there exists a subject that the assembly cost at the time of laminating | stacking a semiconductor element will increase.

  In many stacked packages, an electric signal is shared between the upper semiconductor element and the lower semiconductor element. Generally, a substrate capable of high-density wiring or a substrate using a stacked substrate is used. However, there is a problem that an expensive substrate material is required.

  The present invention solves such a problem. The number of terminals is larger than that of a semiconductor memory element, and the sealing process is stabilized against the stacking of semiconductor elements having different sizes. It is an object of the present invention to provide an inexpensive and inexpensive semiconductor device and a method for manufacturing the same.

To solve the problems described above, the semiconductor device of the present onset Ming, a first substrate having an external electrode terminal to the upper side to the electrode and the lower surface, a first electrically connected to said first substrate A semiconductor substrate, a second substrate bonded to the upper surface of the first semiconductor element, a second semiconductor element electrically connected to the second substrate, and the first substrate In the semiconductor element stacked type semiconductor device composed of a metal wire electrically connecting the second substrate and an insulating resin covering the upper surface of the first substrate, the first and second Semiconductor elements are flip-chip connected to the first and second substrates, respectively, and the second semiconductor elements are electrically connected to the first substrate via the second substrate and the metal wires. An upper surface wiring formed on the upper surface by the second substrate; The lower side surface wiring formed on the side surface is electrically connected, and the lower side surface wiring is connected to the upper side surface wiring by a through hole of the second substrate, and is connected to the upper surface of the first semiconductor element. The side surface and the lower surface wiring of the second substrate are bonded by a conductive adhesive, and the upper surface wiring of the second substrate is electrically connected to the GND of the first substrate through a metal wire. This is a semiconductor device.

  With this configuration, it is possible to achieve a further reduction in size and thickness of the semiconductor device by stabilizing the sealing process when stacking semiconductor elements having a larger number of terminals and different sizes compared to semiconductor memory elements. Become.

  That is, the lower first semiconductor element is flip-chip mounted, the upper second semiconductor element is flip-chip mounted on the second substrate, and the terminal is drawn out to the periphery of the substrate, and the second substrate is connected to the first substrate. By electrically connecting to the substrate with metal wires, the metal wires of the first semiconductor element are eliminated, the wires flow during sealing, the number of metal wires that are subject to wire removal is reduced, and the pad pitch scale conversion (Reduction of the adjacent terminal pitch of the pad) and shortening of the metal wire length to the first substrate (reduction of the wire loop height) can be achieved.

  As a result, it is possible to reduce wire flow, wire disconnection, and wire short-circuit during sealing, which is a problem, and further prevent an increase in the size of the semiconductor device caused by an increase in the length of the metal wire from the second semiconductor element. As a result, the semiconductor device itself can be reduced in size and thickness.

  Specifically, even when the size difference between the first semiconductor element and the second semiconductor element is 4.0 mm or more, the metal wire length can be suppressed to a substantially constant value of 1.5 mm or less, and the stable wire arrangement And the sealing process can be established.

  For example, when the pad pitch of the second semiconductor element is 60 μm, if the metal wire length is 4 mm or more, the occurrence frequency of defects such as a short due to the wire flow increases. Considering that the pad pitch of the 2nd bonding pads formed on the first substrate on the radiation centering on the first semiconductor element is increased according to the length of the fillet formed by flip chip mounting. This effect becomes significant when the size difference of the semiconductor elements is 4 mm or more.

  Moreover, since the scale conversion of the pad pitch is performed by the second substrate, it is not necessary to arrange the bonding pads on the first substrate radially by increasing the pad pitch, and the number of terminals of the second semiconductor element is 250. Even if there are ˜350 pins, the semiconductor device itself can be downsized.

  In this way, the wire length can be shortened by flip-chip bonding the first and second semiconductor elements together and performing the scale conversion on the second substrate, so that both the number of pins of the semiconductor device can be reduced and the size can be reduced. It becomes. Furthermore, the entire semiconductor device can be thinned by flip-chip bonding the second semiconductor element.

  In addition, the wiring pattern on the second substrate allows the shared electrical signal terminal of the second semiconductor element with the first semiconductor element to be rearranged in the vicinity of the shared electrical signal terminal of the first semiconductor element. The wiring pattern in the first substrate eliminates the need for complicated wiring.

For example, when realizing a stacked package having about 300 terminals of the first semiconductor element, about 300 terminals of the second semiconductor element and about 80 terminals of the shared signal terminal with the configuration of FIG. 14 or FIG. Depending on the arrangement of the shared electric signal terminals, a high-density laminated substrate having 4 to 6 layers is necessary. However, the configuration of the present invention has 2 to 3 layers for the first wiring substrate and 1 to 2 layers for the second wiring substrate. The stacked package can be realized by an inexpensive combination of substrates.
Further, the upper surface of the first semiconductor element is electrically connected to the GND of the first substrate through the conductive adhesive, the lower surface wiring and the upper surface wiring of the second substrate, and the metal wire. Since the lower surface of the first semiconductor element is electrically connected to the GND of the first substrate through the first and second semiconductor elements, the potentials of the upper and lower surfaces of the first semiconductor element can be stabilized.

Further, there is the second substrate being larger than the first semiconductor element, and correspondingly the second substrate to the fillet of the sealing resin of the first semiconductor device the first semiconductor element By forming it larger than that, the wire length can be shortened regardless of the fillet of the sealing resin of the first semiconductor element.

Further , the second substrate is composed of an adhesive sheet to which metal wiring is transferred.
In addition , a plurality of semiconductor elements are flip-chip connected to the first substrate.

This configuration enables further high-density mounting.
Further , a plurality of semiconductor elements are flip-chip connected on the second substrate to form a multichip module (MCM) on the first semiconductor element.

With this configuration, the number of electrical connections to the first substrate can be shortened by further high-density mounting and by connecting the chips in the MCM.
Further , the upper surface of the second semiconductor element is exposed to the outside of the insulating resin.

With this configuration, it is possible to reduce the thickness of the entire semiconductor device and improve heat dissipation characteristics.
Method of manufacturing a semi-conductor device of the present invention, the first semiconductor element is flip-chip mounted on the first substrate having an external electrode terminal to the upper side to the electrode and the lower surface, the the second substrate first A second semiconductor element smaller than the first semiconductor element is flip-chip mounted, a second substrate is bonded to the upper surface of the first semiconductor element, and an electrode on the upper surface of the first substrate and the second substrate Are electrically connected with a metal wire, the upper surface of the first substrate is covered with an insulating resin, and the upper surface wiring formed on the upper surface and the lower surface wiring formed on the lower surface of the second substrate; The lower surface wiring is connected to the upper surface wiring by a through hole of the second substrate, and the upper surface of the first semiconductor element is connected to the lower surface of the second substrate. Adhere the side wiring to the second substrate with a conductive adhesive. The surface wiring through a metal wire to GND of the first substrate is characterized in that the electrically connected.
44

  As described above, according to the present invention, the upper semiconductor element and the lower semiconductor element are both mounted on the substrate by flip chip bonding, and each package is adhered and stacked with a thermosetting adhesive or the like, The upper substrate and the lower substrate are electrically connected by wire bonding.

  As a result, a multi-pin chip can be stacked, and a semiconductor device that can be reduced in size and thickness that cannot be realized when the size difference between the upper and lower semiconductor elements is large is realized. Furthermore, since it is stacked after being packaged, it is possible to stack with only a chip that has passed the electrical characteristic inspection, and it is possible to improve the yield. Furthermore, since a stacked package can be realized by combining an inexpensive substrate, the cost of the high-density stacked package can be reduced.

Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.
FIG. 1 shows the configuration of a chip stack package according to a first embodiment of the present invention. In FIG. 1, a chip 1 of a first semiconductor element is flip-chip bonded to a first substrate 2 via bumps 3, and a sealing resin 4 is filled in the gap. Further, the chip 5 of the second semiconductor element is also flip-chip bonded to the second substrate 6 via the bumps 3, and the upper surface of the chip 1 is bonded via the adhesive sheet 14 provided on the lower surface of the second substrate 6. It is joined. The first substrate 2 and the second substrate 6 are electrically connected by a metal wire 7, and the entire upper portion of the substrate 2 is covered with a sealing resin (insulating resin) 8.

  2 to 5 show a flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIGS. 2 and 3, the chip 5 on which the bumps 3 are formed is mounted on the second substrate 6 in which the product areas are arranged in a matrix. Similarly, the chip 1 is flip-chip bonded and mounted on the first substrate 2 formed into a matrix.

  At this time, an organic built-up substrate, a ceramic substrate, a tape substrate, or the like can be used as the first substrate 2 depending on the number of terminals of the external terminals 13 and the intended use, but the second substrate 6 has a wire bond pitch. Since the purpose is to shorten the conversion and the wire length, a relatively inexpensive and thin organic single layer plate or tape substrate having a pattern as shown in FIG. 9 is used.

  The second substrate 6 has a pad arrangement in which the electrode 9 for connecting the chip 5 is mirror-reversed at the terminal position of the chip 5, and the electrode 10 is electrically connected to the first substrate 2 by the metal wire 7. The electrode 9 and the electrode 10 are connected by the wiring 11. The second substrate 6 can also be composed of an adhesive sheet to which metal wiring is transferred.

  For flip chip bonding, a C4 connection structure using solder bumps, SBB connection in which a stat bump is formed on a chip and then connected to a substrate via a conductive paste, or an anisotropic conductive sheet after bumps are formed on a chip (ACF) or a non-conductive film (NCF) can be used for pressure bonding to the substrate.

  Next, as shown in FIG. 4, the second substrate 6 on which the chip 5 is mounted is attached to the wafer ring 16 using an adhesive sheet 14 in which a thermosetting sheet 15a and a dicing sheet 15b are integrated. Thereafter, as shown in FIG. 5, after being separated into pieces by dicing with the blade 17, die bonding is performed on the upper side surface of the chip 1 by heat curing as shown in FIG.

  In the above-described configuration, the thermosetting sheet 15a is used for bonding to the wafer ring 16, but the second substrate 6 is fixed using only the dicing sheet 15b, and dicing is performed. It is also possible to attach the substrate 6 to the chip 1 by attaching a paste to the upper surface of the chip 1. Since the chips 1 and 5 are packaged and can be inspected for electrical characteristics at the time of stacking, it is possible to improve the yield by stacking chips with a configuration that passes the electrical characteristics inspection.

  Next, as shown in FIG. 7, the second substrate 6 is connected to the first substrate 2 with a metal wire 7. The metal wire 7 may use AL or Cu wire in addition to the Au wire generally used in the ball bonding method. Finally, as shown in FIG. 8, the entire upper surface of the first substrate 2 is collectively sealed by transfer molding, and package dicing is performed to form a final outer shape.

  FIG. 10 shows a configuration according to the second embodiment of the present invention. In this configuration, the upper surface of the chip 5 is exposed to the outside of the sealing resin 8, and it is possible to reduce the thickness and improve the heat dissipation. The manufacturing method of this embodiment conforms to the previous manufacturing flow, but after the sealing resin 8 is configured, a step of polishing the upper surface of the package to expose the upper surface of the chip 5 is added. Although the number of steps increases, the thickness of the semiconductor device can be reduced to the maximum.

  FIG. 11 shows a configuration according to the third embodiment of the present invention. In this configuration, the second substrate 6 has a structure in which the size of the second substrate 6 is formed larger than the chip size of the lower chip 1, and the second substrate 6 is filled with the sealing resin fillet of the first substrate 2. By making it larger than the chip 1 corresponding to L, it becomes possible to shorten the wire length regardless of the fillet L of the chip 1, and the length of the fillet L of the conventional flip chip bonding is made of metal. It can prevent that the wire 7 becomes long. As a result, the length of the metal wire 7 can be suppressed to about 0.5 to 1 mm, and the process of the sealing process can be further stabilized.

  FIG. 12 shows a fourth embodiment of the present invention. In this configuration, the second substrate 6 has an upper side surface wiring 19a and a lower side surface wiring 19b formed on both the upper side surface and the lower side surface, respectively, and the upper side surface of the chip 1 and the lower side surface wiring 19b of the second substrate 6 are formed. Are electrically connected by a conductive adhesive. Various types of conductive adhesives such as a sheet, a tape, and a paste are commercially available, and any material may be selected depending on the shape and material of the first semiconductor element and the second substrate. The lower side surface wiring 19b is connected to the upper side surface wiring 19a by the through hole 18 of the substrate 6, and the upper side surface wiring 19a is further connected to the 2nd pad 12 of the first substrate 2 by the metal wire 7, and the 2nd pad 12 is connected to the GND. It is connected.

With the above structure, the back surface potential of the chip 1 can be changed to GND, and a semiconductor device having excellent electrical characteristics can be realized.
FIG. 13 shows a fifth embodiment of the present invention. In this configuration, a plurality of chips 5 are mounted on the second substrate 6 by flip chip bonding to form a multichip module. The chips 5 on the second substrate 6 can be electrically connected to each other via the second substrate 6. As a result, the number of terminals connected to the first substrate 2 with the metal wires 7 can be minimized, and the frequency of occurrence of problems such as wire shorts and disconnection of the metal wires 7 can be reduced. Further, it is possible to further increase the density of the semiconductor device.

  According to the present invention, a semiconductor device can be reduced in size and thickness, such as an information communication device, an office electronic device, a home electronic device, a measuring device, an industrial electronic device such as an assembly robot, a medical electronic device, an electronic toy, etc. Miniaturization can be facilitated.

Sectional drawing of embodiment of the semiconductor device concerning one Embodiment of this invention 2A and 2B show a state in which chips are arranged on a second substrate in the method for manufacturing a semiconductor device according to the embodiment, where FIG. 3A is a plan view and FIG. 2B is a cross-sectional view taken along line A'-B '. The state which has arrange | positioned the chip | tip on the 1st board | substrate in the manufacturing method of the semiconductor device concerning the embodiment is shown, (a) is a top view, (b) is AB sectional view taken on the line. The top view which mounted | wore the wafer ring with the 2nd board | substrate which mounted the chip | tip in the manufacturing method of the semiconductor device concerning the embodiment The schematic diagram which shows the dicing of the 2nd board | substrate which mounted the chip | tip in the manufacturing method of the semiconductor device concerning the embodiment The state which carried out the die bonding in the manufacturing method of the semiconductor device concerning the embodiment is shown, (a) is a top view, (b) is A "-B" arrow sectional drawing. Sectional drawing which shows the state which connected the 2nd board | substrate and 1st board | substrate with the metal wire in the manufacturing method of the semiconductor device concerning the embodiment Sectional drawing which shows the final external shape in the manufacturing method of the semiconductor device concerning the embodiment The top view which shows the 2nd board | substrate concerning the embodiment Sectional drawing of the semiconductor device concerning the 2nd Embodiment of this invention Sectional drawing of the semiconductor device concerning the 3rd Embodiment of this invention. Sectional drawing of the semiconductor device concerning the 4th Embodiment of this invention Sectional drawing of the semiconductor device concerning the 5th Embodiment of this invention Sectional view showing a conventional chip stacked semiconductor device Sectional view showing a conventional chip stacked semiconductor device Sectional view showing a conventional chip stacked semiconductor device

Explanation of symbols

1 Chip 2 First substrate 3 Bump 4 Sealing resin (insulating resin)
5 Chip 6 Second substrate 7 Metal wire 8 Sealing resin (insulating resin)
9 Electrode 10 Electrode 11 Wiring 12 2nd pad 13 External terminal 14 Adhesive sheet 15a Thermosetting sheet 15b Dicing sheet 16 Wafer ring 17 Blade 18 Through hole 19a Upper side wiring 19b Lower side wiring

Claims (7)

A first substrate having an electrode on an upper surface and an external electrode terminal on a lower surface; a first semiconductor element electrically connected to the first substrate; and an upper surface of the first semiconductor element. A second substrate, a second semiconductor element electrically connected on the second substrate, a metal wire electrically connecting the first substrate and the second substrate, and In a semiconductor element stacked type semiconductor device composed of an insulating resin covering the upper surface of the first substrate, the first and second semiconductor elements are flip-chip on the first and second substrates, respectively. Connected to the first substrate through the second substrate and the metal wire, and an upper surface wiring and a lower surface formed on the upper surface of the second substrate. It is formed by electrically connecting the lower surface wiring formed on the side surface. The lower surface wiring is connected to the upper surface wiring by a through hole of the second substrate, and the upper surface of the first semiconductor element and the lower surface wiring of the second substrate are connected by a conductive adhesive. A semiconductor device , wherein the upper surface wiring of the second substrate is electrically connected to the GND of the first substrate via a metal wire . The semiconductor device of claim 1, wherein the second substrate being greater than said first semiconductor element. 3. The semiconductor device according to claim 1, wherein the second substrate is formed of an adhesive sheet to which metal wiring is transferred . The semiconductor device according to claim 1, wherein a plurality of the semiconductor elements are flip-chip connected to the first substrate . The semiconductor device according to any one of claims 1 to 4, characterized in that flip-chip connecting a plurality of said semiconductor element to said second substrate. The semiconductor device according to any one of claim 1 to 5, characterized in that the upper surface of the second semiconductor element is exposed to the outside of the insulating resin. A first semiconductor element is flip-chip mounted on a first substrate having an electrode on the upper surface and an external electrode terminal on the lower surface, and a second semiconductor element is flip-chip mounted on the second substrate, A second substrate is bonded to the upper surface of the semiconductor element, the electrode on the upper surface of the first substrate and the second substrate are electrically connected by a metal wire, and the upper surface of the first substrate is Covering with an insulating resin, the second substrate is formed by electrically connecting an upper side surface wiring formed on the upper side surface and a lower side surface wiring formed on the lower side surface. Connected to the upper surface wiring by a through hole of the second substrate, and the upper surface of the first semiconductor element and the lower surface wiring of the second substrate are bonded by a conductive adhesive, Side wiring is electrically connected to GND on the first board via metal wire The method of manufacturing a semiconductor device, characterized in that the.

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