JP2008016527A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To entirely make a semiconductor device thin in which two semiconductor components are stacked on a circuit board. <P>SOLUTION: A first semiconductor component 6a is mounted in the central part on the upper surface of a circuit board 1 by face-down method. An upper wiring 20 is provided in the central part on the upper surface of the first semiconductor component 6a, and an upper connection pad 22 is connected to the upper wiring 20 in the periphery on the upper surface thereof. A second semiconductor component 6b smaller in size than the first semiconductor component 6a is mounted to the central part on the upper surface of the first semiconductor component 6a by face-down method. The upper connection pad 22 in the periphery on the upper surface of the first semiconductor component 6a is connected with a second upper connection pad 3 in the periphery on the upper surface of the circuit board 1 through a bonding wire 25. In this case, the highest point of the bonding wire 25 is lower than the upper surface of the second semiconductor component 6b, so that the device is entirely made thin. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In the conventional semiconductor device, in order to reduce the mounting area, a first semiconductor chip is mounted at the center of the upper surface of the substrate, and a second semiconductor chip having a smaller size is mounted at the center of the upper surface of the first semiconductor chip. And connecting the connection pads provided at the peripheral portions of the upper surfaces of the first and second semiconductor chips and the upper connection pads provided at the peripheral portions of the upper surface of the substrate through the bonding wires, including the bonding wires There is one in which first and second semiconductor chips are covered with a sealing material, and solder balls are provided under lower layer connection pads provided under the substrate (see, for example, Patent Document 1).

JP 2004-111656 A

  However, in the above-described conventional semiconductor device, the highest point of the bonding wire for connecting the connection pad of the second semiconductor chip and the upper layer connection pad of the substrate is located above the second semiconductor chip. There is a problem that the whole becomes thick. Recently, the number of connection pads of a semiconductor chip has further increased, and the pitch of connection pads has been reduced. As a result, in particular, the bonding area of the connection pads of the second semiconductor chip is reduced, and the bonding wires for connecting the connection pads of the second semiconductor chip and the upper layer connection pads of the substrate are relatively thin and relatively long. However, there is a problem that the impedance becomes large and cannot be adapted for high frequency use.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can be thinned as a whole and can be adapted for high frequency use, and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to the present invention comprises, on a substrate, a plurality of semiconductor structures having a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate in order from the substrate side. The semiconductor device is stacked in the order of the size of the semiconductor substrate, the lowermost semiconductor structure is mounted on the substrate with its external connection electrodes connected to the upper layer connection pads of the substrate, An upper layer wiring is provided on at least one semiconductor structure excluding the uppermost semiconductor structure, and a semiconductor structure mounted on the upper side of the semiconductor structure is connected to the upper layer wiring. The connected upper layer connection pad and the substrate are connected via a bonding wire.

  According to the present invention, the external connection electrode is provided under the semiconductor substrate of each semiconductor structure, and the upper layer wiring is provided on at least one semiconductor structure excluding the uppermost semiconductor structure. The semiconductor structure can be mounted on the substrate by a face-down method without using bonding wires, and the semiconductor structure mounted on the upper part of the semiconductor structure is mounted by the face-down method, so that the lower semiconductor structure By connecting the upper layer connection pad connected to the upper layer wiring of the body and the substrate through the bonding wire, the external connection electrode of the upper semiconductor structure and the substrate can be electrically connected. The entire apparatus can be thinned and can be adapted for high frequency use.

(First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a circuit board 1 having a planar rectangular multilayer wiring structure. A plurality of first upper layer connection pads 2 are provided in the central portion (first region) of the circuit board 1, and a plurality of second upper layer connection pads 3 are provided in the peripheral portion (second region) of the upper surface. A plurality of lower layer connection pads 4 are provided on the lower surface. The first and second upper layer connection pads 2 and 3 and the lower layer connection pad 4 are connected via an internal wiring (not shown) provided in the circuit board 1. A solder ball 5 is provided on the lower surface of the lower layer connection pad 4.

  Planar rectangular first and second semiconductor constructs 6a and 6b are stacked in this order at the center of the circuit board 1. In this case, the first and second semiconductor structures 6a and 6b are different in size but have almost the same basic structure, and are generally called CSP (chip size package). .

  Next, a description will be given of portions where the basic configurations of the first and second semiconductor structures 6a and 6b are substantially the same. The first and second semiconductor constructs 6a and 6b include planar rectangular silicon substrates (semiconductor substrates) 7a and 7b. The size of the silicon substrate 7b is somewhat smaller than the size of the silicon substrate 7a. An integrated circuit (not shown) having a predetermined function is provided on the lower surface of the silicon substrates 7a and 7b, and a plurality of connection pads 8a and 8b made of aluminum metal or the like are provided on the periphery of the lower surface so as to be connected to the integrated circuit. It has been.

  Insulating films 9a and 9b made of silicon oxide or the like are provided on the lower surfaces of the silicon substrates 7a and 7b except for the central parts of the connection pads 8a and 8b, and the central parts of the connection pads 8a and 8b are provided on the insulating films 9a and 9b. The openings 10a and 10b are exposed. Protective films 11a and 11b made of polyimide resin or the like are provided on the lower surfaces of the insulating films 9a and 9b. Openings 12a and 12b are provided in the protective films 11a and 11b at portions corresponding to the openings 10a and 10b of the insulating films 9a and 9b.

  Base metal layers 13a and 13b made of copper or the like are provided on the lower surfaces of the protective films 11a and 11b. Wirings 14a and 14b made of copper are provided on the entire lower surface of the base metal layers 13a and 13b. One end portions of the wirings 14a and 14b including the base metal layers 13a and 13b are connected to the connection pads 8a and 8b through the openings 10a and 10b and the openings 12a and 12b of the insulating films 9a and 9b and the protective films 11a and 11b. Has been.

  Columnar electrodes (external connection electrodes) 15a and 15b made of copper are provided on the lower surfaces of the connection pad portions of the wirings 14a and 14b. Sealing films 16a and 16b made of epoxy resin or the like are provided on the lower surfaces of the protective films 11a and 11b including the wirings 14a and 14b so that the lower surfaces thereof are flush with the lower surfaces of the columnar electrodes 15a and 15b. Solder balls 17a and 17b are provided on the lower surfaces of the columnar electrodes 15a and 15b.

  Here, the second semiconductor structure 6b includes a silicon substrate 7b, a connection pad 8b, an insulating film 9b, a protective film 11b, a base metal layer 13b, a wiring 14b, a columnar electrode 15b, a sealing film 16b, and a solder ball 17b. Has been.

  Next, the difference between the first semiconductor structure 6a and the second semiconductor structure 6b will be described. An insulating film 18 made of polyimide resin or the like is provided on the upper surface of the silicon substrate 7a. A base metal layer 19 made of copper or the like is provided in the upper surface center portion (first region) of the insulating film 18. An upper wiring 20 made of copper is provided on the entire upper surface of the base metal layer 19. One end portion of the upper layer wiring 20 including the base metal layer 19 is connected to an upper layer connection pad 22 made of copper including the base metal layer 21 made of copper or the like provided in the peripheral portion (second region) of the upper surface of the insulating film 18. Has been.

  Here, the first semiconductor structure 6a includes a silicon substrate 7a, a connection pad 8a, an insulating film 9a, a protective film 11a, a base metal layer 13a, a wiring 14a, a columnar electrode 15a, a sealing film 16a, a solder ball 17a, an insulating film. The film 18, the base metal layer 19, the upper layer wiring 20, the base metal layer 21, and the upper layer connection pad 22 are configured.

  The first semiconductor structure 6a is bonded to the first upper layer connection pad 2 provided at the center of the upper surface of the circuit board 1 so that the solder ball 17a is bonded to the center of the upper surface of the circuit board 1. It is installed. In this case, an underfill material 23 is provided between the first semiconductor structure 6 a and the circuit board 1.

  The second semiconductor structure 6b has the solder ball 17b bonded to the connection pad portion of the upper layer wiring 20 provided at the center of the upper surface of the first semiconductor structure 6a. It is mounted on the center of the upper surface of 6a. In this case, an underfill material 24 is provided between the second semiconductor structure 6b and the first semiconductor structure 6a.

  The upper layer connection pads 22 provided in the periphery of the upper surface of the first semiconductor structure 6a and the second upper connection pads 3 provided in the periphery of the upper surface of the circuit board 1 are connected through bonding wires 25 made of gold. Has been. In this case, the highest point of the bonding wire 25 is at a position lower than the upper surface of the second semiconductor structure 6b. On the upper surface of the circuit board 1 including the first and second semiconductor constructs 6a and 6b and the bonding wires 25, an encapsulant 26 made of epoxy resin or the like is placed on the upper face of the second semiconductor construct 6b. It is provided to be one.

  As described above, in this semiconductor device, the columnar electrodes 15a and 15b are provided under the silicon substrates 7a and 7b of the first and second semiconductor constructs 6a and 6b, and the silicon substrate of the first semiconductor construct 6a is provided. Since the upper layer wiring 20 and the upper layer connection pad 22 connected to the upper layer wiring 20 are provided on 7a, the first semiconductor structure 6a is mounted on the circuit board 1 in a face-down manner without using bonding wires. In addition, the second semiconductor structure 6b is mounted on the first semiconductor structure 6a in a face-down manner, and the upper connection pads 22 of the first semiconductor structure 6a and the second upper layer of the circuit board 1 are mounted. By connecting the connection pads 3 via the bonding wires 25, the solder balls 17b of the second semiconductor structure 6b and the second upper connection pads 3 of the circuit board 1 are electrically connected. It can be connected to, thereby the entire apparatus can be made thinner, and may be also be adapted for high frequency.

  That is, the highest point of the bonding wire 25 for electrically connecting the solder ball 17b of the second semiconductor structure 6b and the second upper layer connection pad 3 of the circuit board 1 is the upper surface of the second semiconductor structure 6b. The overall position of the apparatus can be reduced. Moreover, since the upper surface of the sealing material 26 is flush with the upper surface of the second semiconductor structure 6b, the entire device can be made as thin as possible.

  One end portion of the bonding wire 25 for electrically connecting the solder ball 17b of the second semiconductor structure 6b and the second upper layer connection pad 3 of the circuit board 1 is the upper surface of the first semiconductor structure 6a. Since it is connected to the upper layer connection pad 22 provided in the peripheral portion, the length of the bonding wire 25 can be made relatively short. Moreover, the upper layer connection pads 22 provided in the periphery of the upper surface of the first semiconductor structure 6a have no relation to the narrow pitch of the connection pads 8a under the silicon substrate 7a, and the size thereof is increased as much as possible. It is possible. As a result, a relatively thick and relatively short bonding wire 25 can be used, the impedance can be reduced, and it can be adapted for high frequency use.

  Next, an example of a method for manufacturing the semiconductor device will be described. First, an example of a method for manufacturing the first semiconductor structure 6a will be described. In this case, as shown in FIG. 2, a connection pad 8a, an insulating film 9a, a protective film 11a, a base metal layer 13a, a wiring 14a, a columnar electrode 15a, and a silicon substrate (hereinafter referred to as a semiconductor wafer 31) in a wafer state. A film in which the sealing film 16a is formed and the solder ball 17a is not formed is prepared. In this case, the thickness of the semiconductor wafer 31 is somewhat thicker than the thickness of the silicon substrate 7a of the first semiconductor structure 6a shown in FIG. In FIG. 2, an area indicated by reference numeral 32 is an area corresponding to dicing street.

  Next, as shown in FIG. 3, the lower surface side of the semiconductor wafer 31 is appropriately ground to reduce the thickness of the semiconductor wafer 31 appropriately. Next, the one shown in FIG. 3 is turned upside down. As shown in FIG. 4, the lower surface of the sealing film 16a including the lower surface of the columnar electrode 15a is placed on the upper surface of the support plate 33 made of glass, hard resin, metal, or the like. The adhesive layer 34 is bonded to the upper surface of the provided novolac type phenolic resin or the like. The support plate 33 including the adhesive layer 34 compensates for a decrease in strength caused by appropriately reducing the thickness of the semiconductor wafer 31 and protects the lower surface of the sealing film 16a including the lower surface of the columnar electrode 15a. As will be described later, it is finally removed.

  Next, as shown in FIG. 5, a base metal layer 35 is formed on the entire top surface of the semiconductor wafer 31. In this case, the base metal layer 35 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, a plating resist film 36 is formed on the upper surface of the base metal layer 35 by patterning. In this case, an opening 37 is formed in the plating resist film 36 in a portion corresponding to the upper layer wiring 20 and the upper layer connection pad 22 formation region. Next, by performing electrolytic plating of copper using the base metal layer 35 as a plating current path, the upper layer wiring 20 and the upper layer connection pads 22 are formed on the upper surface of the base metal layer 35 in the opening 37 of the plating resist film 36.

  Next, the plating resist film 36 is peeled off, and then unnecessary portions of the base metal layer 35 are removed by etching using the upper layer wiring 20 and the upper layer connection pad 22 as a mask. As shown in FIG. The underlying metal layers 19 and 21 remain only under the upper connection pads 22. Next, the support plate 33 is removed together with the adhesive layer 34.

  Next, as shown in FIG. 7, solder balls 17a are formed on the lower surface of the columnar electrodes 15a. Next, as shown in FIG. 8, when the insulating film 18, the semiconductor wafer 31, the insulating film 9a, the protective film 11a, and the sealing film 16a are cut along the dicing street 32, the insulating film 18 and the upper layer are formed on the silicon substrate 7a. A plurality of first semiconductor structures 6a having a structure in which the wiring 20 and the upper layer connection pads 22 are provided are obtained.

  Next, as shown in FIG. 9, the first and second upper layer connection pads 2 and 3 are formed on the upper surface of the circuit board 1, the lower layer connection pad 4 is formed on the lower surface, and the solder balls 5 are not formed. Prepare things. Next, the solder ball 17a of the first semiconductor structure 6a is bonded to the first upper layer connection pad 2 of the circuit board 1, so that the first semiconductor structure 6a is faced down to the center of the upper surface of the circuit board 1. It is installed by the method. Next, the underfill material 23 is filled between the first semiconductor structure 6 a and the circuit board 1.

  Next, as shown in FIG. 1, the solder ball 17b of the second semiconductor structure 6b is joined to the connection pad portion of the upper layer wiring 20 of the first semiconductor structure 6a, whereby the second semiconductor structure 6b. Is mounted on the center of the upper surface of the first semiconductor structure 6a in a face-down manner. Next, the underfill material 24 is filled between the second semiconductor structure 6b and the first semiconductor structure 6a.

  Next, the upper connection pads 22 in the peripheral area on the upper surface of the first semiconductor structure 6a and the second connection pads 3 in the peripheral area on the upper surface of the circuit board 1 are connected via bonding wires 25 made of gold. Next, the upper surface of the circuit board 1 including the first and second semiconductor structures 6a and 6b and the bonding wires 25 is sealed with an encapsulant 26 made of epoxy resin or the like, the upper surface of which is the upper surface of the second semiconductor structure 6b. And to be flush with each other. Next, solder balls 5 are formed on the lower surface of the lower layer connection pads 4 of the circuit board 1. Thus, the semiconductor device shown in FIG. 1 is obtained.

(Second Embodiment)
In the first embodiment, the case where two semiconductor structures are stacked on the circuit board has been described. However, three or more semiconductor structures may be stacked. For example, the second embodiment of the present invention shown in FIG. As in the embodiment, three semiconductor structures may be stacked. This semiconductor device differs greatly from the semiconductor device shown in FIG. 1 in that it is larger than the first semiconductor structure 6a and has the same structure as that of the first semiconductor structure 6a. Is mounted at the center of the upper surface of the circuit board 1, and the first semiconductor structure 6a is mounted at the center of the upper surface of the lowermost semiconductor structure 6c.

  That is, the lowermost semiconductor structure 6c is mounted in a face-down manner at the center of the upper surface of the circuit board 1 by bonding the solder balls 17b to the first upper connection pads 2 of the circuit board 1. Yes. An underfill material 41 is provided between the lowermost semiconductor structure 6 c and the circuit board 1. An insulating film 18c is provided on the upper surface of the silicon substrate 7c of the lowermost semiconductor structure 6c. A plurality of upper layer wirings 20c are provided in the center of the upper surface of the insulating film 18c, and a plurality of upper layer connection pads 22c are provided in the periphery of the upper surface so as to be connected to the upper layer wirings 20c.

  The first semiconductor structure 6a has a solder ball 17a bonded to the connection pad portion of the upper wiring 20c of the lowermost semiconductor structure 6c, so that the first semiconductor structure 6a has a face at the center of the upper surface of the lowermost semiconductor structure 6c. It is installed in the down method. An underfill material 23 is provided between the first semiconductor structure 6a and the lowermost semiconductor structure 6c. The upper layer connection pad 22c of the lowermost semiconductor structure 6c and the second upper layer connection pad 3c provided on the periphery of the upper surface of the circuit board 1 are connected via a bonding wire 25c. The second upper layer connection pad 3 c is connected to the lower layer connection pad 4 via an internal wiring (not shown) of the circuit board 1.

(Other embodiments)
In FIG. 1 and FIG. 10, the second semiconductor structure 6b in the uppermost layer does not have the upper layer wiring 20 and the upper layer wiring connection pad 22 provided on the upper surface of the first semiconductor structure 6a. Therefore, any structure may be used as long as it is mounted on the central portion of the upper surface of the lower first semiconductor structure 6a. Therefore, a plurality of semiconductor structures other than the lowermost layer may be mounted at the center of the upper surface of the lowermost semiconductor structure.

1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the semiconductor device as 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit board 2 1st upper layer connection pad 3 2nd upper layer connection pad 4 Lower layer connection pad 5 Solder ball 6a 1st semiconductor structure 6b 2nd semiconductor structure 7a, 7b Silicon substrate 8a, 8b Connection pad 9a, 9b Insulating film 11a, 11b Protective film 14a, 14b Wiring 15a, 15b Columnar electrode 16a, 16b Sealing film 17a, 17b Solder ball 18 Insulating film 20 Wiring 22 Connection pad 23, 24 Underfill material 25 Bonding wire 26 Sealing material

Claims (13)

  A semiconductor device in which a plurality of semiconductor structures having a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate are stacked on the substrate in order of increasing size of the semiconductor substrate from the substrate side. The lowermost semiconductor structure is mounted on the substrate with the external connection electrodes connected to the upper connection pads of the substrate, and at least one semiconductor structure excluding the uppermost semiconductor structure An upper layer wiring is provided on the semiconductor structure, and a semiconductor structure mounted on top of the semiconductor structure is connected to the upper layer wiring. The upper layer connection pad connected to the upper layer wiring and the substrate are connected via a bonding wire. A semiconductor device characterized by being connected.   2. The semiconductor device according to claim 1, wherein the lower semiconductor structure includes an insulating film provided between the semiconductor substrate, the upper layer wiring, and the upper layer connection pad.   2. The semiconductor according to claim 1, wherein each of the semiconductor structures includes a columnar electrode as the external connection electrode and a sealing film covering an outer peripheral surface of the columnar electrode. apparatus.   In the invention according to claim 3, the semiconductor structure in the lowermost layer has a solder ball provided under the columnar electrode, and the solder ball is bonded to the first connection pad of the substrate. A featured semiconductor device.   4. The semiconductor structure according to claim 3, wherein the upper semiconductor structure has a solder ball provided below the columnar electrode, and the solder ball is bonded to a connection pad portion of an upper wiring of the lower semiconductor structure. A semiconductor device which is characterized by being made.   2. The semiconductor device according to claim 1, wherein there are a plurality of the semiconductor structures other than the lowest layer.   In the first aspect of the present invention, a plurality of lower layer connection pads are provided to be connected to the first and second upper layer connection pads under the substrate, and solder balls are provided under the lower layer connection pads. A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, wherein the highest point of the bonding wire is located lower than the upper surface of the uppermost semiconductor structure.   The semiconductor device according to claim 8, wherein a sealing material is provided on the substrate including the plurality of semiconductor structures and the bonding wires.   10. The semiconductor device according to claim 9, wherein the upper surface of the sealing material is flush with the upper surface of the uppermost semiconductor structure. A semiconductor device in which a plurality of semiconductor structures having a semiconductor substrate and external connection electrodes provided under the semiconductor substrate are stacked on the substrate in order of increasing size of the semiconductor substrate from the substrate side, The lowermost semiconductor structure is mounted on the substrate with its external connection electrodes connected to the upper layer connection pads of the substrate, and on at least one semiconductor structure excluding the uppermost semiconductor structure. An upper layer wiring is provided, a semiconductor structure mounted on top of the semiconductor structure is connected to the upper layer wiring, and an upper layer connection pad connected to the upper layer wiring and the substrate are connected via a bonding wire A method of manufacturing a semiconductor device having a structure,
When manufacturing the lower semiconductor structure, forming an insulating film on a semiconductor substrate in a wafer state;
Forming the upper layer wiring and the upper layer connection pad on the insulating film;
Cutting the semiconductor substrate in a wafer state to obtain a plurality of lower semiconductor structures.   In the invention according to claim 11, when manufacturing the lower semiconductor structure, the semiconductor substrate in the wafer state is ground to form a thickness of the semiconductor substrate in the wafer state before forming the insulating film. A method for manufacturing a semiconductor device, comprising a step of thinning.   13. The support plate according to claim 12, wherein the lower surface side of the semiconductor substrate in the wafer state is finally removed after the semiconductor substrate in the wafer state is ground and before the insulating film is formed. A method of manufacturing a semiconductor device, comprising a step of bonding to a semiconductor device.

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