JP2002289769A - Stacked semiconductor device and its manufacturing method - Google Patents

Stacked semiconductor device and its manufacturing method

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Publication number
JP2002289769A
JP2002289769A JP2001087012A JP2001087012A JP2002289769A JP 2002289769 A JP2002289769 A JP 2002289769A JP 2001087012 A JP2001087012 A JP 2001087012A JP 2001087012 A JP2001087012 A JP 2001087012A JP 2002289769 A JP2002289769 A JP 2002289769A
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Japan
Prior art keywords
wiring
semiconductor device
conductor
film
surface
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Withdrawn
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JP2001087012A
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Japanese (ja)
Inventor
Hiroaki Fujimoto
Toru Nomura
博昭 藤本
徹 野村
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP2001087012A priority Critical patent/JP2002289769A/en
Publication of JP2002289769A publication Critical patent/JP2002289769A/en
Application status is Withdrawn legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

PROBLEM TO BE SOLVED: To make the entire device lightweight by making a structure for mounting a plurality of semiconductor elements on one wiring board in a stacked semiconductor device.
SOLUTION: The stacked semiconductor device is mounted with at least two semiconductor elements on a wiring board 10 to constitute one package CSP, the upper face peripheral part of a sealing resin 15 has a cutting part 17 by grinding, and the stacked semiconductor device has the structure with a reduced volume. Thus, the lightweight of the laminated semiconductor device constituting the plurality of the semiconductor elements 12, 14 on one package can be realized. Furthermore, since a film wiring conductor 13 is interposed between a first semiconductor element 12 and a second semiconductor element 14, the whole laminated semiconductor device has flexibility and has the structure capable of dealing with stress due to thermal expansion.
COPYRIGHT: (C)2002,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は複数の機能の半導体素子を三次元方向に積層搭載した積層型半導体装置およびその製造方法に関するものであり、特に突起電極により各半導体素子をフリップチップ接続するとともに接続の信頼性の高い積層型半導体装置およびその製造方法に関するものである。 The present invention relates is related to a stacked semiconductor device and a manufacturing method thereof and a semiconductor element are laminated mounted on three-dimensional directions of a plurality of functions, each of the semiconductor elements as well as flip-chip connection in particular by the protruding electrode it relates reliable stacked semiconductor device and a manufacturing method thereof connected.

【0002】 [0002]

【従来の技術】近年、回路構成された1つの配線基板(キャリア基板)上に複数の機能の半導体素子を積層搭載し、1パッケージを構成する積層型半導体装置が開発されている。 In recent years, a semiconductor device of the plurality of functions is stacked and mounted on a single circuit board having a circuit configuration (carrier substrate), stacked semiconductor device constituting one package has been developed.

【0003】以下、開発されている従来の積層型半導体装置について、その代表構造として2つの半導体素子が基板上に積層搭載されたタイプの積層型半導体装置について説明する。 [0003] Hereinafter, the conventional stacked semiconductor device that has been developed, the two semiconductor devices will be described stacked semiconductor device of the type stacked and mounted on the substrate as a representative structure.

【0004】図9は従来の積層型半導体装置の構成を示す断面図である。 [0004] FIG. 9 is a sectional view showing the structure of a conventional stacked semiconductor device.

【0005】図9に示すように、従来の積層型半導体装置は、配線電極1a,1bおよび底面に端子電極2を有した配線基板3と、配線基板3上に樹脂4を介してその表面側が配線基板3と対向してフリップチップ接続された第1の半導体素子5と、第1の半導体素子5の裏面上に接着剤6を介してその表面側を上にして搭載された第2の半導体素子7を有し、第1の半導体素子5はその表面の電極パッド5aに設けた突起電極5bが配線基板3 [0005] As shown in FIG. 9, the conventional stacked semiconductor device, the wiring electrode 1a, and the wiring board 3 having the terminal electrodes 2 and 1b and a bottom surface, its surface on the wiring board 3 via the resin 4 a first semiconductor element 5 flip chip connected so as to face the wiring board 3, a second semiconductor which the surface mounted facing upward with an adhesive 6 on the back surface of the first semiconductor element 5 It has a device 7, the first semiconductor element 5 projecting electrodes 5b wiring board 3 provided on the electrode pads 5a of the surface
の配線電極1aと接続し、第2の半導体素子7はその表面の電極パッド7aが配線基板3の配線電極1bと金属細線8で接続され、配線基板3の上面領域が絶縁性の封止樹脂9で封止された構造である。 Of connected to the wiring electrode 1a, the second semiconductor element 7 the electrode pad 7a on its surface is connected to the wiring electrode 1b and the metal thin wires 8 of the wiring board 3, the upper surface region of the wiring board 3 is an insulating sealing resin a sealed structure 9.

【0006】また配線基板3上に搭載された半導体素子は、メモリー素子、ロジック素子などの複数の種類の半導体素子であり、1パッケージで多機能素子による高機能型の半導体装置である。 [0006] semiconductor element mounted on the wiring board 3, a memory device, a plurality of kinds of semiconductor devices such as logic devices, a high-performance semiconductor device according to the multi-function device in one package.

【0007】次に従来の積層型半導体装置の製造方法について図面を参照しながら説明する。 [0007] Next will be described with reference to the drawings a method for manufacturing the conventional stacked semiconductor device. 図10,図11は従来の積層型半導体装置の製造方法を示す工程ごとの主要な断面図である。 10, FIG. 11 is a principal sectional view of each process showing a manufacturing method of the conventional stacked semiconductor device.

【0008】まず図10(a)に示すように、第1の半導体素子5の表面の複数の電極パッド5a上に突起電極(バンプ)5bを各々形成する。 [0008] First, as shown in FIG. 10 (a), each forming a protruding electrode (bump) 5b on the electrode pads 5a of the surface of the first semiconductor element 5. この突起電極の形成はメッキバンプ、ワイヤーボンド法によるスタッドバンプなどの工法で形成される。 The formation of the protruding electrodes are plated bumps are formed by method such as stud bumps according wire bonding method.

【0009】次に図10(b)に示すように、配線基板3の上面に対してシート状の異方性導電性(ACF)の樹脂4を供給するとともに、第1の半導体素子5をその突起電極5bの面を配線基板3の上面に対向させる。 [0009] Next, as shown in FIG. 10 (b), supplies the resin 4 of the sheet-like anisotropic conductive to the upper surface of the wiring board 3 (ACF), the first semiconductor element 5 that is opposed surfaces of the projection electrodes 5b on the upper surface of the wiring board 3. ここで配線基板への樹脂4の供給は配線基板3の配線電極1aを覆うように供給するものであり、シート状以外に液状の樹脂をポッティングにより供給してもよい。 Here the supply of the resin 4 on the wiring board is to supply so as to cover the wiring electrode 1a of the wiring board 3, the liquid resin may be supplied by potting in addition to a sheet.

【0010】次に図10(c)に示すように、第1の半導体素子5を配線基板3の上面に加圧して、第1の半導体素子5の突起電極5bと配線基板3の配線電極1aとを接続する。 [0010] Next, as shown in FIG. 10 (c), first semiconductor element 5 by pressurizing the upper surface of the wiring board 3, the first protruding electrode 5b and the wiring electrodes 1a of the wiring board 3 of the semiconductor element 5 to connect the door.

【0011】次に図10(d)に示すように、第2の半導体素子7を配線基板3に搭載した第1の半導体素子5 [0011] Next, as shown in FIG. 10 (d), the first semiconductor device equipped with the second semiconductor element 7 on the wiring board 3 5
の裏面(背面側)に対して接着剤6により、その裏面で接着固定する。 The adhesive 6 with respect to the rear surface (back side), is bonded and fixed at the rear surface thereof.

【0012】次に図11(a)に示すように、搭載した第2の半導体素子7の電極パッド7aと配線基板3の上面の配線電極1bとを金属細線8により電気的に接続する。 [0012] Next, as shown in FIG. 11 (a), the wiring electrode 1b of the upper surface of the electrode pad 7a and the wiring board 3 of the second semiconductor element 7 mounted is electrically connected by metal thin wires 8.

【0013】そして図11(b)に示すように、配線基板3の上面領域を絶縁性の封止樹脂9で封止することにより積層型半導体装置を形成するものである。 [0013] Then, as shown in FIG. 11 (b), is to form a laminated-type semiconductor device by the upper surface region of the wiring board 3 are sealed with the sealing resin 9 insulating.

【0014】以上のような各工程により、従来は配線基板上に2つの半導体素子を搭載した1パッケージタイプの積層型半導体装置を実現していた。 The [0014] above steps, such as, has been conventionally realized stacked semiconductor device of one package type equipped with two semiconductor elements on the wiring substrate.

【0015】 [0015]

【発明が解決しようとする課題】しかしながら前記従来の積層型半導体装置では、2つの半導体素子を1枚の配線基板上に搭載する構造であるため、配線基板の上面領域へ付加される構成部材が多く、熱膨張によって配線基板の反り、または熱膨張、反りによる半導体素子と配線基板の配線電極との接続部分へのダメージが懸念されていた。 In [0006] However the conventional stacked semiconductor device, since a structure for mounting two semiconductor elements on one of the wiring board, the components to be added to the upper surface region of the wiring board many, warp of the wiring substrate by thermal expansion or thermal expansion, damage to the connecting portion between the semiconductor element and the wiring electrodes of the wiring board due to warping has been a concern.

【0016】すなわち熱膨張によって、積層型半導体装置を構成する配線基板、半導体素子、突起電極などの各構成部材の熱膨張係数の差から、半導体素子が膨張した場合、パッケージ内部で微動することにより、半導体素子と配線基板の配線電極との接続部分が破断する恐れがあった。 [0016] That is due to thermal expansion, the wiring substrate constituting the stacked semiconductor device, a semiconductor element, the difference in thermal expansion coefficients of the components, such as protruding electrodes, when the semiconductor device is inflated by fine movement inside the package the connection portion between the wiring electrode of the semiconductor element and the wiring board there is a risk of rupture. 従来は積層型半導体装置を構成する配線基板、 Wiring board prior to forming the laminated type semiconductor device,
半導体素子、突起電極などの各構成部材の熱膨張係数を近似するようにしたり、または熱膨張や、それによる積層型半導体装置自体の反りに対抗できる構造にするなどして対策していたが、今後は2つの半導体素子の搭載にとどまらず、3つ以上の半導体素子を1つの配線基板上に搭載して1パッケージを構成する傾向にあるため、根本的な積層型半導体装置の構造の開発が必要とされていた。 Semiconductor element, or so as to approximate the thermal expansion coefficient of the components, such as protruding electrodes, or or thermal expansion, it had been measures, such as by a structure that can counter the warping of the stacked semiconductor device itself by it, future not only the mounting of the two semiconductor elements, since there is a tendency to form one package by mounting three or more semiconductor elements on one wiring board, the development of the structure of the underlying stacked semiconductor device It has been required.

【0017】さらに1パッケージで複数の半導体素子を搭載しているため、全体として体積が増加し、その重量も増加するため、軽量化を実現した積層型半導体装置が要望されていた。 [0017] Due to the further mounting a plurality of semiconductor elements in one package, the whole volume increases as, therefore the weight also increases, stacked semiconductor device in which lighter has been demanded.

【0018】本発明は前記した従来の課題を解決するものであり、2つ以上の半導体素子を配線基板上に3次元で搭載して1パッケージを構成した積層型半導体装置において、各半導体素子と配線基板の配線電極との接続部分の接続の信頼性を高め、かつ軽量化を図ることができる積層型半導体装置およびその製造方法を提供することを目的とする。 [0018] The present invention has been made to solve the conventional problems described above, in the stacked type semiconductor device which constitute one package of two or more semiconductor devices mounted in three dimensions on a wiring substrate, and the semiconductor elements enhance the reliability of the connection of the connecting portion of the wiring electrodes of the wiring substrate, and an object thereof to provide a stacked semiconductor device and a manufacturing method thereof can be made lighter.

【0019】 [0019]

【課題を解決するための手段】前記従来の課題を解決するために本発明の積層型半導体装置は、配線電極を有した配線基板と、前記配線基板上に樹脂を介してその表面側が前記配線基板と対向してフリップチップ接続された第1の半導体素子と、前記第1の半導体素子の裏面上にフィルム配線導体を介してその表面側が前記第1の半導体素子の裏面と対向してフリップチップ接続された第2 The stacked semiconductor device of the Means for Solving the Problems The present invention to solve the conventional problems, a wiring board having a wiring electrode, the surface side of the wiring through the resin on the wiring substrate the first semiconductor device, the first of the front side through the film wiring conductor on the back surface of the semiconductor element of the first semiconductor device of the back surface opposed to a flip chip that is flip-chip connected to the substrate and a counter the second, which is connected
の半導体素子との少なくとも2つの半導体素子を有し、 At least two semiconductor elements of the semiconductor element,
前記第1の半導体素子はその表面に設けた突起電極が前記配線基板の配線電極と接続し、前記第2の半導体素子はその表面に設けた突起電極が前記フィルム配線導体の配線導体と接続し、前記配線導体は前記配線基板の配線電極と接続し、前記配線基板の上面領域は封止樹脂で封止されている積層型半導体装置であって、研削によって前記封止樹脂の上面周辺部の体積が減じられている積層型半導体装置である。 Said first semiconductor device is connected protruding electrodes provided on the surface of the wiring electrodes of the wiring substrate, the second semiconductor element has protruding electrodes provided on the surface thereof connected to the wiring conductor of the film wiring conductor the wiring conductor is connected to the wiring electrodes of the wiring substrate, the top surface region of the wiring board is a multilayer semiconductor device encapsulated with a sealing resin, the upper surface peripheral portion of the sealing resin by grinding a stacked type semiconductor device volume is reduced.

【0020】そして具体的には、フィルム配線導体は配線導体を軟性樹脂で挟んだ構造である積層型半導体装置である。 [0020] Then Specifically, film wiring conductor is stacked semiconductor device has a structure sandwiched between flexible resin wiring conductors.

【0021】また、配線基板は、上面に配線電極と、下面に前記上面の配線電極と接続した端子電極とを有した配線基板である積層型半導体装置である。 Further, the wiring substrate includes a wiring electrode on the upper surface, a stacked-type semiconductor device is a circuit board having a terminal electrode connected to the wiring electrode of the upper surface to the lower surface.

【0022】また、第1の半導体素子または第2の半導体素子の面積と配線基板の面積とは、前記配線基板の面積が大きい条件で略同等の大きさで構成されてチップサイズパッケージを構成している積層型半導体装置である。 Further, the area and the area of ​​the wiring substrate of the first semiconductor element and the second semiconductor element, is composed of substantially the same size with a large area condition of the wiring substrate to constitute the chip size package and it has a stacked-type semiconductor device.

【0023】前記構成の通り、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板の配線電極との接続部分が破断することを防止し、接続の信頼性を高めることができる。 [0023] As the configuration, the second or more stacked semiconductor devices, because they are stacked and mounted through the configured film wiring conductors soft resin, by the thermal expansion of the stacked semiconductor device, a semiconductor element If There inflated, even if the fine movement within the package, to prevent to move in conjunction also connected portion with its expansion movement, the connection portion between the wiring electrode of the semiconductor element and the wiring board to break the connection it is possible to improve the reliability. またフィルム配線導体は配線導体がその表裏面側が軟性樹脂で挟まれた3層構造であるため、内層の配線導体自体の固定は避けられ、熱膨張の微動に対応できるものである。 Since film wiring conductor its front and back surface side of the wiring conductor is a three-layer structure sandwiched between the soft resins, fixed inner wiring conductor itself are avoided, it is those that can correspond to tremor thermal expansion. また半導体素子と半導体素子との間には軟性樹脂で構成されたフィルム配線導体が介在しているので、積層型半導体装置全体としてフレキシブル性を有し、熱膨張による応力に対応できる構造である。 Since film wiring conductor made of a soft resin between the semiconductor element and the semiconductor element are interposed, has flexibility as a whole stacked semiconductor device, a structure to accommodate the stress due to thermal expansion.

【0024】さらに封止樹脂の上面の周辺部は封止樹脂が研削で除去されて、封止樹脂全体の体積が減じられているため、複数の半導体素子を1パッケージに構成した積層型半導体装置の軽量化を実現できるものである。 Furthermore periphery of the upper surface of the sealing resin is molding resin is removed by grinding, the volume of the whole sealing resin is reduced, the stacked semiconductor device constituting a plurality of semiconductor elements in one package in which the weight reduction can be achieved.

【0025】また本発明の積層型半導体装置の製造方法は、上面に配線電極と、下面に前記上面の配線電極と接続した端子電極とを有した配線基板に対して、樹脂を介してその表面の電極パッドに突起電極が形成された第1 [0025] method of manufacturing a stacked semiconductor device of the present invention, a wiring electrode on the upper surface, the wiring board having a terminal electrode connected to the wiring electrode of the upper surface to the lower surface, the surface through the resin first the electrode pad protruding electrodes formed
の半導体素子をフリップチップ接続し、前記突起電極と前記配線基板の配線電極とを接続する第1の工程と、前記第1の半導体素子の裏面および前記配線基板上面に一体でフィルム配線導体を接着するとともに、前記フィルム配線導体の配線導体の外方端部を前記配線基板の配線電極と接続する第2の工程と、前記第1の半導体素子の裏面に対して、前記フィルム配線導体を介してその表面の電極パッドに突起電極が形成された第2の半導体素子をフリップチップ接続し、前記突起電極と前記フィルム配線導体の配線導体の内方端部とを接続する第3の工程と、前記配線基板の上面領域を封止樹脂で封止する第4 The semiconductor device is flip-chip connected, bonding the first step and the film wiring conductor integrally with the back surface and the wiring substrate upper surface of the first semiconductor device for connecting the wiring electrodes of the wiring board and the projecting electrodes while, the second step of the outer end portion of the wiring conductor film wiring conductor connected to the wiring electrodes of the wiring board, the rear surface of the first semiconductor device, through the film wiring conductor a third step of the second semiconductor element electrode pad protruding electrode surface is formed is flip-chip connected, connects the inner end of the wiring conductor and said protruding electrode the film conductor, wherein 4 that the top surface area of ​​the wiring substrate are sealed with a sealing resin
の工程と、前記配線基板の上面に形成した封止樹脂の上面周辺部に対して研削処理を行い、前記封止樹脂の上面周辺部の体積を減じる第5の工程とよりなる積層型半導体装置の製造方法である。 And steps, the performs grinding processing with respect to the upper surface peripheral portion of the sealing resin formed on the upper surface of the wiring board, the more the fifth step of reducing the volume of the upper surface peripheral portion of the sealing resin stacked semiconductor device it is a method of manufacture.

【0026】また本発明の積層型半導体装置の製造方法は、その上面に複数の半導体素子が個々に搭載されるもので、また上面に個々の半導体素子に対応した配線電極が設けられ、下面には上面の配線電極と基板内部で接続した端子電極が設けられ、個々の半導体素子単位ごとに分割され得る構造の1枚の大型の配線基板に対して、樹脂を介してその表面の電極パッドに突起電極が形成された第1の半導体素子をフリップチップ接続し、前記突起電極と前記配線基板の配線電極とを接続する第1の工程と、前記第1の半導体素子の裏面および前記配線基板上面に一体でフィルム配線導体を接着するとともに、前記フィルム配線導体の配線導体の外方端部を前記配線基板の配線電極と接続する第2の工程と、前記第1の半導体素子の裏面に対し [0026] method of manufacturing a stacked semiconductor device of the present invention, the upper surface intended plurality of semiconductor elements are mounted individually, also wiring electrodes corresponding to individual semiconductor elements provided on the upper surface, a lower surface It is provided terminal electrodes connected by the wiring electrode and the substrate inside the top, relative to one large wiring board structure that may be divided into individual semiconductor devices unit, the electrode pads of the surface through the resin a first semiconductor element projecting electrodes is formed is flip-chip connected, a first step of connecting the wiring electrodes of the wiring board and the protruding electrodes, the back surface and the wiring substrate upper surface of the first semiconductor element thereby bonding the film wiring conductor integrally with, a second step of connecting the outer end of the wiring conductor of the film conductor and the wiring electrodes of the wiring board with respect to the rear surface of the first semiconductor element 、前記フィルム配線導体を介してその表面の電極パッドに突起電極が形成された第2の半導体素子をフリップチップ接続し、前記突起電極と前記フィルム配線導体の配線導体の内方端部とを接続する第3 , Said second semiconductor device via a film wiring conductor electrode pads protruding electrodes of the surface formed by flip-chip connected, connects the inner end of the wiring conductor and said protruding electrode said film wiring conductor third to
の工程と、前記配線基板の上面領域を封止樹脂で封止する第4の工程と、前記配線基板に対して、個々の積層型半導体装置に切断分離するとともに、前記配線基板の上面に形成した封止樹脂の上面周辺部に対して研削処理を行い、前記封止樹脂の上面周辺部の体積を減じる第5の工程とよりなる積層型半導体装置の製造方法である。 And step, a fourth step for sealing with the sealing resin to the upper surface region of the wiring board, with respect to the wiring board, as well as cut and separated into individual stacked semiconductor device, formed on the upper surface of the wiring substrate It was performed grinding the upper surface peripheral portion of the sealing resin, wherein a method of manufacturing become more stacked semiconductor device and a fifth step of reducing the volume of the upper surface peripheral portion of the sealing resin.

【0027】そして具体的には、第1の半導体素子の裏面に対して、フィルム配線導体を介してその表面の電極パッドに突起電極が形成された第2の半導体素子をフリップチップ接続し、前記突起電極と前記フィルム配線導体の配線導体の内方端部とを接続する第3の工程では、 [0027] and specifically the rear surface of the first semiconductor device, the second semiconductor element projecting electrodes on the electrode pads of the surface is formed through a film wiring conductor flip chip connection, the in the third step of connecting the inner end of the wiring conductor of the bump electrode the film conductor,
第2の半導体素子を前記フィルム配線導体に対して加圧し、前記突起電極で前記フィルム配線導体のフィルム材を突き破って前記配線導体の内方端部とを接続する積層型半導体装置の製造方法である。 In the second pressurized semiconductor element to the film conductor, the method of fabricating the multilayer semiconductor device said at protruding electrode breaks through the film material of the film wiring conductor connecting the inner end of the wiring conductor is there.

【0028】また、第1の半導体素子の裏面および配線基板上面に一体でフィルム配線導体を接着するとともに、前記フィルム配線導体の配線導体の外方端部を前記配線基板の配線電極と接続する第2の工程では、配線導体を軟性樹脂で挟んだ構造のフィルム配線導体を用いる積層型半導体装置の製造方法である。 Further, the connecting as well as the adhesive film wiring conductor integrally with the back surface and the wiring substrate upper surface of the first semiconductor device, the outer end of the wiring conductor of the film conductor and the wiring electrodes of the wiring substrate the second step, the wiring conductor is a manufacturing method of a stacked semiconductor device using a film wiring conductor sandwiched by soft resin.

【0029】前記構成の通り、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板の配線電極との接続部分が破断することを防止し、接続の信頼性を高めることができる構造を実現できる。 [0029] As the configuration, the second or more stacked semiconductor devices, because they are stacked and mounted through the configured film wiring conductors soft resin, by the thermal expansion of the stacked semiconductor device, a semiconductor element If There inflated, even if the fine movement within the package, to prevent to move in conjunction also connected portion with its expansion movement, the connection portion between the wiring electrode of the semiconductor element and the wiring board to break the connection a structure that can increase the reliability can be realized. またフィルム配線導体に対して、半導体素子を突起電極を加圧して接続する場合においても、フィルム配線導体のフィルム材が外圧を吸収するため、下側の半導体素子への影響を解消し、安定に信頼性よくフリップチップ接続できるものである。 Also the film conductor, in case of connecting the semiconductor element projecting electrodes pressurized Also, because the film material of the film wiring conductor absorbs external pressure, to eliminate the influence of the lower semiconductor element, stable in which high reliability can flip chip bonding.

【0030】さらに一括成形後に個々の積層型半導体装置に切断分離する工程で、切断とともに封止樹脂の周辺部を研削するため、封止樹脂の上面の周辺部は封止樹脂が除去されて、封止樹脂全体の体積を減じることができ、軽量化を達成できるものである。 Furthermore in the process of cutting into individual stacked semiconductor device after batch molding, for grinding a peripheral portion of the sealing resin with cutting, the peripheral portion of the upper surface of the sealing resin is molding resin is removed, It can reduce the volume of the entire sealing resin, in which the weight can be achieved.

【0031】 [0031]

【発明の実施の形態】以下、本発明の積層型半導体装置およびその製造方法の一実施形態について説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a description will be given of an embodiment of a stacked semiconductor device and a manufacturing method thereof of the present invention.

【0032】まず本実施形態の積層型半導体装置について図面を参照しながら説明する。 Firstly it will be described with reference to the accompanying drawings stacked semiconductor device of the present embodiment. 図1は本実施形態の積層型半導体装置を示す主要な断面図である。 Figure 1 is a major cross-sectional view of a stacked type semiconductor device of the present embodiment.

【0033】本実施形態の積層型半導体装置は、配線電極を有した配線基板と、その配線基板上にその表面側が配線基板と対向してフリップチップ接続された第1の半導体素子と、その第1の半導体素子の裏面上にフィルム配線導体を介してその表面側が第1の半導体素子の裏面と対向してフリップチップ接続された第2の半導体素子との少なくとも2つの半導体素子を有した積層型半導体装置であって、第1の半導体素子はその表面に設けた突起電極が配線基板の配線電極と接続し、配線基板と対向してフリップチップ接続された第1の半導体素子以外の半導体素子はその表面に設けた突起電極でフィルム配線導体を介してフリップチップ接続され、そのフィルム配線導体の配線導体は配線基板の配線電極と接続して1パッケージでチップ The stacked semiconductor device of the present embodiment, a wiring board having a wiring electrode, a first semiconductor element is flip-chip connected to face the surface side of the wiring board to the circuit board, the first its surface is laminated with at least two semiconductor elements and the second semiconductor element is flip-chip connected to face the back surface of the first semiconductor element through a film wiring conductor on the back surface of the first semiconductor element a semiconductor device, the first semiconductor device is connected to the wiring electrode of the protruding electrodes is the wiring board provided on the surface thereof, the semiconductor device other than the first semiconductor element is flip-chip connected to the wiring board and the opposite is flip-chip connected through a film wiring conductor protruding electrodes provided on the surface thereof, the chip wiring conductor of the film wiring conductor in one package by connecting the wiring electrodes of the wiring substrate 層構造を有するものである。 And it has a layer structure.

【0034】具体的には図1に示すように、本実施形態の積層型半導体装置は、上面(表面)に配線電極10 [0034] Specifically, as shown in FIG. 1, a stacked semiconductor device of the present embodiment, the wiring electrodes 10 on the upper surface (surface)
a,10bを有し、下面(裏面)に各配線電極10a, a, it has a 10b, the wiring electrodes 10a on the lower surface (back surface),
10bと基板内部で電気的に接続した端子電極を有した配線基板10と、配線基板10上に異方性導電性(AC 10b and a wiring board 10 having a terminal electrode electrically connected inside the substrate, the anisotropic conductive on the wiring board 10 (AC
F)の樹脂11を介してその表面側が配線基板10と対向してフリップチップ接続されたマイコン素子などの第1の半導体素子12と、第1の半導体素子12の裏面上にフィルム配線導体13を介してその表面側が第1の半導体素子12の裏面と対向してフリップチップ接続されたメモリー素子などの第2の半導体素子14との少なくとも2つの半導体素子を有した積層型半導体装置であって、第1の半導体素子12はその表面の電極パッド12 A first semiconductor element 12 such as a flip-chip connected the microcomputer device the surface side is opposed to the wiring board 10 via the resin 11 F), the film wiring conductors 13 on the back surface of the first semiconductor element 12 a stacked type semiconductor device having at least two semiconductor elements and the second semiconductor element 14 of the surface side and back surface opposed to flip-chip connected memory element of the first semiconductor device 12 via, the first semiconductor element 12 is an electrode pad 12 of the surface
a上に設けた突起電極12bが配線基板10の配線電極10aと接続し、第2の半導体素子14はその表面の電極パッド14a上に設けた突起電極14bがフィルム配線導体13の配線導体13aの内方端部と接続し、その配線導体13aの外方端部は配線基板10の配線電極1 Connected to the protruding electrodes 12b are wiring electrodes 10a of the wiring substrate 10 provided on a, the second semiconductor element 14 protruding electrodes 14b provided on the electrode pads 14a of the surface of the wiring conductor 13a of the film wiring conductor 13 connected to the inner end, an outer end of the wiring conductor 13a is wire electrode 1 of the wiring board 10
0bと接続した構造である。 0b to be a structure connection. そして第2の半導体素子1 The second semiconductor element 1
4の裏面が露出されて配線基板10の上面領域は封止樹脂15で封止されているものである。 Upper surface region of the wiring board 10 4 of the rear surface is exposed is what is sealed with a sealing resin 15.

【0035】また、フィルム配線導体13は、配線導体13aをエポキシ系樹脂、エラストマー、シリコーン樹脂などの軟性樹脂によるフィルム材13bで挟んだ構造であり、各素子間の衝撃を吸収している構造である。 Further, film wiring conductor 13, an epoxy resin wiring conductors 13a, elastomers are sandwiched by the film material 13b by soft resin such as silicone resin, in the structure that absorbs impact between the elements is there.

【0036】そして本実施形態の積層型半導体装置は、 [0036] The stacked semiconductor device of this embodiment,
第1の半導体素子12または第2の半導体素子14の面積と配線基板10の面積とは、配線基板10の面積が大きい条件で略同等の大きさで構成されてCSP(チップサイズパッケージ)を構成しているものである。 And the area of ​​the wiring substrate 10 area of ​​the first semiconductor element 12 or the second semiconductor element 14, with a large area condition of the wiring substrate 10 is composed of substantially the same size constituting the CSP (chip size package) it is what you are.

【0037】以上、本実施形態の積層型半導体装置は、 The above, stacked semiconductor device of this embodiment,
少なくとも2つ以上の半導体素子を配線基板上に搭載して1パッケージCSPを構成したものであり、特に2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体13を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板10の配線電極10a,10bとの接続部分が破断することを防止し、接続の信頼性を高めることができる。 At least two or more are those in which the semiconductor device constitutes a package CSP is mounted on the wiring board, the semiconductor element, especially a stack of more than two eyes through the film wiring conductor 13 made of a soft resin because they are stacked and mounted Te, the thermal expansion of the stacked semiconductor device, when the semiconductor device is inflated, even if the fine movement within the package, to move in conjunction also connected portion with its expansion movement, the semiconductor element the wiring electrode 10a of the wiring substrate 10, to prevent the connection part between 10b breaks, it is possible to improve the reliability of the connection. またフィルム配線導体13は配線導体13aがその表裏面側が軟性樹脂によるフィルム材13 The film wiring conductor 13 is film material wiring conductor 13a is by its front and back surfaces are soft resin 13
bで挟まれた3層構造であるため、内層の配線導体13 Since a three-layer structure sandwiched by b, the inner layer of the wiring conductor 13
a自体の固定は避けられ、熱膨張の微動に対応できるものである。 Fixing of a per se are avoided, it is able to handle the fine movement of the thermal expansion. また半導体素子と半導体素子との間には軟性樹脂で構成されたフィルム配線導体13が介在しているので、積層型半導体装置全体としてフレキシブル性を有し、熱膨張による応力に対応できる構造である。 Since film wiring conductor 13 made of a soft resin between the semiconductor element and the semiconductor element are interposed, it has flexibility as a whole stacked semiconductor device, is a structure that can correspond to the stress due to thermal expansion .

【0038】また第2の半導体素子14の裏面を露出させて配線基板10の上面領域を封止樹脂15で封止しているので、第2の半導体素子14に発熱性の半導体素子を採用したとしても、放熱効果を高めることができる。 [0038] Since sealing the top region in the sealing resin 15 of the wiring substrate 10 to expose the back surface of the second semiconductor element 14, employing the exothermic semiconductor element to the second semiconductor element 14 as well, it is possible to enhance the heat dissipation effect.
これは半導体素子の裏面を封止樹脂外に露出させるためにはフリップチップ構造が適しているものであり、本実施形態のように基板上に搭載するすべての半導体素子がフリップチップ接続構造を有しているため、放熱効果を高めるに適したパッケージ構造である。 This is to expose the back surface of the semiconductor element to the outside of the sealing resin are those flip-chip structure is suitable, closed all the semiconductor device flip-chip connection structure for mounting on a substrate as in this embodiment since it is a package structure suitable for enhancing the heat dissipation effect.

【0039】次に本実施形態の積層型半導体装置の製造方法について図面を参照しながら説明する。 [0039] Next the production method of the stacked semiconductor device of the present embodiment will be described with reference to the drawings. 図2,図3 FIGS. 2 and 3
は本実施形態の積層型半導体装置の製造方法を示す工程ごとの主要な断面図である。 Is a major cross-sectional view of each process showing a manufacturing method of a stacked semiconductor device of the present embodiment.

【0040】まず図2(a)に示すように、第1の半導体素子12の表面の複数の電極パッド12a上に突起電極(バンプ)12bを各々形成する。 [0040] First, as shown in FIG. 2 (a), each forming a protruding electrode (bump) 12b on a plurality of electrode pads 12a of the surface of the first semiconductor element 12. この突起電極の形成はメッキバンプ、ワイヤーボンド法によるスタッドバンプなどの工法で形成される。 The formation of the protruding electrodes are plated bumps are formed by method such as stud bumps according wire bonding method.

【0041】次に図2(b)に示すように、配線基板1 [0041] Then, as shown in FIG. 2 (b), the wiring board 1
0の上面に対してシート状の異方性導電性(ACF)の樹脂11を供給するとともに、マイコン(ロジック)素子などの第1の半導体素子12をその突起電極12bの面を配線基板10の上面に対向させる。 Supplies resin 11 of a sheet-like anisotropic conductive (ACF) to the upper surface of 0, the microcomputer (logic) elements of the first semiconductor element 12 and the projection electrodes 12b faces the wiring board 10, such as It is opposed to the top surface. ここで配線基板10への樹脂11の供給は配線基板10の配線電極10 Here the supply of the resin 11 on the wiring substrate 10 is wire electrodes 10 of the wiring board 10
aを覆うように供給するものであり、シート状以外に液状の樹脂をポッティングにより供給してもよい。 Is intended to supply to cover the a, a liquid resin may be supplied by potting in addition to a sheet. またこの樹脂11の配線基板10と第1の半導体素子12との間隙への充填は、前述のようにシート状の樹脂11を予め配線基板10上に供給する以外、第1の半導体素子1 The filling of the gap between the wiring substrate 10 of the resin 11 and the first semiconductor element 12, except that supplied to the advance on the wiring board 10 of the sheet-like resin 11, as described above, the first semiconductor element 1
2と配線基板10の配線電極10aとを接続した後、注入によって充填形成してもよい。 2 and after connecting the wiring electrodes 10a of the wiring board 10 may be filled formed by implantation. この後注入による充填では、絶縁性の樹脂でよい。 The filling by injection after this may be an insulating resin.

【0042】次に図2(c)に示すように、第1の半導体素子12を配線基板10の上面に加圧して、第1の半導体素子12の突起電極12bと配線基板10の配線電極10aとを接続する。 [0042] Next, as shown in FIG. 2 (c), pressurizes the first semiconductor element 12 on the upper surface of the wiring board 10, wiring electrodes 10a of the bump electrode 12b and the wiring substrate 10 of the first semiconductor element 12 to connect the door. なお、素子接続、固定後において、第1の半導体素子12の厚みを薄厚にするため、グラインダーによる研削、さらにポリッシングを行い、素子厚を薄くする工程を付加してもよい。 It is to be noted that the device connection, after fixing, to the thickness of the first semiconductor element 12 to the thin, grinding by a grinder, further subjected to polishing may be added a step of thinning the element thickness.

【0043】次に図2(d)に示すように、第1の半導体素子12の裏面および配線基板10上面に一体でフィルム配線導体13を接着する。 [0043] Then, as shown in FIG. 2 (d), the adhesive film wiring conductor 13 integrally with the back surface and the wiring substrate 10 upper surface of the first semiconductor element 12. この場合、配線導体13 In this case, the wiring conductor 13
aの表裏面を軟性樹脂によるフィルム材13bで挟んだ3層構造のフィルム配線導体を用いるものである。 The front and back surfaces of a is to use a film wiring conductor of a three-layer structure is sandwiched between the film material 13b by soft resin. またフィルム配線導体13には接着性を持たせるか、または加熱してフィルム配線導体13を軟化させて接着する。 Also the film wiring conductor 13 or to have adhesion, or heated to soften the film wiring conductor 13 is bonded.

【0044】さらに図3(a)に示すように、フィルム配線導体の接着とともに、フィルム配線導体13の配線導体13aの外方端部を配線基板10の配線電極10b [0044] As further shown in FIG. 3 (a), together with the adhesive film wiring conductor, the wiring of the outer end portion of the wiring board 10 of the wiring conductor 13a of the film wiring conductor 13 the electrode 10b
と接続する。 To connect with.

【0045】次に図3(b)に示すように、第1の半導体素子12の裏面に対して、フィルム配線導体13を介してその表面の電極パッド14aに突起電極14bが形成されたメモリー素子などの第2の半導体素子14をフリップチップ接続し、突起電極14bとフィルム配線導体13の配線導体13aの内方端部とを接続する。 [0045] Then, as shown in FIG. 3 (b), the rear surface of the first semiconductor element 12, a memory element projecting electrodes 14b to the electrode pad 14a of the surface through the film wiring conductor 13 are formed a second semiconductor element 14, such as a flip-chip connected, connects the inner end portion of the wiring conductor 13a of the bump electrode 14b and the film wiring conductor 13. この場合、第2の半導体素子14をフィルム配線導体13に対して加熱状態で加圧し、突起電極14bでフィルム配線導体13のフィルム材13bを突き破って配線導体1 In this case, pressurized in a heated state to the second semiconductor element 14 to the film wiring conductor 13, breaks through the film material 13b of the film wiring conductor 13 protruding electrodes 14b wiring conductor 1
3aの内方端部とを接続するものである。 3a is used to connect the inner end of. また、ここでフィルム配線導体13に対して、第2の半導体素子14 Further, where the film wiring conductor 13, the second semiconductor element 14
の突起電極14bを加圧して接続するにおいても、フィルム配線導体13のフィルム材13bが外圧を吸収するため、下側の第1の半導体素子12への影響を解消し、 Also in connecting the protruding electrode 14b is pressurized, since the film material 13b of the film wiring conductor 13 absorbs the external pressure, to eliminate the influence of the first semiconductor element 12 of the lower,
安定に信頼性よくフリップチップ接続できるものである。 Those capable of stably reliably flip chip bonding. なお、素子接続、固定後において、第2の半導体素子14の厚みを薄厚にするため、グラインダーによる研削、さらにポリッシングを行い、素子厚を薄くする工程を付加してもよい。 It is to be noted that the device connection, after fixing, to the thickness of the second semiconductor element 14 to the thin, grinding by a grinder, further subjected to polishing may be added a step of thinning the element thickness.

【0046】そして図3(c)に示すように、配線基板10の上面領域を絶縁性のエポキシ樹脂などの封止樹脂15で封止する。 [0046] Then, as shown in FIG. 3 (c), the upper surface region of the wiring board 10 is sealed with a sealing resin 15 such as an insulating epoxy resin. この樹脂封止においては、金型を用いたトランスファーモールド法やポッティング工法により封止できるものである。 In this resin sealing, in which can be sealed by a transfer molding method or a potting method using a mold. また樹脂封止では、第2の半導体素子14の裏面を露出させて配線基板10の上面領域を封止樹脂15で封止する。 In the resin sealing, the top surface area of ​​the wiring substrate 10 to expose the back surface of the second semiconductor element 14 is sealed with a sealing resin 15. この封止構造により、第2 This sealing structure, the second
の半導体素子14に発熱性の半導体素子を採用したとしても、放熱効果を高めることができる。 As was the semiconductor element 14 to the heat generation of the semiconductor element adopted, it is possible to enhance the heat dissipation effect.

【0047】以上、本実施形態の積層型半導体装置の製造方法では、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体13を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板10の配線電極1 The above, since the manufacturing method of a stacked semiconductor device of the present embodiment, the second or more stacked semiconductor devices, which are stacked and mounted through the film wiring conductor 13 made of a soft resin, by thermal expansion of the stacked semiconductor device, when the semiconductor device is inflated, even if the fine movement within the package, to move in conjunction also connected portion with its expansion movement, wiring electrode 1 of the semiconductor element and the wiring board 10
0a,10bとの接続部分が破断することを防止し、接続の信頼性を高めることができる構造を実現できる。 0a, to prevent the connection part between 10b breaks, the structure can be realized which can increase the reliability of the connection. またフィルム配線導体13に対して、半導体素子を突起電極を加圧して接続するにおいても、フィルム配線導体1 Further to the film wiring conductor 13, also in the semiconductor device for connecting the protruding electrode pressurizing, film wiring conductor 1
3のフィルム材13bが外圧を吸収するため、下側の半導体素子への影響を解消し、安定に信頼性よくフリップチップ接続できるものである。 Since the third film material 13b absorbs the external pressure, to eliminate the influence of the lower semiconductor element, those capable of stably reliably flip chip bonding.

【0048】また本実施形態の積層型半導体装置の製造方法では、基板上への各半導体素子の搭載、フィルム配線導体の形成、封止の各工程は、その上面に複数の半導体素子が個々に搭載されるもので、また上面に個々の半導体素子に対応した配線電極が設けられ、下面には上面の配線電極と基板内部で接続した端子電極が設けられ、 [0048] In the manufacturing method of the stacked semiconductor device of this embodiment, mounting of the semiconductor elements on a substrate, forming a film wiring conductor, each step of the sealing is independently plurality of semiconductor elements on its upper surface intended to be mounted, also the wiring electrodes corresponding to individual semiconductor devices formed on the upper surface, the lower surface terminal electrode is provided which is connected with the wiring electrode and the substrate inside the top surface,
個々の半導体素子単位ごとに分割され得る構造の1枚の大型の配線基板に対して各々行なうものであり、一括成形工法と称される量産に適した製造工法である。 Is intended to perform each against one large wiring board structure that may be divided into individual semiconductor elements units, a manufacturing method suitable for called mass production batch molding method. そして配線基板の上面に対して封止樹脂で封止した後、最終工程として、ダイシングブレードにより個々の積層型半導体装置に切断分離する工程を有するものである。 Then after sealing with a sealing resin to the upper surface of the wiring board, as a final step, and has a step of cutting into individual stacked semiconductor device by dicing blade. したがって、図1に示したような実施形態の積層型半導体装置の外形形状として、封止樹脂15の側面が配線基板10 Thus, as the outer shape of the stacked type semiconductor device embodiments as shown in FIG. 1, the side surface wiring board 10 of the sealing resin 15
の側面と同一面に位置しているものであり、これは一括切断によって分割された形状である。 It is those located in the side in the same plane, which is a shape divided by bulk cutting.

【0049】また本実施形態の積層型半導体装置の製造方法で用いたフィルム配線導体については、図4の平面図に示すように、搭載する半導体素子の表面の電極パッドの配置および配線基板の配線電極の配置に対して、各々大きさ、ピッチなどの条件を合わせた配線導体13a [0049] Regarding film wiring conductors used in the method for manufacturing a stacked semiconductor device of the present embodiment, as shown in the plan view of FIG. 4, the arrangement of the electrode pads of the surface of the semiconductor element to be mounted and the wiring board interconnection with respect to the arrangement of the electrodes, each size, wiring conductors 13a to match conditions such as pitch
を軟性樹脂によるフィルム材13bで挟んだ3層構造であり、図に示した構造は半導体素子の電極パッドが素子周辺部に配置されたペリフェラルパッド配置に対応させた構造を示している。 The a three-layer structure is sandwiched between the film material 13b by soft resin, the structure shown in the figure shows the structure in which the electrode pads of the semiconductor element is made to correspond to the peripheral pad arrangement which is arranged on the element periphery. 勿論、配線導体13aの長さやフィルム材13b自体の面積についても配線基板や下側の半導体素子の面積、段差に応じて設定するものである。 Of course, the area of ​​the length or film material 13b semiconductor devices even wiring board and the lower the area itself of the wiring conductor 13a, is to set according to the step.

【0050】次に図5の断面図には、本実施形態で説明した積層型半導体装置において、3つの半導体素子を1 [0050] The next cross-sectional view of FIG. 5, in the stacked type semiconductor device described in this embodiment, three semiconductor elements 1
パッケージCSPとした形態を示す。 It shows the morphology and package CSP.

【0051】図5に示すように、配線基板10と対向してフリップチップ接続された第1の半導体素子12以外の第2の半導体素子14、第3の半導体素子16は突起電極14b、突起電極16bで各々フィルム配線導体1 [0051] As shown in FIG. 5, the wiring board 10 opposite to the second semiconductor device 14 other than the first semiconductor element 12 is flip-chip connected to the third semiconductor element 16 protruding electrodes 14b, protrusion electrodes each at 16b film wiring conductor 1
3を介してフリップチップ接続され、そのフィルム配線導体13の配線導体13aは配線基板10の配線電極1 3 is flip-chip connected through the wiring electrodes 1 of the wiring conductor 13a is a wiring board 10 of the film wiring conductor 13
0bと接続して1パッケージでチップ積層構造を有するものである。 Connected with 0b and has a chip stack structure in one package. このように3つの半導体素子を積層搭載する場合であっても、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体13を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板10の配線電極との接続部分が破断することを防止し、接続の信頼性を高めることができる構造を実現できる。 Even in the case of such laminated mounting three semiconductor element, the second or more stacked semiconductor devices, because they are stacked and mounted through the film wiring conductor 13 made of a soft resin, laminated by thermal expansion of the type semiconductor device, when the semiconductor device is inflated, even if the fine movement within the package, to move in conjunction also connected portion with its expansion movement, between the semiconductor element and the wiring electrodes of the wiring board 10 It prevents the connection portions are broken, the structure can be realized which can increase the reliability of the connection. またフィルム配線導体13に対して、半導体素子を突起電極を加圧して接続するにおいても、フィルム配線導体13のフィルム材が外圧を吸収するため、下側の半導体素子への影響を解消し、安定に信頼性よくフリップチップ接続できるものである。 Further to the film wiring conductor 13, in connecting the semiconductor element projecting electrodes pressurize, because the film material of the film wiring conductor 13 absorbs the external pressure, to eliminate the influence of the lower semiconductor element, stable in which high reliability can flip chip connected to.

【0052】次に別の実施形態の積層型半導体装置およびその製造方法について説明する。 [0052] Next, another embodiment stacked semiconductor device and a manufacturing method thereof will be described.

【0053】図6は別の実施形態の積層型半導体装置を示す主要な断面図である。 [0053] FIG. 6 is a principal sectional view of a stacked type semiconductor device of another embodiment.

【0054】図6に示すように、本実施形態の積層型半導体装置は、配線基板10上面の封止樹脂15の内部の構造は図1に示した構造と同様であるが、封止樹脂15 [0054] As shown in FIG. 6, the stacked semiconductor device of the present embodiment, although the internal structure of the wiring substrate 10 upper surface of the sealing resin 15 is similar to the structure shown in FIG. 1, the sealing resin 15
の上面周辺部は研削による切削部17を有して体積が減じられている構造である。 Upper surface peripheral portion of a structure volume has a cutting portion 17 by grinding is reduced. 本実施形態では図1で示した積層型半導体装置の封止樹脂の体積に対して20[%] 20 [%] with respect to the volume of the sealing resin of the stacked semiconductor device shown in FIG. 1 in this embodiment
の体積を研削によって減じている。 It is reduced by grinding the volume.

【0055】この構造により、複数の半導体素子を1パッケージに構成した積層型半導体装置の軽量化を実現できるものである。 [0055] With this structure, those that can achieve weight reduction of the stacked semiconductor device constructed a plurality of semiconductor elements in one package.

【0056】次に本実施形態の積層型半導体装置の製造方法について、図面を参照しながら説明する。 [0056] Next, a manufacturing method of a stacked semiconductor device of the present embodiment will be described with reference to the drawings.

【0057】図7,図8は本実施形態の積層型半導体装置の製造方法を示す主要な工程ごとの断面図である。 [0057] Figure 7, Figure 8 is a cross-sectional view of each primary steps showing a manufacturing method of a stacked semiconductor device of the present embodiment.

【0058】まず図7(a)に示すように、前述の積層型半導体装置の製造方法で説明した通り、配線基板10 [0058] First, as shown in FIG. 7 (a), as described in the aforementioned method of the stacked semiconductor device, the wiring board 10
に対して複数の半導体素子を搭載、電気的に接続し、配線基板10の上面を封止樹脂15で封止する。 Mounting a plurality of semiconductor elements relative to, electrically connected, the upper surface of the wiring substrate 10 is sealed with a sealing resin 15. ここでは個々の半導体素子単位ごとに分割され得る構造の1枚の大型の配線基板10を使用している。 It is using the wiring substrate 10 of one large structure may be divided into individual semiconductor elements units.

【0059】次に図7(b)に示すように、封止樹脂1 [0059] Next, as shown in FIG. 7 (b), the sealing resin 1
5が形成された配線基板10の上方の各分割領域に対して、研削機能部18と切断機能部19とを有した回転ブレード20を配置させる。 5 with respect to each divided region of the upper wiring board 10 is formed, to place the rotary blade 20 having a grinding function unit 18 and the cutting function unit 19.

【0060】次に図8(a)に示すように、回転ブレード20を封止樹脂15に当接させ、回転ブレード20の研削機能部18で封止樹脂15を研削除去するとともに、封止樹脂15、配線基板10の分割領域を切断機能部19で切断することにより、個々の積層型半導体装置21を得る。 [0060] Next, as shown in FIG. 8 (a), the rotary blade 20 is brought into contact with the sealing resin 15, the sealing resin 15 along with ground removed by the grinding function portion 18 of the rotary blade 20, the sealing resin 15, by cutting the divided area of ​​the wiring substrate 10 in the cutting function unit 19 to obtain the individual stacked semiconductor device 21.

【0061】これにより、図8(b)に示すように、封止樹脂15の上面周辺部は研削による切削部17を有して体積が減じられている構造の積層型半導体装置21を実現できるものである。 [0061] Thus, as shown in FIG. 8 (b), the upper surface peripheral portion of the sealing resin 15 can be realized a stacked semiconductor device 21 having the structure volume has a cutting portion 17 by grinding is reduced it is intended.

【0062】なお、使用する回転ブレード20の研削機能部18の幅や、切断機能部19の幅、長さ、および研削機能部18と切断機能部19との長さについては、切断分離する封止樹脂の厚み、配線基板の厚みにより適宜、設定するものである。 [0062] The width and the grinding function portion 18 of the rotary blade 20 to be used, the width of the cutting function section 19, the length, and the length of the grinding function unit 18 and the cutting function unit 19, sealing the cut and separated the thickness of the sealing resin, suitably by the thickness of the wiring board, and sets. また研削機能部18の粗さについても同様である。 The same is true for the roughness of the grinding function unit 18.

【0063】以上、本実施形態では、配線電極を有した配線基板と、その配線基板上にその表面側が配線基板と対向してフリップチップ接続された第1の半導体素子と、その第1の半導体素子の裏面上にフィルム配線導体を介してその表面側が第1の半導体素子の裏面と対向してフリップチップ接続された第2の半導体素子との少なくとも2つの半導体素子を有した積層型半導体装置であって、第1の半導体素子はその表面に設けた突起電極が配線基板の配線電極と接続し、配線基板と対向してフリップチップ接続された第1の半導体素子以外の半導体素子はその表面に設けた突起電極でフィルム配線導体を介してフリップチップ接続され、そのフィルム配線導体の配線導体は配線基板の配線電極と接続して1パッケージでチップ積層構造を [0063] above, in this embodiment, a wiring board having a wiring electrode, a first semiconductor element is flip-chip connected the surface side to the wiring substrate is opposed to the wiring substrate, the first semiconductor in stacked semiconductor device having at least two semiconductor elements of the second semiconductor element in which the surface side is flip-chip connected to face the back surface of the first semiconductor element through a film wiring conductor on the back surface of the element there, the first semiconductor device is connected protruding electrodes provided on the surface of the wiring electrodes of the wiring board, a semiconductor element other than the first semiconductor element is flip-chip connected to the wiring board and the opposite on the surface is flip-chip connected through a film wiring conductor protruding electrodes provided, the chip stack structure wiring conductors of the film wiring conductor 1 package connected to the wiring electrodes of the wiring substrate するものであるため、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体を介して積層搭載され、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板の配線電極との接続部分が破断することを防止し、接続の信頼性を高めることができる。 For those wherein the, the second or more stacked semiconductor devices, are stacked and mounted through the configured film wiring conductors soft resin, by the thermal expansion of the stacked semiconductor device, when the semiconductor device is inflated, be finely within the package, to move in conjunction also connected portion with its expansion movement, to prevent the connection portion between the wiring electrode of the semiconductor element wiring substrate is broken, increase the reliability of the connection be able to. またフィルム配線導体は配線導体がその表裏面側が軟性樹脂で挟まれた3層構造であるため、内層の配線導体自体の固定は避けられ、熱膨張の微動に対応できるものである。 Since film wiring conductor its front and back surface side of the wiring conductor is a three-layer structure sandwiched between the soft resins, fixed inner wiring conductor itself are avoided, it is those that can correspond to tremor thermal expansion. また半導体素子と半導体素子との間には軟性樹脂で構成されたフィルム配線導体が介在しているので、積層型半導体装置全体としてフレキシブル性を有し、熱膨張による応力に対応できる構造である。 Since film wiring conductor made of a soft resin between the semiconductor element and the semiconductor element are interposed, has flexibility as a whole stacked semiconductor device, a structure to accommodate the stress due to thermal expansion.

【0064】 [0064]

【発明の効果】本発明の積層型半導体装置は、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動し、半導体素子と配線基板の配線電極との接続部分が破断することを防止し、 The stacked semiconductor device of the present invention exhibits, the second or more stacked semiconductor devices, because they are stacked and mounted through the configured film wiring conductors soft resin, of the stacked type semiconductor device thermal expansion, when inflated semiconductor elements, even if the fine movement inside the package, that the expansion move in with moving connecting portion is also linked to the connection portion between the wiring electrode of the semiconductor element and the wiring board is broken to prevent,
接続の信頼性を高めることができる積層型半導体装置である。 A stacked type semiconductor device capable of increasing the reliability of the connection. また半導体素子と半導体素子との間には軟性樹脂で構成されたフィルム配線導体が介在しているので、積層型半導体装置全体としてフレキシブル性を有し、熱膨張による応力に対応できる構造を有した高信頼性の積層型半導体装置を実現できるものである。 Since film wiring conductor made of a soft resin between the semiconductor element and the semiconductor element are interposed, it has flexibility as a whole stacked semiconductor device, having a structure capable of corresponding to the stress due to thermal expansion in which it can realize a highly reliable stacked semiconductor device.

【0065】また本発明の積層型半導体装置の製造方法は、2つ目以上の積層された半導体素子は、軟性樹脂で構成されたフィルム配線導体を介して積層搭載されているため、積層型半導体装置の熱膨張によって、半導体素子が膨張した場合、パッケージ内部で微動しても、その膨張移動にともなって接続部分も連動して移動するため、半導体素子と配線基板の配線電極との接続部分が破断することを防止し、接続の信頼性を高めることができる構造を実現できる。 [0065] The method for manufacturing a stacked semiconductor device of the present invention, the second or more stacked semiconductor devices, because they are stacked and mounted through the configured film wiring conductors in flexible resin, the stacked semiconductor by the thermal expansion of the device, when the semiconductor device is inflated, even if the fine movement within the package, to move in conjunction also connected portion with its expansion movement, the connection portion between the wiring electrodes of the semiconductor element and the wiring substrate prevented from breaking, the structure can be realized which can increase the reliability of the connection. またフィルム配線導体に対して、 Also the film wiring conductor,
半導体素子を突起電極を加圧して接続するにおいても、 Also in the semiconductor device for connecting the protruding electrode pressurizing,
フィルム配線導体のフィルム材が外圧を吸収するため、 Since the film material of the film wiring conductor absorbs external pressure,
下側の半導体素子への影響を解消し、安定に信頼性よくフリップチップ接続できるものである。 To eliminate the influence of the lower semiconductor element, those capable of stably reliably flip chip bonding.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施形態の積層型半導体装置を示す断面図 Sectional view of a stacked type semiconductor device of an embodiment of the invention; FIG

【図2】本発明の一実施形態の積層型半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a stacked semiconductor device according to an embodiment of the present invention; FIG

【図3】本発明の一実施形態の積層型半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a stacked semiconductor device according to an embodiment of the present invention; FIG

【図4】本発明の一実施形態の積層型半導体装置の製造方法で用いるフィルム配線導体を示す平面図 Plan view of a film wiring conductor used in the production method of the stacked semiconductor device according to an embodiment of the invention; FIG

【図5】本発明の一実施形態の積層型半導体装置を示す断面図 Sectional view of a stacked type semiconductor device of an embodiment of the present invention; FIG

【図6】本発明の一実施形態の積層型半導体装置を示す断面図 Sectional view of a stacked type semiconductor device of an embodiment of the invention; FIG

【図7】本発明の一実施形態の積層型半導体装置の製造方法を示す断面図 7 is a cross-sectional view showing a method of manufacturing a stacked semiconductor device according to an embodiment of the present invention

【図8】本発明の一実施形態の積層型半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a stacked semiconductor device according to an embodiment of the invention; FIG

【図9】従来の積層型半導体装置を示す断面図 Figure 9 is a sectional view showing a conventional stacked semiconductor device

【図10】従来の積層型半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of FIG. 10 conventional stacked semiconductor device

【図11】従来の積層型半導体装置の製造方法を示す断面図 Figure 11 is a sectional view showing a conventional method of manufacturing a stacked semiconductor device

【符号の説明】 DESCRIPTION OF SYMBOLS

1a,1b 配線電極 2 端子電極 3 配線基板 4 樹脂 5 第1の半導体素子 5a 電極パッド 5b 突起電極 6 接着剤 7 第2の半導体素子 7a 電極パッド 8 金属細線 9 封止樹脂 10 配線基板 10a,10b 配線電極 11 樹脂 12 第1の半導体素子 12a 電極パッド 12b 突起電極 13 フイルム配線導体 13a 配線導体 13b フィルム材 14 第2の半導体素子 14a 電極パッド 14b 突起電極 15 封止樹脂 16 第3の半導体素子 16b 突起電極 17 切削部 18 研削機能部 19 切断機能部 20 回転ブレード 21 積層型半導体装置 1a, 1b wiring electrodes 2 terminal electrode 3 wiring board 4 Resin 5 first semiconductor element 5a electrode pad 5b protruding electrodes 6 adhesive 7 second semiconductor element 7a electrode pads 8 thin metal wire 9 a sealing resin 10 wiring board 10a, 10b wiring electrodes 11 resin 12 first semiconductor element 12a electrode pad 12b protruding electrode 13 film conductor 13a wiring conductor 13b film material 14 and the second semiconductor element 14a electrode pad 14b protruding electrodes 15 sealing resin 16 third semiconductor element 16b projecting electrode 17 cutting portion 18 grinding function unit 19 disconnect unit 20 rotating blade 21 stacked semiconductor device

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H01L 21/60 H01L 25/08 Z 23/12 501 23/28 Fターム(参考) 4M109 AA01 BA03 CA04 CA21 DA03 DA07 EA02 5F044 KK07 KK08 KK16 LL09 MM06 NN07 NN13 QQ01 RR16 RR18 5F061 AA01 BA03 CA04 CA21 GA05 ────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. 7 identification mark FI theme Court Bu (reference) H01L 21/60 H01L 25/08 Z 23/12 501 23/28 F -term (reference) 4M109 AA01 BA03 CA04 CA21 DA03 DA07 EA02 5F044 KK07 KK08 KK16 LL09 MM06 NN07 NN13 QQ01 RR16 RR18 5F061 AA01 BA03 CA04 CA21 GA05

Claims (8)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 配線電極を有した配線基板と、 前記配線基板上に樹脂を介してその表面側が前記配線基板と対向してフリップチップ接続された第1の半導体素子と、 前記第1の半導体素子の裏面上にフィルム配線導体を介してその表面側が前記第1の半導体素子の裏面と対向してフリップチップ接続された第2の半導体素子との少なくとも2つの半導体素子を有し、 前記第1の半導体素子はその表面に設けた突起電極が前記配線基板の配線電極と接続し、 前記第2の半導体素子はその表面に設けた突起電極が前記フィルム配線導体の配線導体と接続し、前記配線導体は前記配線基板の配線電極と接続し、 前記配線基板の上面領域は封止樹脂で封止されている積層型半導体装置であって、 研削によって前記封止樹脂の上面周辺部の体積が減じ And 1. A wiring board having a wiring electrode, a first semiconductor element is flip-chip connected the surface side opposite to the wiring board via the resin on the wiring substrate, the first semiconductor through the film wiring conductor on the back surface of the element has at least two semiconductor elements and the second semiconductor element is flip-chip connected the surface side and back surface facing the first semiconductor element, the first the semiconductor element is connected to the wiring electrodes of the wiring substrate protruding electrodes provided on the surface thereof, the second semiconductor element has protruding electrodes provided on the surface thereof connected to the wiring conductor of the film wiring conductor, the wiring conductors connected to the wiring electrodes of the wiring substrate, the top surface region of the wiring board is a multilayer semiconductor device encapsulated with a sealing resin, the volume of the upper surface peripheral portion of the sealing resin is reduced by the grinding られていることを特徴とする積層型半導体装置。 Stacked semiconductor device characterized by being.
  2. 【請求項2】 フィルム配線導体は配線導体を軟性樹脂で挟んだ構造であることを特徴とする請求項1に記載の積層型半導体装置。 2. A film wiring conductors stacked semiconductor device according to claim 1, wherein the wiring conductor is a structure sandwiched by soft resin.
  3. 【請求項3】 配線基板は、上面に配線電極と、下面に前記上面の配線電極と接続した端子電極とを有した配線基板であることを特徴とする請求項1に記載の積層型半導体装置。 3. A wiring board, a stacked semiconductor device according to claim 1, wherein the wiring electrode on the upper surface, to be a wiring board having a terminal electrode connected to the wiring electrode of the upper surface to the lower surface .
  4. 【請求項4】 第1の半導体素子または第2の半導体素子の面積と配線基板の面積とは、前記配線基板の面積が大きい条件で略同等の大きさで構成されてチップサイズパッケージを構成していることを特徴とする請求項1に記載の積層型半導体装置。 4. The area and the area of ​​the wiring substrate of the first semiconductor element and the second semiconductor element, constitute a chip size package in a large area condition of the wiring board is composed of substantially the same size it is stacked semiconductor device according to claim 1, wherein the.
  5. 【請求項5】 上面に配線電極と、下面に前記上面の配線電極と接続した端子電極とを有した配線基板に対して、樹脂を介してその表面の電極パッドに突起電極が形成された第1の半導体素子をフリップチップ接続し、前記突起電極と前記配線基板の配線電極とを接続する第1 5. A wiring on the upper surface electrode, the wiring board having a terminal electrode connected to the wiring electrode of the upper surface to the lower surface, the protrusion electrode to electrode pads of the surface was formed through the resin the first semiconductor element by flip chip connection, first connecting the wiring electrodes of the wiring board and the projecting electrodes
    の工程と、 前記第1の半導体素子の裏面および前記配線基板上面に一体でフィルム配線導体を接着するとともに、前記フィルム配線導体の配線導体の外方端部を前記配線基板の配線電極と接続する第2の工程と、 前記第1の半導体素子の裏面に対して、前記フィルム配線導体を介してその表面の電極パッドに突起電極が形成された第2の半導体素子をフリップチップ接続し、前記突起電極と前記フィルム配線導体の配線導体の内方端部とを接続する第3の工程と、 前記配線基板の上面領域を封止樹脂で封止する第4の工程と、 前記配線基板の上面に形成した封止樹脂の上面周辺部に対して研削処理を行い、前記封止樹脂の上面周辺部の体積を減じる第5の工程とよりなることを特徴とする積層型半導体装置の製造方法。 And step, the bonding film wiring conductor integrally with the back surface and the wiring substrate upper surface of the first semiconductor device, the outer end of the wiring conductor of the film wiring conductor connected to the wiring electrodes of the wiring substrate a second step, the rear surface of the first semiconductor element, the second semiconductor element is flip-chip connection protruding electrodes to the electrode pads of the surface was formed through the film conductor, said protrusions a third step of connecting the inner end of the wiring conductor of the the electrode film wiring conductor, the upper surface region of the wiring board and the fourth step of sealing with the sealing resin, the upper surface of the wiring substrate It performs grinding processing with respect to the upper surface peripheral portion of the formed sealing resin, the manufacturing method of the stacked semiconductor device characterized by comprising further a fifth step of reducing the volume of the upper surface peripheral portion of the sealing resin.
  6. 【請求項6】 その上面に複数の半導体素子が個々に搭載されるもので、また上面に個々の半導体素子に対応した配線電極が設けられ、下面には上面の配線電極と基板内部で接続した端子電極が設けられ、個々の半導体素子単位ごとに分割され得る構造の1枚の大型の配線基板に対して、樹脂を介してその表面の電極パッドに突起電極が形成された第1の半導体素子をフリップチップ接続し、前記突起電極と前記配線基板の配線電極とを接続する第1の工程と、 前記第1の半導体素子の裏面および前記配線基板上面に一体でフィルム配線導体を接着するとともに、前記フィルム配線導体の配線導体の外方端部を前記配線基板の配線電極と接続する第2の工程と、 前記第1の半導体素子の裏面に対して、前記フィルム配線導体を介してその表面 6. those plurality of semiconductor elements on its upper surface are mounted individually, also wiring electrodes corresponding to individual semiconductor devices formed on the upper surface, the lower surface connected by a wiring electrode and the substrate inside the upper surface a terminal electrode provided, each relative to one large wiring board structure can be divided into semiconductor elements unit, a first semiconductor element projecting electrodes on the electrode pads of the surface is formed through the resin the flip-chip connected, a first step of connecting the wiring electrodes of the wiring board and the protruding electrodes, as well as adhere the film wiring conductor integrally with the back surface and the wiring substrate upper surface of the first semiconductor element, a second step of connecting the outer end of the wiring conductor of the film conductor and the wiring electrodes of the wiring board, the rear surface of the first semiconductor device, the surface via the film wiring conductor 電極パッドに突起電極が形成された第2の半導体素子をフリップチップ接続し、前記突起電極と前記フィルム配線導体の配線導体の内方端部とを接続する第3の工程と、 前記配線基板の上面領域を封止樹脂で封止する第4の工程と、 前記配線基板に対して、個々の積層型半導体装置に切断分離するとともに、前記配線基板の上面に形成した封止樹脂の上面周辺部に対して研削処理を行い、前記封止樹脂の上面周辺部の体積を減じる第5の工程とよりなることを特徴とする積層型半導体装置の製造方法。 A second semiconductor element projecting electrodes on the electrode pads are formed by flip chip bonding, a third step of connecting the inner end of the said protruding electrode film wiring conductors of the wiring conductor, the wiring substrate a fourth step of sealing the upper surface region with a sealing resin, with respect to the wiring board, as well as cut and separated into individual stacked semiconductor device, the upper surface peripheral portion of the sealing resin formed on the upper surface of the wiring substrate It performs grinding processing on the method for manufacturing a stacked semiconductor device characterized by comprising further a fifth step of reducing the volume of the upper surface peripheral portion of the sealing resin.
  7. 【請求項7】 第1の半導体素子の裏面に対して、フィルム配線導体を介してその表面の電極パッドに突起電極が形成された第2の半導体素子をフリップチップ接続し、前記突起電極と前記フィルム配線導体の配線導体の内方端部とを接続する第3の工程では、第2の半導体素子を前記フィルム配線導体に対して加圧し、前記突起電極で前記フィルム配線導体のフィルム材を突き破って前記配線導体の内方端部とを接続することを特徴とする請求項5または請求項6に記載の積層型半導体装置の製造方法。 Relative 7. back surface of the first semiconductor device, the second semiconductor element projecting electrodes on the electrode pads of the surface is formed through a film wiring conductor flip chip connection, the said protruding electrode in the third step of connecting the inner end of the wiring conductor of the film conductor, pressurized second semiconductor element to the film conductor, break through the film material of the film wiring conductor in the protruding electrode method for manufacturing a stacked semiconductor device according to claim 5 or claim 6, characterized in that connecting the inner end of the wiring conductor Te.
  8. 【請求項8】 第1の半導体素子の裏面および配線基板上面に一体でフィルム配線導体を接着するとともに、前記フィルム配線導体の配線導体の外方端部を前記配線基板の配線電極と接続する第2の工程では、配線導体を軟性樹脂で挟んだ構造のフィルム配線導体を用いることを特徴とする請求項5または請求項6に記載の積層型半導体装置の製造方法。 8. with adhering the film wiring conductor integrally with the back surface and the wiring substrate upper surface of the first semiconductor element, first the outer end of the wiring conductor of the film wiring conductor connected to the wiring electrodes of the wiring substrate the second step, the manufacturing method of the stacked semiconductor device according to claim 5 or claim 6 wiring conductor which comprises using a film wiring conductor sandwiched by soft resin.
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