JP7269756B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device mounted with a semiconductor element and a manufacturing method thereof.

In recent years, there have been leadless package type semiconductor devices such as SON packages (Small Outline Non-leaded packages) and QFN packages (Quad Flat Non-leaded packages). A leadless package type semiconductor device is advantageous in reducing the size and thickness of the semiconductor device because terminals for external connection do not protrude from the sealing resin that encapsulates the semiconductor element. For example, Patent Document 1 discloses such a leadless package type semiconductor device.

The semiconductor device described in Patent Document 1 includes a semiconductor element, a lead frame, thin metal wires (wires), and a sealing resin. The lead frame is made of copper, for example. The lead frame has a die pad section and a plurality of lead sections spaced apart from each other. The die pad portion supports the semiconductor element. Each of the plurality of lead portions is electrically connected to the semiconductor element through a thin metal wire, and is a terminal for external connection when the semiconductor device is mounted on a circuit board of electronic equipment or the like. The sealing resin covers the semiconductor element and the fine metal wires.

Japanese Patent Application Laid-Open No. 2001-257304

In the semiconductor device disclosed in Patent Document 1, the sealing resin covers the semiconductor element and the fine metal wires. Since the thin metal wires are formed on the semiconductor element, they hinder the thinning of the encapsulating resin. Further, the lead frame can be formed by processing a metal plate (copper plate), for example. Therefore, the conventional semiconductor device has room for improvement in terms of thickness reduction.

The present disclosure has been created in view of the above problems, and an object thereof is to provide a thin semiconductor device and a method for manufacturing the semiconductor device.

A semiconductor device provided by a first aspect of the present disclosure has a semiconductor element, and a first main surface and a first back surface facing opposite sides in a thickness direction, and the semiconductor element is provided on the first main surface. A mounted first substrate, a first conductive portion formed on a portion of the first main surface, and a first conductive portion connected to the first conductive portion and viewed in a first direction orthogonal to the thickness direction a first electrode including a second conductive portion overlapping the first substrate; a sealing resin covering the semiconductor element; and a second electrode exposed from the sealing resin and conducting to the first electrode. and the second electrode is in contact with the second conductive portion.

A method for manufacturing a semiconductor device provided by the second aspect of the present disclosure includes a substrate preparation step of preparing a substrate having a main surface and a back surface facing opposite sides in a thickness direction; a recess forming step of forming a recess recessed from the surface toward the back surface; a step of forming one electrode; a step of mounting a semiconductor device electrically connected to the first electrode; a step of forming a sealing resin for forming a sealing resin covering the semiconductor device; Grinding in the thickness direction toward the main surface side to expose the second conductive portion; and a second electrode forming step of forming a second electrode in contact with the exposed second conductive portion. characterized by

According to the semiconductor device of the present disclosure, it is possible to reduce the thickness of the semiconductor device. In addition, the manufacturing method of the semiconductor device of the present disclosure can manufacture a thin semiconductor device.

1 is a perspective view showing a semiconductor device according to a first embodiment; FIG. FIG. 2 is a perspective view of FIG. 1 with a sealing resin and an insulating layer omitted; 1 is a plan view showing a semiconductor device according to a first embodiment; FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment; FIG. 1 is a side view showing a semiconductor device according to a first embodiment; FIG. 4 is a cross-sectional view taken along line VI-VI of FIG. 3; FIG. FIG. 4 is a cross-sectional view along line VII-VII of FIG. 3; 3 is a cross-sectional view for explaining a manufacturing process (recess forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a plan view for explaining a manufacturing process (recess forming process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (insulating layer forming process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (an internal resin layer forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a plan view for explaining a manufacturing process (an internal resin layer forming process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (base layer forming process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (plating layer forming process) of the semiconductor device shown in FIG. 1; FIG. 2 is a plan view for explaining a manufacturing process (plating layer forming process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (bonding layer forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a cross-sectional view for explaining a manufacturing process (base layer removing process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (semiconductor element mounting process) of the semiconductor device shown in FIG. 1; FIG. 2 is a plan view for explaining a manufacturing process (semiconductor element mounting process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (sealing resin forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a cross-sectional view for explaining a manufacturing process (grinding process) of the semiconductor device shown in FIG. 1; FIG. 3 is a bottom view for explaining a manufacturing process (grinding process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (an external resin layer forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a bottom view for explaining a manufacturing process (an external resin layer forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a cross-sectional view for explaining a manufacturing process (side exposure process) of the semiconductor device shown in FIG. 1; FIG. 3 is a bottom view for explaining a manufacturing process (side exposure process) of the semiconductor device shown in FIG. 1; FIG. 2 is a cross-sectional view for explaining a manufacturing process (second electrode forming process) of the semiconductor device shown in FIG. 1; FIG. 3 is a bottom view for explaining a manufacturing process (second electrode forming process) of the semiconductor device shown in FIG. 1; FIG. It is a bottom view which shows the semiconductor device which concerns on 2nd Embodiment. It is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 30 is a cross-sectional view for explaining a manufacturing process (recess forming process) of the semiconductor device shown in FIG. 29; FIG. 30 is a plan view for explaining a manufacturing process (recess forming process) of the semiconductor device shown in FIG. 29; 30 is a cross-sectional view for explaining a manufacturing process (plating layer forming process) of the semiconductor device shown in FIG. 29; FIG. 30 is a cross-sectional view for explaining a manufacturing process (a base layer removing process) of the semiconductor device shown in FIG. 29; FIG. 30 is a cross-sectional view for explaining a manufacturing process (second electrode forming process) of the semiconductor device shown in FIG. 29; FIG. It is a sectional view showing a semiconductor device concerning a 3rd embodiment. 37 is a cross-sectional view for explaining the manufacturing process (recess forming process) of the semiconductor device shown in FIG. 36; FIG. FIG. 37 is a plan view for explaining the manufacturing process (recess forming process) of the semiconductor device shown in FIG. 36; It is a sectional view showing a semiconductor device concerning a 4th embodiment. FIG. 40 is a partially enlarged view enlarging a part of FIG. 39; FIG. 40 is a cross-sectional view for explaining a manufacturing process (recess forming process) of the semiconductor device shown in FIG. 39; It is a top view which shows the semiconductor device which concerns on 5th Embodiment. It is a bottom view which shows the semiconductor device which concerns on 5th Embodiment. It is a side view which shows the semiconductor device which concerns on 5th Embodiment. FIG. 43 is a cross-sectional view along the XLV-XLV line in FIG. 42; 46 is a partially enlarged sectional view enlarging a part of FIG. 45; FIG. FIG. 43 is a cross-sectional view along line XLVII-XLVII in FIG. 42; FIG. 48 is a partially enlarged sectional view enlarging a part of FIG. 47; 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a plan view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a plan view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a plan view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a bottom view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a bottom view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a bottom view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. 43 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 42; FIG. It is a sectional view showing a semiconductor device concerning a modification of a 5th embodiment. It is a sectional view showing a semiconductor device concerning a 6th embodiment. It is a sectional view showing a semiconductor device concerning a 7th embodiment.

Preferred embodiments of the semiconductor device of the present disclosure and the method of manufacturing the semiconductor device of the present disclosure will be specifically described below with reference to the drawings.

[First embodiment]
1 to 7 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A10 of this embodiment includes a substrate 11, a substrate 12, an insulating layer 15, a first electrode 20, a second electrode 30, a semiconductor element 41, a bonding layer 42, an internal resin layer 51, an external resin layer 52, and a sealing layer. A stopper resin 60 is provided.

FIG. 1 is a perspective view showing the semiconductor device A10. FIG. 2 is a perspective view of FIG. 1 with the insulating layer 15 and the sealing resin 60 omitted. FIG. 3 is a plan view showing the semiconductor device A10. In the figure, for convenience of understanding, the insulating layer 15 is omitted, and the semiconductor element 41 and the sealing resin 60 are shown by imaginary lines. FIG. 4 is a bottom view showing the semiconductor device A10. FIG. 5 is a side view showing the semiconductor device A10. 6 is a cross-sectional view taken along line VI-VI of FIG. 3. FIG. FIG. 7 is a cross-sectional view along line VII-VII of FIG. For convenience of explanation, in these figures, the horizontal direction of the plan view (see FIG. 3) is the first direction x, and the vertical direction of the plan view perpendicular to the first direction x is the second direction y and the first direction x. and the second direction y is defined as a thickness direction z. One side of the thickness direction z (upper side view and cross-sectional view) is referred to as the upper side, and the other side of the thickness direction z (lower side view and cross-sectional view) is referred to as the lower side, but the posture of the semiconductor device A10 is not limited.

The semiconductor device A10 is a resin package that is surface-mounted on wiring boards of various electronic devices. As shown in FIGS. 3 and 4, the semiconductor device A10 has a rectangular shape when viewed in the thickness direction z (plan view). The semiconductor device A10 is of the QFN package type.

The substrate 11 is composed of a single crystal intrinsic semiconductor material. The intrinsic semiconductor material according to this embodiment is Si (which is silicon). As shown in FIGS. 6 and 7, the substrate 11 has a rectangular shape when viewed in the thickness direction z (planar view). The thickness direction z dimension (thickness) of the substrate 11 is, for example, about 50 to 150 μm. The substrate 11 has a first major surface 111 , a first back surface 112 and a plurality of first side surfaces 113 .

As shown in FIGS. 6 and 7, the first main surface 111 and the first back surface 112 are separated from each other in the thickness direction z and face opposite sides. The first main surface 111 is the upper surface of the substrate 11 shown in FIGS. 6 and 7. FIG. The first rear surface 112 faces the thickness direction z and is the lower surface of the substrate 11 shown in FIGS. The first rear surface 112 faces the circuit board when the semiconductor device A10 is mounted on the circuit board. Each of the plurality of first side surfaces 113 is sandwiched between the first main surface 111 and the first rear surface 112 as shown in FIGS. 6 and 7 . Each first side surface 113 is flat and orthogonal to the first main surface 111 and the first back surface 112, respectively. The substrate 11, as shown in FIGS. 3 and 4, has four first side surfaces 113 facing in the first direction x and the second direction y, respectively.

Each of the multiple substrates 12 is made of the same material as the substrate 11 . That is, each substrate 12 is made of an intrinsic semiconductor material of Si. In this embodiment, the plurality of substrates 12 have substantially the same size and shape. Each substrate 12 has a rectangular shape in plan view, as shown in FIG. The plurality of substrates 12 are all spaced apart from the substrate 11 and the plurality of substrates 12 are spaced apart from each other, as shown in FIG. Each substrate 12 has the same thickness as the substrate 11 . The shape, size, and number of substrates 12 are not limited. Each substrate 12 has a second major surface 121 , a second back surface 122 and a plurality of second side surfaces 123 .

The second major surface 121 faces the same direction as the first major surface 111, as shown in FIG. The second major surface 121 is flat. The second back surface 122 faces the same direction as the first back surface 112, as shown in FIG. The second back surface 122 is flat. The second main surface 121 and the second back surface 122 face opposite sides in the thickness direction z. Each of the plurality of second side surfaces 123 is sandwiched between the second main surface 121 and the second back surface 122 as shown in FIG. Each second side surface 123 is flat and orthogonal to the second main surface 121 and the second back surface 122, respectively. In this embodiment, as shown in FIG. 4, the substrate 12 has four second side surfaces 123 facing in the first direction x and the second direction y, respectively. Of the four second side surfaces 123 of each substrate 12 , the second side surface 123 facing the substrate 11 is in contact with the internal resin layer 51 . Also, the second side surface 123 facing the substrate 11 and the second side surface 123 facing the opposite side are exposed from the sealing resin 60 . For convenience of understanding, the second side surface 123 exposed from the sealing resin 60 may be referred to as "exposed side surface 123a".

The substrate 11 and the plurality of substrates 12 are arranged apart from each other. The substrate 11 and the plurality of substrates 12 are all at the same position in the thickness direction z. The first main surface 111 and each second main surface 121 are arranged at the same position in the thickness direction z. Also, the first back surface 112 and each second back surface 122 are arranged at the same position in the thickness direction z. As shown in FIGS. 3 and 4, the plurality of substrates 12 includes a plurality of substrates 12a respectively facing two first side surfaces 113 facing the first direction x and two first side surfaces facing the second direction y. There are a plurality of substrates 12b facing 113 . The plurality of substrates 12a overlap the substrate 11 when viewed in the second direction y, and the plurality of substrates 12b overlap the substrate 11 when viewed in the first direction x. In this embodiment, four substrates 12 are arranged so as to face each of the four first side surfaces 113 of the substrate 11 . These four substrates 12 are arranged at regular intervals along each first side surface 113 . The substrate 11 corresponds to the "first substrate" described in the claims, and the substrate 12 corresponds to the "second substrate" and "third substrate" described in the claims.

The insulating layer 15 is formed on the substrate 11 so as to cover the first main surface 111 and the plurality of first side surfaces 113, as shown in FIGS. Moreover, as shown in FIG. 6, the insulating layer 15 is formed so as to cover the surface of each substrate 12 except for the second rear surface 122 and the exposed side surface 123a. The insulating layer 15 is an electrically insulating film, and electrically insulates the substrates 11 and 12 from the first electrode 20 . The insulating layer 15 is made of SiO ₂ and is formed by thermally oxidizing the substrates 11 and 12 . In this embodiment, the thickness of the insulating layer 15 is, for example, approximately 0.7 to 1.0 μm. The material, thickness, and formation method of the insulating layer 15 are not limited.

The first electrode 20 is a conductor arranged inside the semiconductor device A10. The first electrode 20 is electrically connected to the semiconductor element 41 . The first electrode 20 is composed of a base layer and a plated layer that are laminated to each other. The underlying layer is composed of a Ti layer and a Cu layer laminated to each other, and has a thickness of about 200 to 800 nm. The plating layer is formed outside the base layer so as to be in contact with the base layer. The plating layer is made of Cu, and its thickness is set to be thicker than that of the underlying layer, and is about 3 to 10 μm. Since the base layer and the plated layer are integrated, they are shown as the first electrode 20 in FIGS. 6 and 7 without distinction. Note that the material and thickness of the first electrode 20 are not limited. In this embodiment, the first electrode 20 includes a first conductive portion 21 and a second conductive portion 22, as shown in FIG.

The first conductive portion 21 and the second conductive portion 22 are connected and integrally formed. The first conductive portion 21 is a portion of the first electrode 20 that is arranged on a portion of the first major surface 111 of the substrate 11 . The second conductive portion 22 is a portion of the first electrode 20 that is arranged between the substrate 11 and the substrate 12 . In the present embodiment, the second conductive portion 22 is a rectangular prism in plan view. In addition, the shape of the second conductive portion 22 is not limited, and may be a circular cylinder in plan view. The second conductive portion 22 has a connection surface 221 in contact with the second electrode 30, as shown in FIG. The connection surface 221 is a flat surface facing one side of the thickness direction z (downward in FIG. 6). In this embodiment, the connection surface 221 is flush with the first back surface 112 and the second back surface 122 . The connection surface 221 corresponds to the "back surface of the second conductive part" described in the claims. Some of the first electrodes 20 correspond to the "fourth electrode" described in the claims.

The second electrode 30 is a conductor that is electrically connected to the first electrode 20 and exposed to the outside. The second electrode 30 is a terminal for mounting the semiconductor device A10 on a circuit board. The second electrode 30 contacts the substrate 12 and the first electrode 20, as shown in FIG. The second electrode 30 is formed by electroless plating. In this embodiment, the second electrode 30 is composed of a Ni layer, a Pd layer, and an Au layer that are laminated together. The Ni layer is in contact with the substrate 12 and the first electrode 20, and the Au layer is exposed to the outside. Also, the Pd layer is interposed between the Ni layer and the Au layer. The second electrode 30 entirely overlaps the sealing resin 60 in plan view. In this embodiment, the thickness of the second electrode 30 is about 3 to 15 μm. The number, thickness, material, and forming method of the second electrodes 30 are not limited. A part of the second electrodes 30 corresponds to the "third electrode" described in the claims. The second electrode 30 includes a first electrode covering portion 31, a second rear surface covering portion 32, and an exposed side surface covering portion 33, as shown in FIG.

The first electrode covering portion 31 is a portion of the second electrode 30 that covers the connection surface 221 of the second conductive portion 22 . The second back surface covering portion 32 is a portion of the second electrode 30 that covers the second back surface 122 of the substrate 12 . The exposed side surface covering portion 33 is a portion of the second electrode 30 that covers the exposed side surface 123 a of the substrate 12 . In this embodiment, the exposed side surface covering portion 33 covers the entire exposed side surface 123a. The exposed side covering portion 33 overlaps the sealing resin 60 in plan view. The first electrode covering portion 31, the second rear covering portion 32, and the exposed side covering portion 33 are integrally formed.

The semiconductor element 41 is an element serving as a functional core of the semiconductor device A10. Semiconductor element 41 is, for example, an integrated circuit (IC) such as an LSI (Large Scale Integration). The semiconductor element 41 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode. The semiconductor element 41 has a rectangular shape in plan view. A semiconductor element 41 is mounted on the substrate 11 . The semiconductor element 41 overlaps the substrate 11 in plan view. The semiconductor element 41 has an element main surface 411 and an element back surface 412 .

The element main surface 411 faces the thickness direction z and faces the same direction as the first main surface 111 of the substrate 11 . The element back surface 412 faces the thickness direction z and faces the side opposite to the element main surface 411 . The device rear surface 412 faces the first main surface 111 .

The semiconductor element 41 has a plurality of electrode pads 413 . A plurality of electrode pads 413 are formed on the element back surface 412 . The plurality of electrode pads 413 are made of Al (aluminum), for example. The semiconductor element 41 is mounted by flip chip bonding.

The bonding layer 42 is a conductive member interposed between the first conductive portion 21 of the first electrode 20 and the semiconductor element 41 (electrode pad 413), as shown in FIGS. In this embodiment, the electrode pad 413 and the first conductive portion 21 are connected via the bonding layer 42 . The bonding layer 42 is made of an alloy containing Sn (tin). Examples of such alloys include Sn--Sb alloys, lead-free solders such as Sn--Ag alloys, and Pb (lead)-containing solders. The bonding layer 42 is formed by electrolytic plating, for example. In this embodiment, the semiconductor element 41 is fixed to the first conductive portion 21 (first electrode 20 ) by the bonding layer 42 .

The internal resin layer 51 is arranged inside the semiconductor device A10. Internal resin layer 51 is made of polyimide, for example. The inner resin layer 51 insulates the substrates 11 and 12 from the first electrode 20 . This reduces the risk of the first electrodes 20 short-circuiting through the substrate 11 . In the semiconductor device A10, the insulating layer 15 also provides insulation between the first electrode 20 and the substrates 11 and 12. As shown in FIG. The substrates 11 and 12 are also made of an intrinsic Si semiconductor material having insulating properties. Therefore, even if the internal resin layer 51 is not provided, the risk of short-circuiting between the first electrodes 20 can be suppressed. However, it is desirable to provide the internal resin layer 51 in order to suppress the risk of short circuit more reliably. The internal resin layer 51 includes a first portion 511 and a second portion 512, as shown in FIG.

The first portion 511 is a portion arranged on the first main surface 111 of the substrate 11 . In this embodiment, the first portion 511 covers the entire first main surface 111 . The second portion 512 is a portion interposed between the substrates 11 and 12 . A through hole 512a is formed through the second portion 512 in the thickness direction z. The through hole 512a has a rectangular shape in plan view. Due to the through hole 512a, the second portion 512 has a rectangular annular cross section along the xy plane. The second conductive portion 22 is filled in the through hole 512a.

The external resin layer 52 is exposed to the outside of the semiconductor device A10. External resin layer 52 is made of, for example, polyimide or epoxy. The external resin layer 52 covers at least the entire surface of the first rear surface 112 . The external resin layer 52 is for insulating the plurality of second electrodes 30 from each other. When the semiconductor device A10 is mounted on a circuit board or the like, the external resin layer 52 can suppress short-circuiting between the second electrodes 30 due to soldering. Furthermore, in the present embodiment, the external resin layer 52 separates the second electrodes 30 from each other by covering a portion of each second back surface 122 as shown in FIG. 4 . Therefore, it is possible to further suppress the occurrence of a short circuit between the second electrodes 30 . Note that the external resin layer 52 may not be provided.

The encapsulating resin 60 is a synthetic resin containing, for example, a black epoxy resin as a main component. The sealing resin 60 covers the semiconductor element 41 as shown in FIG. Also, part of the sealing resin 60 is interposed between the adjacent substrates 12a and between the adjacent substrates 12b. The sealing resin 60 has a resin main surface 61 , a resin back surface 62 and a plurality of resin side surfaces 63 .

The resin main surface 61 faces the same direction as the element main surface 411 . The resin back surface 62 faces the same direction as the element back surface 412, as shown in FIG. The resin rear surface 62 is covered with the external resin layer 52 as shown in FIG. Each resin side surface 63 has a flat portion 631 and a recessed portion 632 . The flat portion 631 is a portion of the resin side surface 63 that is flat. The concave portion 632 is a portion of the resin side surface 63 recessed from the flat portion 631 . In this embodiment, the recess 632 is positioned at the edge on the side where the substrate 11 and the substrate 12 are arranged.

Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 8 to 28. FIG. 8 to 28, FIG. 9, FIG. 12, FIG. 15, and FIG. 19 are plan views showing one process related to the method of manufacturing the semiconductor device A10. 28 is a bottom view showing one step of the method of manufacturing the semiconductor device A10. The drawings other than these are cross-sectional views showing one process related to the method of manufacturing the semiconductor device A10. The cross section is the same as the cross section shown in FIG.

First, as shown in FIGS. 8 and 9, a base material 810 having a main surface 810a and a back surface 810b facing in the thickness direction z is prepared, and the base material 810 is coated with a film extending from the main surface 810a in the thickness direction z. A recessed recess 801 is formed. The base material 810 is an assembly of parts corresponding to the substrates 11 and 12 of the semiconductor device A10. In this embodiment, the material of the substrate 810 is an intrinsic semiconductor material of Si. In the step of preparing the substrate 810 (substrate preparation step), for example, a silicon wafer is prepared as the substrate 810 . The step of forming recesses 801 in base material 810 (recess formation step) is performed, for example, by dry etching. By forming the recess 801 in the base material 810 by the recess forming step, the bottom surface 801a and the upright surface 801b appear in the recess 801 . The upright surface 801b has an upper end shown in FIG. 8 connected to the main surface 810a and a lower end shown in FIG. 8 connected to the bottom surface 801a. The standing surface 801b stands up from the bottom surface 801a and is perpendicular to the bottom surface 801a. Further, by forming the concave portion 801, the main surface 810a is divided into a first main surface 811a and a plurality of second main surfaces 812a which are separated from each other. Note that the recess forming step is not limited to dry etching. For example, a (110) plane having a crystal orientation of (110) may be employed as the main surface 810a, and the recesses 801 may be formed by anisotropic etching using KOH (potassium hydroxide). In this case, the upright plane 801b is a (111) plane with a crystal orientation of (111).

Then, as shown in FIG. 10, an insulating layer 815 is formed. The insulating layer 815 corresponds to the insulating layer 15 of the semiconductor device A10. In the step of forming insulating layer 815 (insulating layer forming step), base material 810 is thermally oxidized to form insulating layer 815 over the entire surface of main surface 810a, bottom surface 801a and upright surface 801b. The thickness of insulating layer 815 is, for example, about 0.7 to 1.0 μm.

Next, as shown in FIGS. 11 and 12, a resin layer 851 is formed. The resin layer 851 corresponds to the internal resin layer 51 of the semiconductor device A10. In the step of forming the resin layer 851 (internal resin layer forming step), first, a photosensitive polyimide resin is applied to the main surface 810a of the base material 810 and the entire surface of the recessed portion 801 using, for example, a spin coater (rotary coating device). is applied to the substrate 810 . A film-like photosensitive polyimide resin may be attached. Then, patterning is performed by exposing and developing the photosensitive polyimide resin. Thereby, the resin layer 851 shown in FIGS. 11 and 12 is formed. This resin layer 851 has a first portion 851a and a second portion 851b. The first portion 851 a is a portion formed on a portion of the main surface 810 a of the base material 810 . The second portion 851b is a portion formed so as to be interposed between the first main surface 811a and the second main surfaces 812a in plan view. The second portion 851b has a through hole 851d penetrating in the thickness direction z. The insulating layer 815 is exposed from the through hole 851d.

Next, as shown in FIG. 13, an underlying layer 820a is formed. A portion of the underlying layer 820a will later correspond to a portion of the first electrode 20 of the semiconductor device A10 (the underlying layer of the first electrode 20 described above). The base layer 820a is formed by a sputtering method. The underlying layer 820a according to the present embodiment is composed of a Ti layer and a Cu layer that are laminated to each other. In the step of forming the base layer 820a (base layer forming step), after forming a Ti layer in contact with the insulating layer 815 and the base material 810, a Cu layer is formed in contact with the Ti layer.

Next, as shown in FIGS. 14 and 15, a plating layer 820b is formed. The plating layer 820b corresponds to part of the first electrode 20 of the semiconductor device A10 (the plating layer of the first electrode 20 described above). The plating layer 820b is formed by photolithographic patterning and electroplating. In the step of forming the plating layer 820b (plating layer forming step), first, a resist layer (not shown) for forming the plating layer 820b is formed by photolithography. In forming the resist layer, a photosensitive resist is applied so as to cover the entire surface of the underlying layer 820a, and patterning is performed by exposing and developing the photosensitive resist. This patterning exposes a portion of the underlying layer 820a (the portion forming the plating layer 820b). Then, a plated layer 820b is formed on the exposed underlying layer 820a by electrolytic plating using the underlying layer 820a as a conductive path. In this embodiment, a suppressor and an accelerator are added to the plating solution during electroplating, and the portion of the underlying layer 820a located on the bottom surface 801a of the recess 801 is more affected than the portion located on the main surface 810a. , Plating deposits and grows preferentially. Thereby, the plating layer 820b is formed so as to fill the through hole 851d of the second portion 851b of the resin layer 851. Next, as shown in FIG. After that, by removing the resist layer, the plated layer 820b shown in FIGS. 14 and 15 is formed.

Next, as shown in FIG. 16, a bonding layer 842 is formed. The bonding layer 842 corresponds to the bonding layer 42 of the semiconductor device A10. The bonding layer 842 is formed by photolithographic patterning and electroplating. In the step of forming the bonding layer 842 (bonding layer forming step), first, a resist layer (not shown) for forming the bonding layer 842 is formed on the plating layer 820b, and the resist layer is patterned. This patterning exposes a portion of the plating layer 820b (the portion forming the bonding layer 842) from the resist layer. Then, a bonding layer 842 is formed in contact with a portion of the plating layer 820b exposed from the resist layer by electroplating using the underlying layer 820a and the plating layer 820b as a conductive path. After that, the resist layer is removed. In this embodiment, lead-free solder such as Sn--Ag alloy or Sn--Sb alloy is used as the material of the bonding layer 842. FIG.

Next, as shown in FIG. 17, all unnecessary base layers 820a that are not covered with the plating layer 820b are removed from the base material 810. Next, as shown in FIG. Wet etching is used to remove the unnecessary base layer 820a. This wet etching uses, for example, a mixed solution of H ₂ SO ₄ (sulfuric acid) and H ₂ O ₂ (hydrogen peroxide). As shown in FIG. 17, the resin layer 851 is exposed from the removed portion of the underlying layer 820a by removing the unnecessary underlying layer 820a (underlying layer removing step). Further, the first electrode 820 is formed by removing the base layer 820a. The first electrode 820 includes a first conductive portion 821 formed on the first main surface 811a and a second conductive portion 822 filled in the through hole 851d of the second portion 851b of the resin layer 851 . The first electrode 820 corresponds to the first electrode 20 of the semiconductor device A10. Therefore, the steps including the base layer forming step, the plated layer forming step, and the base layer removing step correspond to the "first electrode forming step" recited in the claims.

Next, as shown in FIGS. 18 and 19, a semiconductor element 841 is mounted on the base material 810 . The semiconductor element 841 corresponds to the semiconductor element 41 of the semiconductor device A10. The process of mounting the semiconductor element 841 (semiconductor element mounting process) is performed by FCB (Flip Chip Bonding). After applying flux to the electrode bumps (not shown) of the semiconductor element 841 , the semiconductor element 841 is temporarily attached to the bonding layer 842 with the element main surface 841 a facing the substrate 810 using a flip chip bonder. At this time, the bonding layer 842 is sandwiched between both the first electrode 820 and the semiconductor element 841 . Next, after the bonding layer 842 is melted by reflow, the bonding layer 842 is solidified by cooling, thereby completing the mounting of the semiconductor element 841 . In addition, in FIG. 18 (the same applies to FIGS. 20, 21, 23, 25, and 27), the base layer 820a and the plated layer 820b are shown as the first electrode 820 without distinction.

Next, as shown in FIG. 20, a sealing resin 860 covering the semiconductor element 841 is formed. The sealing resin 860 corresponds to the sealing resin 60 of the semiconductor device A10. The sealing resin 860 according to the present embodiment is a synthetic resin having electrical insulation, for example, a black epoxy resin as a main component. In the process of forming the sealing resin 860 (sealing resin forming process), the sealing resin 860 is formed on the base material 810 so as to cover the semiconductor element 841 without exposing it.

Next, as shown in FIGS. 21 and 22, the base material 810 is ground from the rear surface 810b side. In the step of grinding the base material 810 (grinding step), the grinding is performed until the first electrode 820 (second conductive portion 822) is exposed. Through the grinding process, the base material 810 located below the recess 801 in the thickness direction z is scraped off. Moreover, the insulating layer 815 covering the bottom surface 801a of the recess 801 is also scraped off, and the exposed surface 822a of the second conductive portion 822 appears. The exposed surface 822a corresponds to the connection surface 221 of the second conductive portion 22 of the semiconductor device A10. Further, the grinding process divides the base material 810 into a substrate 811 and a plurality of substrates 812 . A substrate 811 and a substrate 812 correspond to the substrate 11 and the substrate 12 of the semiconductor device A10, respectively. A semiconductor element 841 is mounted on the substrate 811 . Each substrate 812 is spaced apart from substrate 811 . The substrate 811 and the plurality of substrates 812 are fixed with a sealing resin 860 . Between the substrate 811 and each substrate 812, the second conductive portion 822 of the first electrode 820 and the second portion 851b of the resin layer 851 are arranged.

Next, as shown in FIGS. 23 and 24, a resin layer 852 is formed. The resin layer 852 corresponds to the external resin layer 52 of the semiconductor device A10. The step of forming the resin layer 852 (external resin layer forming step) is performed by screen printing. A portion of the resin layer 852 is opened, and a portion of the back surface of the substrate 812, a portion of the second portion 851b of the resin layer 851, and the exposed surface 822a are exposed from the opened portion. Thereby, the resin layer 852 shown in FIGS. 23 and 24 is formed.

Next, as shown in FIGS. 25 and 26, the surface (second side surface 812c) of each substrate 812 opposite to the surface facing the substrate 811 is exposed. The second side surface 812c corresponds to the exposed side surface 123a of the substrate 12 of the semiconductor device A10. In the step of exposing the second side surface 812c (side surface exposing step), a groove 869 is formed in the rear surface of the sealing resin 860 by half-cut dicing using blade dicing. In this embodiment, the grooves 869 are formed in a grid pattern in which stripes extending along the first direction x and stripes extending along the second direction y intersect. By forming the groove 869, the second side surface 812c of the substrate 812 is exposed.

Next, as shown in FIGS. 27 and 28, a second electrode 830 is formed. The second electrode 830 corresponds to the second electrode 30 of the semiconductor device A10. The step of forming the second electrode 830 (second electrode forming step) is by electroless plating. In this embodiment, the Ni layer, the Pd layer, and the Au layer are deposited in this order by electroless plating. At this time, the Ni layer is formed so as to contact and cover the exposed surface 822a of the first electrode 820 exposed from the resin layer 852, part of the back surface of the substrate 812, and the second side surface 812c. A Pd layer is formed on the Ni layer, and an Au layer is formed on the Pd layer. Thereby, the second electrode 830 shown in FIGS. 27 and 28 is formed. Therefore, the resin layer 852 is also used as a mask layer that defines the region where the second electrode 830 is to be formed. The second electrode 830 covers the first electrode covering portion 831 covering the exposed surface 822a of the first electrode 820, the second rear covering portion 832 covering part of the rear surface of the substrate 812, and the second side surface 812c of the substrate 812. It includes exposed side coverings 833 . The exposed side covering portion 833 is formed inside the groove 869 . Note that the second electrode 830 is not formed on the surfaces of the sealing resin 860 and the resin layer 852 by electroless plating in the second electrode forming step.

Next, by cutting the sealing resin 860 along the first direction x and the second direction y, the semiconductor elements 841 are divided into individual pieces. The step of cutting the sealing resin 860 (cutting step) is performed by blade dicing. In the blade dicing, a dicing blade thinner than the dicing blade used in the side exposure step is used. For example, in the cutting step, other dicing methods such as laser dicing or plasma dicing may be used instead of blade dicing. In this embodiment, the semiconductor element 841 is divided into individual pieces by cutting along the cutting line CL shown in FIG. Through the cutting step, the individual piece becomes the semiconductor device A10. A cutting line CL extending in the first direction x shown in FIG. 28 is set so as to pass through the center in the width direction of the groove 869 extending in the first direction x in plan view. Similarly, a cutting line CL extending in the second direction y direction shown in FIG. 28 is set so as to pass through the center of the width direction of the groove 869 extending in the second direction y in plan view. In this embodiment, the width of the processed line at the time of cutting in the cutting step is made narrower than the width of the groove 869 . Therefore, the side surface of the sealing resin 860 after cutting has a recess due to the groove 869 . The recess corresponds to the recess 632 of the resin side surface 63 of the semiconductor device A10. Through the above steps, the semiconductor device A10 is manufactured.

Next, the effects of the semiconductor device A10 and the manufacturing method thereof according to the first embodiment will be described.

The semiconductor device A10 includes the first electrode 20 formed by electrolytic plating and the second electrode 30 formed by electroless plating. Therefore, the semiconductor device A10 is wired by plating and does not use a lead frame formed of a metal plate. Wiring by plating can be made thinner than when a leadframe structure is used. Therefore, the thickness of the semiconductor device A10 can be reduced.

According to the semiconductor device A10, the first electrode 20 and the second electrode 30 are provided. The first electrode 20 is electrically connected to the semiconductor element 41 and is connected to the second electrode 30 through the substrate 11 and the substrates 12 which are separated from each other. The second electrode 30 is exposed to the outside of the semiconductor device A10 and formed by electroless plating so as to be in contact with the first electrode 20 and the substrate 12 . The second electrode 30 is a terminal for mounting the semiconductor device A10 on a circuit board. In a semiconductor device having a lead frame structure different from that of the semiconductor device A10, there is a case where the lead frame, sealing resin, and the like are collectively cut by, for example, blade dicing in the manufacturing process. During this dicing, the metal that is the material of the lead frame may be stretched and burrs (metal burrs) may be generated at the cut portion. Such metal burrs may cause poor connection between the lead portion and the circuit board when the circuit board or the like is mounted, resulting in poor mounting. In addition, such metal burrs may short-circuit adjacent lead portions, causing malfunction. On the other hand, in the manufacturing method of the semiconductor device A10, the second electrode 30 is formed by electroless plating, and the second electrode 30 (the second electrode 830) is not cut. Therefore, it is possible to suppress the occurrence of the metal burrs in the terminal for external connection (second electrode 30). As a result, the semiconductor device A10 can suppress defective mounting and defective operation caused by metal burrs.

According to the semiconductor device A10, as shown in FIG. 6, the connection surface 221 and the second rear surface 122 are flush with each other. By adopting such a configuration, the surfaces exposed to the outside of the first electrode covering portion 31 covering the connection surface 221 and the second rear surface covering portion 32 covering the second rear surface 122 are flush with each other. That is, the bottom surface side portion of the second electrode 30 can be made flush.

According to the semiconductor device A10, the second electrode 30 includes the exposed side covering portion 33. As shown in FIG. When the semiconductor device A10 is mounted on a circuit board or the like, it is electrically connected with solder. If the exposed side surface covering portion 33 is not provided, it is necessary to check the connection state of the solder between the first electrode covering portion 31 and the second back surface covering portion 32 and the circuit board. had to use. However, in this embodiment, the solder that electrically connects the semiconductor device A10 and the circuit board can be formed so as to cover the exposed side covering portion 33 . Therefore, by adopting such a configuration, the connection state of the solder can be visually confirmed from the side surface of the semiconductor device A10.

According to the semiconductor device A10, the second electrode 30 includes a first electrode covering portion 31, a second back surface covering portion 32, and an exposed side covering portion 33, all of which are shown in FIGS. , overlaps the sealing resin 60 in plan view. That is, it does not protrude outside the sealing resin 60 in plan view. By adopting such a configuration, a leadless package type semiconductor device A10 can be realized. In particular, the semiconductor device A10 includes a plurality of substrates 12 separated from each other, and the plurality of substrates 12 are covered with the second electrodes 30, respectively. Therefore, in this embodiment, a QFN package type semiconductor device A10 can be realized.

According to the semiconductor device A10, the material of the substrate 12 is silicon. As with the metal such as Cu of the first electrode 20, the silicon is deposited by electroless plating. That is, the second electrode 830 (the second electrode 30 in the semiconductor device A10) becomes the substrate 812 (the substrate 12 in the semiconductor device A10) and the first electrode 820 (the first electrode in the semiconductor device A10) by electroless plating in the second electrode forming step. It is simultaneously deposited on the electrode 20). Therefore, in the second electrode forming step, the first electrode covering portion 831, the second back covering portion 832, and the exposed side covering portion 833 (the first electrode covering portion 31, the second back covering portion 32, and And the exposed side covering portion 33) can be formed at the same time.

[Second embodiment]
29 and 30 show a semiconductor device according to the second embodiment of the present disclosure. In the following description, elements that are the same as or similar to those of the first embodiment are denoted by the same reference numerals, and overlapping descriptions are omitted. The semiconductor device A20 of this embodiment differs from the semiconductor device A10 of the first embodiment in that it includes a heat dissipation layer 70 .

FIG. 29 is a bottom view showing the semiconductor device A20. FIG. 30 is a cross-sectional view of the semiconductor device A20, corresponding to the cross-section shown in FIG. 6 of the first embodiment.

As shown in FIG. 30, the substrate 11 in this embodiment has a through hole 114 extending from the first main surface 111 to the first rear surface 112 in the thickness direction z. The through hole 114 has a rectangular shape in plan view, as shown in FIG. The through hole 114 is filled with the heat dissipation layer 70 .

The heat dissipation layer 70 is for dissipating heat generated from the semiconductor element 41 . In this embodiment, the heat dissipation layer 70 is made of the same material as the first electrode 20 . That is, the heat dissipation layer 70 is made of metal containing Cu. As shown in FIG. 30, the heat dissipation layer 70 is arranged in the direction in which the element rear surface 412 of the semiconductor element 41 faces in the thickness direction z. The heat dissipation layer 70 has a rectangular shape in plan view, as shown in FIG. The heat dissipation layer 70 overlaps the semiconductor element 41 in plan view. In addition, the heat dissipation layer 70 is arranged at the same position as the first electrode 20 (second conductive portion 22) in the thickness direction z. In this embodiment, as shown in FIG. 29, the heat dissipation layer 70 is separated from the semiconductor element 41 in the thickness direction z, and the sealing resin 60 is interposed in the separated region. Note that the heat dissipation layer 70 may be in direct contact with the semiconductor element 41 or may be joined with a joining material (not shown). The heat dissipation layer 70 makes the substrate 11 have a rectangular ring shape in a plan view. The heat dissipation layer 70 has a heat dissipation layer rear surface 72 .

The heat dissipation layer back surface 72 faces the same direction as the first back surface 112 . The heat dissipation layer rear surface 72 is flush with the first rear surface 112 . The heat dissipation layer rear surface 72 is exposed from the external resin layer 52 .

The second electrode 30 in the present embodiment further includes a heat dissipation layer back surface covering portion 34 as shown in FIGS. 29 and 30 . The heat dissipation layer back surface covering portion 34 covers the heat dissipation layer back surface 72 . In the first embodiment, the heat dissipation layer back surface covering portion 34 is formed by electroless plating during the second electrode forming step. The heat dissipation layer rear surface covering portion 34 is formed at the same time as the first electrode covering portion 31 , the second rear surface covering portion 32 , and the exposed side surface covering portion 33 . The heat dissipation layer back surface 72 may be covered with the external resin layer 52 without being covered with the heat dissipation layer back surface covering portion 34 . However, in order to improve the heat dissipation efficiency of the heat dissipation layer 70, it is desirable to cover the back surface of the heat dissipation layer 70 with the cover portion 34. FIG.

An example of a method for manufacturing the semiconductor device A20 will be described with reference to FIGS. 31 to 35. FIG. The description of the parts common to the manufacturing method of the semiconductor device A10 according to the first embodiment will be omitted. 31 to 35, except for FIG. 32, are cross-sectional views for explaining the manufacturing process of the semiconductor device A20, which are the same as the cross-section shown in FIG. FIG. 32 is a plan view for explaining the manufacturing process of the semiconductor device A20.

A substrate 810 having a main surface 810a and a back surface 810b facing the thickness direction z is prepared in the same manner as in the manufacturing method according to the first embodiment. Then, a concave portion 801 is formed in the base material 810 so as to be depressed from the main surface 810a in the thickness direction z. In this embodiment, when the recess 801 is formed, a recess 802 recessed in the thickness direction z is also formed. Note that the recess 801 and the recess 802 may be formed at the same time or separately. The recess 802 is spaced apart from the recess 801 . The recess 802 has a bottom surface 802a and an upright surface 802b. The bottom surface 802a has a rectangular shape in plan view. The bottom surface 802a is at the same position as the bottom surface 801a of the recess 801 in the thickness direction z. The bottom surface 802a is surrounded by the first main surface 811a in plan view. The upright surface 802b has an upper end shown in FIG. 31 connected to the first main surface 811a and a lower end shown in FIG. 31 connected to the bottom surface 802a. The standing surface 802b stands up from the bottom surface 802a and is perpendicular to the bottom surface 802a. The recess 802 is formed by dry etching in the same manner as the recess 801 . The recess 802 may be formed by wet etching as in the first embodiment.

Then, similarly to the manufacturing method according to the first embodiment, an insulating layer forming process, an internal resin layer forming process, an underlying layer forming process, and a plated layer forming process are performed. As a result, unlike the first embodiment, as shown in FIG. 33, a plated layer 820c filling the recess 802 is further formed. The plating layer 820c is of the same quality as the plating layer 820b.

Next, a bonding layer forming step and a base layer removing step are performed in the same manner as in the manufacturing method according to the first embodiment. In this embodiment, after the base layer removing step, as shown in FIG. 34, a heat dissipation layer 870 is formed of the plating layer 820c and the base layer 820a covered with the plating layer 820c. The heat dissipation layer 870 corresponds to the heat dissipation layer 70 of the semiconductor device A20.

Next, similarly to the manufacturing method according to the first embodiment, a semiconductor element mounting step, a sealing resin forming step, a grinding step, an external resin layer forming step, a side surface exposing step, a second electrode forming step, and a cutting step are performed. conduct. In the present embodiment, in the grinding step, grinding is performed until the first electrode 820 (second conductive portion 822) is exposed and the heat dissipation layer 870 (heat dissipation layer rear surface 872) is also exposed. In addition, in the external resin layer forming step, the exposed heat dissipation layer rear surface 872 is not covered with the resin layer 852 and is left exposed. As a result, as shown in FIG. 35, a heat dissipation layer back surface covering portion 834 covering the heat dissipation layer back surface 872 is formed during the second electrode forming step (electroless plating). The heat dissipation layer back surface covering portion 834 corresponds to the heat dissipation layer back surface covering portion 34 of the second electrode 30 of the semiconductor device A20. Through the steps described above, the semiconductor device A20 shown in FIGS. 29 and 30 is manufactured.

According to the semiconductor device A20, similarly to the first embodiment, it is possible to suppress the occurrence of metal burrs in the terminals for external connection (second electrodes 30). Therefore, the semiconductor device A20 can suppress defective mounting and defective operation caused by metal burrs.

According to the semiconductor device A20, the heat dissipation layer 70 is provided. Therefore, the heat emitted from the semiconductor element 41 is released by the heat dissipation layer 70, so that the semiconductor device A20 can improve heat dissipation compared to the semiconductor device A10.

[Third embodiment]
FIG. 36 shows a semiconductor device according to the third embodiment of the present disclosure. In the following description, elements that are the same as or similar to those in the first and second embodiments are denoted by the same reference numerals, and overlapping descriptions are omitted. The semiconductor device A20 of this embodiment differs from the semiconductor device A10 of the first embodiment in that the first side surface 113 of the substrate 11 and the second side surface 123 of the substrate 12 (excluding the exposed side surface 123a) are inclined. different in

FIG. 36 is a cross-sectional view of the semiconductor device A30, corresponding to the cross-section shown in FIG. 6 of the first embodiment.

In the substrate 11 according to this embodiment, each first side surface 113 is inclined with respect to the first rear surface 112 as shown in FIG. The angle between each first side surface 113 and the first back surface 112 is about 55°. Therefore, the dimension of the cross section of the substrate 11 parallel to the first back surface 112 increases from the first main surface 111 toward the first back surface 112 in the thickness direction z.

In the substrate 12 according to this embodiment, each second side surface 123 excluding the exposed side surface 123 a is inclined with respect to the second back surface 122 . The angle formed by each second side surface 123 excluding the exposed side surface 123a and the second rear surface 122 is about 55°. Note that the exposed side surface 123a is orthogonal to the second main surface 121 and the second rear surface 122, as in the first embodiment.

An example of a method for manufacturing the semiconductor device A30 will be described with reference to FIGS. 37 and 38. FIG. The description of the parts common to the manufacturing method of the semiconductor device A10 according to the first embodiment will be omitted. The method for manufacturing the semiconductor device A30 differs from the method for manufacturing the semiconductor device A10 in the recess forming process.

FIG. 37 is a cross-sectional view for explaining the manufacturing process of the semiconductor device A30, which is the same as the cross-section shown in FIG. FIG. 38 is a plan view for explaining the manufacturing process of the semiconductor device A30.

The recess forming step according to the present embodiment is performed by wet etching instead of dry etching. Specifically, in the substrate preparation step, the (100) plane having the (100) crystal orientation is employed as the main surface 810a. Then, recesses 803 are formed by anisotropic etching using KOH (potassium hydroxide), for example. KOH is an example of an alkaline etching solution that can achieve good anisotropic etching for Si single crystals. The recess 803 has a bottom surface 803a and a plurality of upright surfaces 803b. The upright surface 803b forms an angle of about 55° with respect to the bottom surface 803a. The etching solution is not limited to KOH, and may be an alkaline solution such as TMAH (tetramethylammonium hydroxide) or EDP (ethylenediaminepyrocatel).

In subsequent processes, the insulating layer forming process, the internal resin layer forming process, the base layer forming process, the plating layer forming process, the bonding layer forming process, the base layer removing process, the semiconductor element mounting process, The sealing resin forming process, the grinding process, the external resin layer grinding process, the side exposing process, the second electrode forming process, and the cutting process are performed in the same manner. In this embodiment, in the side surface exposure step, the grooves 869 are formed in the portions corresponding to the two-dot chain lines in FIGS. A second side surface 812c is formed that is perpendicular to the . Through the above steps, the semiconductor device A30 shown in FIG. 36 is manufactured.

According to the semiconductor device A30, similarly to the first embodiment, it is possible to suppress the generation of metal burrs in the terminals for external connection (second electrodes 30). Therefore, the semiconductor device A30 can suppress defective mounting and defective operation caused by metal burrs.

According to semiconductor device A30, first side surface 113 and second side surface 123 (excluding exposed side surface 123a) are inclined. This inclination originates from the upright surface 803b of the recess 803 formed in the recess forming step. Since the upright surface 803b is inclined in the concave portion 803, the upright surface 803b is opened upward compared to the case where the upright surfaces 801b and 802b are upright as in the first and second embodiments. there is Therefore, the thicknesses of the insulating layer 815, the resin layer 851, the underlying layer 820a, and the like covering the upright surface 803b can be easily made uniform. However, if the standing surface 803b is inclined, the outer shape in plan view becomes large. In other words, in the semiconductor devices A10 and A20, when the upright surfaces 801b and 802b stand upright, the size in plan view can be reduced.

In this embodiment, the case where the heat dissipation layer 70 is not provided is shown, but the heat dissipation layer 70 may be provided as in the second embodiment.

In the first to third embodiments, each second electrode 30 includes the exposed side covering portion 33, but the exposed side covering portion 33 may not be included. For example, in the above-described first embodiment, by performing the electroless plating in the second electrode forming step without performing the side surface exposing step, that is, without forming the groove 869, the second electrode not including the exposed side surface covering portion 33 is formed. An electrode 30 can be formed. In this modification, the resin layer 852 is cut along the cutting line CL in the external resin layer forming process so that the second electrode 830 is not cut when the sealing resin 860 is cut along the cutting line CL (during the cutting process). should be formed in In other words, it is preferable to form the resin layer 852 on the cutting line CL so that the second electrode 830 is not formed in the second electrode forming step. Even in such a case, since the second electrode 30 (second electrode 830) is not cut, it is possible to suppress the occurrence of metal burrs in the terminal for external connection (second electrode 30). .

[Fourth embodiment]
39 and 40 show a semiconductor device according to the fourth embodiment of the present disclosure. The semiconductor device A40 of the fourth embodiment differs from the semiconductor device A10 in the shape of the concave portion 632 formed in each resin side surface 63 of the sealing resin 60 . FIG. 39 is a cross-sectional view showing the semiconductor device A40, corresponding to the cross-section shown in FIG. FIG. 40 is a partially enlarged sectional view enlarging a part of FIG. 39. FIG.

Each recess 632 of the semiconductor device A40 has a first surface 632a and a second surface 632b, as shown in FIG. In each recess 632 , the first surface 632 a faces the same direction as the flat portion 631 connected to the recess 632 . The first surface 632a is substantially parallel to the thickness direction z. The first surface 632 a is flush with the exposed side surface 123 a of the substrate 12 . In each recess 632, the second surface 632b connects to the first surface 632a of the recess 632 and to the flat portion 631 of the resin side surface 63 on which the recess 632 is formed. The second surface 632b is a curved surface. As shown in FIG. 40, a boundary edge 632c between the second surface 632b and the flat portion 631 is located above a boundary edge 632d between the second surface 632b and the first surface 632a in the thickness direction z. Each boundary edge 632c, 632d extends along either the first direction x or the second direction y. Also in the semiconductor devices A10, A20, A30, each recess 632 has a first surface 632a and a second surface 632b. However, the second surfaces 632b of the semiconductor devices A10, A20, A30 are flat, and the two boundary edges 632c, 632d are at approximately the same position in the thickness direction z.

In the semiconductor device A40, for example, when half-cut dicing is performed in the side exposure process, the bottom 869a of the formed groove 869 may be curved as shown in FIG. In FIG. 41, groove 869 is recessed in a U shape. In this way, when the groove 869 with the curved bottom portion 869a is formed, the subsequent process (especially the cutting process) is performed to form the second surface 632b that is a curved surface. 41 is a cross-sectional view for explaining one step (side surface exposure step) of the manufacturing method of the semiconductor device A40, and corresponds to the cross-section of FIG.

According to the semiconductor device A40, the same effects as those of the semiconductor device A10 can be obtained.

[Fifth embodiment]
42 to 48 show a semiconductor device according to the fifth embodiment of the present disclosure. A semiconductor device A50 of the fifth embodiment includes a substrate 13, an insulating layer 15, a first electrode 20, a second electrode 30, a semiconductor element 41, a bonding layer 42, an internal resin layer 51, an external resin layer 52, and a sealing resin. 60.

FIG. 42 is a plan view showing the semiconductor device A50. In FIG. 42, the semiconductor element 41 and the sealing resin 60 are indicated by imaginary lines (double-dot chain lines), and the insulating layer 15 and the inner resin layer 51 are omitted. FIG. 43 is a bottom view showing the semiconductor device A50. FIG. 44 is a side view showing the semiconductor device A50. 45 is a cross-sectional view along the XLV-XLV line in FIG. 42. FIG. FIG. 46 is a partially enlarged sectional view enlarging a part of FIG. 45. FIG. 47 is a cross-sectional view taken along line XLVII--XLVII in FIG. 42. FIG. FIG. 48 is a partially enlarged sectional view enlarging a part of FIG. 47. FIG.

The substrate 13 is made of the same material as the substrate 11 . That is, the substrate 13 is made of an intrinsic semiconductor material of Si. The substrate 13, as shown in FIG. 47, has a main surface 13a and a back surface 13b.

As shown in FIG. 47, the main surface 13a and the back surface 13b are separated from each other in the thickness direction z and face opposite sides. The main surface 13a is the upper surface of the substrate 13 and faces upward in the thickness direction z. The back surface 13b is the lower surface of the substrate 13 and faces downward in the thickness direction z. In this embodiment, the substrate 13 corresponds to the "first substrate" described in the claims, and the main surface 13a (the main surface 131a and the main surface 132a) corresponds to the "first main substrate" described in the claims. The back surface 13b (the back surface 131b and the back surface 132b) corresponds to the "first back surface" described in the claims.

The substrate 13 includes a support portion 131 and a plurality of projecting portions 132, as shown in FIGS. It should be noted that the substrate 13 may be composed only of the supporting portion 131 without including the plurality of protruding portions 132 .

The support portion 131 is a portion that supports the semiconductor element 41 . The support portion 131 has a rectangular shape in plan view. The support portion 131, as shown in FIG. 45, has a main surface 131a, a back surface 131b and a plurality of side surfaces 131c.

As shown in FIG. 45, the main surface 131a and the back surface 131b are separated from each other in the thickness direction z and face opposite sides. The main surface 131a is the upper surface of the support portion 131 and faces upward in the thickness direction z. Main surface 131a is a portion of main surface 13a. The back surface 131b is the lower surface of the support portion 131 and faces downward in the thickness direction z. The back surface 131b is part of the back surface 13b.

Each of the plurality of side surfaces 131c is sandwiched between the main surface 131a and the back surface 131b in the thickness direction z, as shown in FIG. Each side surface 131c is flat and perpendicular to both the main surface 131a and the back surface 131b. Each side surface 131 c is in contact with the sealing resin 60 . The support portion 131 has a pair of side surfaces 131c that are spaced apart in the first direction and face opposite to each other, and a pair of side surfaces 131c that are spaced apart in the second direction and face opposite to each other, a total of four side faces 131c.

As shown in FIGS. 42 and 43, each of the projections 132 protrudes from one of the side surfaces 131c in plan view. In the embodiment shown in FIG. 42, the substrate 13 has three protruding portions 132 protruding from each side surface 131c of the supporting portion 131, and the three protruding portions 132 extend in the first direction x or the second direction in plan view. lined up in y. Also, the three protruding portions 132 are spaced apart in plan view, and a portion of the first electrode 20 and a portion of the sealing resin 60 are arranged between them. Each projecting portion 132 has a rectangular shape in plan view. Each protrusion 132 has a main surface 132a, a back surface 132b and a side surface 132c, as shown in FIG.

As shown in FIG. 47, the main surface 132a and the back surface 132b are separated from each other in the thickness direction z and face opposite sides. The main surface 132a is the upper surface of the projecting portion 132 and faces upward in the thickness direction z. The major surface 132a is flush with the major surface 131a. Main surface 132a is a portion of main surface 13a. The back surface 132b is the lower surface of the projecting portion 132 and faces downward in the thickness direction z. The back surface 132b is flush with the back surface 131b. The back surface 132b is part of the back surface 13b.

As shown in FIG. 47, the side surface 132c is located on the opposite side of each projecting portion 132 from the side connected to the support portion 131. As shown in FIG. As shown in FIG. 47, the side surface 132c is sandwiched between the main surface 132a and the back surface 132b in the thickness direction z. The side surface 132c is flat and perpendicular to both the main surface 132a and the back surface 132b. Side surface 132 c is covered with insulating layer 15 , internal resin layer 51 and sealing resin 60 . Side surface 132 c may be exposed to the outside of semiconductor device A 50 , may be covered only with insulating layer 15 , or may be covered with insulating layer 15 and internal resin layer 51 .

As shown in FIGS. 45 and 47, the insulating layer 15 covers the surfaces of the substrate 13 excluding the back surface 13b.

Each of the plurality of first electrodes 20 includes a first conductive portion 23, a second conductive portion 24 and a third conductive portion 25 in the semiconductor device A50, as shown in FIGS.

The first conductive portion 23 is partially formed on the main surface 131a of the support portion 131 of the substrate 13, as shown in FIG. A bonding layer 42 is formed on the first conductive portion 23 . The first conductive portion 23 is composed of a foundation layer and a plated layer that are laminated to each other. The underlying layer is composed of, for example, a Ti layer and a Cu layer laminated together. The Ti layer is in contact with the inner resin layer 51, and the Cu layer is in contact with the plating layer. The material of the plating layer is Cu, for example. The plated layer is thicker than the underlying layer. The underlying layer and the plating layer are integrated.

The second conductive portion 24 is connected to the first conductive portion 23 and the third conductive portion 25, as shown in FIG. A portion of the second conductive portion 24 overlaps the substrate 13 when viewed in either the first direction x or the second direction y. The second conductive portion 24 is composed of a plated layer. The material of the plating layer is Cu, for example. In addition, the second conductive portion 24 may be composed of a base layer and a plated layer that are laminated to each other. The underlying layer is composed of, for example, a Ti layer and a Cu layer laminated together. The Cu layer contacts the plating layer.

The second conductive portion 24 has a main surface 241, a back surface 242, a first side surface 243 and a second side surface 244, as shown in FIG. The main surface 241 and the back surface 242 are spaced apart and face opposite sides in the thickness direction z. The main surface 241 is the upper surface of each second conductive portion 24 and faces upward in the thickness direction z. The main surface 241 is in contact with the sealing resin 60 . The rear surface 242 is the lower surface of each second conductive portion 24 and faces downward in the thickness direction z. The back surface 242 is flush with the resin back surface 62 of the sealing resin 60, as shown in FIG. Both the first side surface 243 and the second side surface 244 are connected to the back surface 242 and substantially parallel to the thickness direction z. Both the first side surface 243 and the second side surface 244 are connected to the back surface 242 at the lower edges in the thickness direction z. The first side surface 243 and the second side surface 244 face opposite sides in either the first direction x or the second direction y. The first side surface 243 faces the side surface 131c of the support portion 131 (substrate 13) with a portion of the insulating layer 15 and a portion of the internal resin layer 51 interposed therebetween. The second side surface 244 is exposed from the sealing resin 60 .

The third conductive portion 25 is connected to the second conductive portion 24 as shown in FIG. The third conductive portion 25 protrudes from the main surface 241 of the second conductive portion 24 in the thickness direction z. A boundary between the third conductive portion 25 and the second conductive portion 24 is flush with the main surface 241 . The third conductive portion 25 is composed of a plated layer. The material of the plating layer is Cu, for example.

The third conductive portion 25 has a first surface 251, a second surface 252, a third surface 253, a fourth surface 254 and a fifth surface 255, as shown in FIG.

The first surface 251 is flush with the second side surface 244 . The first surface 251 is positioned between the second surface 252 and the fifth surface 255 in plan view. The second surface 252 is located outside the semiconductor device A50 relative to the first surface 251 in plan view. The second surface 252 is flush with the flat portion 631 of the sealing resin 60 . A third surface 253 connects the first surface 251 and the second surface 252 . In this embodiment, the third surface 253 is flat. The third surface 253 faces downward in the thickness direction z. The fourth surface 254 faces upward in the thickness direction z. A fourth surface 254 connects to the second surface 252 . The fourth surface 254 contacts the sealing resin 60 . The fifth surface 255 is substantially parallel to the thickness direction z. Fifth surface 255 connects to fourth surface 254 . The fifth surface 255 contacts the sealing resin 60 . Fifth surface 255 connects to main surface 241 .

In each third conductive portion 25 , the fifth surface 255 is located between the first side surface 243 and the second side surface 244 in plan view, and the second surface 252 is located further than the second side surface 244 in plan view. It is located outside the semiconductor device A50. Therefore, the fifth surface 255 overlaps the second conductive portion 24 in plan view, and the second surface 252 does not overlap the second conductive portion 24 in plan view.

Each third conductive portion 25 has a first boundary edge 25a and a second boundary edge 25b each extending along either the first direction x or the second direction y. The first boundary edge 25 a is the boundary between the first surface 251 and the third surface 253 . The second boundary edge 25 b is the boundary between the second surface 252 and the third surface 253 . The first boundary edge 25a and the second boundary edge 25b are arranged at substantially the same position in the thickness direction z.

In the first electrode 20, the separation distance in the thickness direction z between the rear surface 242 of the second conductive portion 24 and the fourth surface 254 of the third conductive portion 25 is, for example, about 100 μm. That is, in the first electrode 20, the thickness of the portion where the second conductive portion 24 and the third conductive portion 25 are stacked is approximately 100 μm, for example. In addition, the said dimension is an example and is not limited to this.

As shown in FIGS. 45 and 46, the second electrode 30 is electrically connected to the first electrode 20 and exposed to the outside of the semiconductor device A50. The second electrode 30 is made of a conductive material. The second electrode 30 can be composed of, for example, a Ni layer, a Pd layer, and an Au layer that are stacked together, similar to the second electrode 30 of the semiconductor device A10. The second electrode 30 is a terminal for mounting the semiconductor device A50 on a circuit board. The second electrode 30 entirely overlaps the sealing resin 60 in plan view. The second electrode 30 includes a first covering portion 35, a second covering portion 36 and a third covering portion 37 in the semiconductor device A50.

The first covering portion 35 covers part of the back surface 242 of the second conductive portion 24, as shown in FIG. The second covering portion 36 covers the second side surface 244 of the second conductive portion 24 and the first surface 251 of the third conductive portion 25, as shown in FIG. The second covering portion 36 is connected to the first covering portion 35 . The third covering portion 37 covers the third surface 253 of the third conductive portion 25, as shown in FIG. The third covering portion 37 is connected to the second covering portion 36 .

As shown in FIG. 45, the semiconductor element 41 is mounted on the supporting portion 131 of the substrate 13 in the semiconductor device A50, and overlaps the supporting portion 131 of the substrate 13 in plan view.

As shown in FIG. 45, the bonding layer 42 is interposed between the first conductive portion 23 of the first electrode 20 and the semiconductor element 41 (electrode pad 413) in the semiconductor device A50. The electrode pad 413 and the first conductive portion 23 are electrically connected through the bonding layer 42 .

The internal resin layer 51 covers the insulating layer 15, as shown in FIGS. Note that the semiconductor device A50 may not include the internal resin layer 51 .

As shown in FIGS. 43, 45 and 46, the external resin layer 52 includes the entire back surface 13b of the substrate 13, the entire resin back surface 62 of the sealing resin 60, and the second conductive portion 24 (first electrode 20 ) covers a portion of the back surface 242 of the . The back surface 242 of the second conductive portion 24 exposed from the external resin layer 52 is covered with the second electrode 30 (first covering portion 35).

In the sealing resin 60 of the semiconductor device A50, the concave portion 632 of each resin side surface 63 has a first surface 632a and a second surface 632b, as shown in FIG.

In each recess 632 of the semiconductor device A50, as shown in FIG. 48, the first surface 632a and the second surface 632b are connected and both are flat. The first surface 632a is flush with the second side surface 244 of the second conductive portion 24 (first electrode 20) and the first surface 251 of the third conductive portion 25 (first electrode 20). The second surface 632b is flush with the third surface 253 of the third conductive portion 25 (first electrode 20). The second surface 632b faces downward in the thickness direction z. The first surface 632 a and the second surface 632 b are not covered with the second electrode 30 . That is, the first surface 632 a and the second surface 632 b are exposed from the second electrode 30 .

Next, an example of a method for manufacturing the semiconductor device A50 will be described with reference to FIGS. 49 to 64. FIG. 49 to 64, FIGS. 50, 53 and 55 are plan views showing one step relating to the method of manufacturing the semiconductor device A50, and FIGS. FIG. 4 is a bottom view showing a step in the method; The drawings other than these are cross-sectional views showing one process related to the method of manufacturing the semiconductor device A50. The cross-sectional view corresponds to the cross-section shown in FIG.

First, as shown in FIGS. 49 and 50, a substrate 810 having a main surface 810a and a back surface 810b facing the thickness direction z is prepared, and the substrate 810 is recessed from the main surface 810a toward the thickness direction z. A recess 801 is formed. In the manufacturing method of this embodiment, the forming range of the concave portion 801 is different from that of the manufacturing method of the first embodiment. The base material 810 will later become the substrate 13 of the semiconductor device A50. The material of the base material 810 and the method of forming the concave portion 801 are the same as in the substrate preparation process according to the first embodiment.

Next, as shown in FIG. 51, an insulating layer 815 and a resin layer 851 are formed in order. A method for forming the insulating layer 815 is the same as the insulating layer forming process according to the first embodiment. The method of forming the resin layer 851 is the same as the resin layer forming process according to the first embodiment.

Next, as shown in FIGS. 52 and 53, a foundation layer 820a, a plated layer 820b and a bonding layer 842 are formed in this order. The method of forming the base layer 820a is the same as the base layer forming process according to the first embodiment. The method of forming the plating layer 820b is the same as the plating layer forming process according to the first embodiment. A method for forming the bonding layer 842 is the same as the bonding layer forming process according to the first embodiment.

Next, as shown in FIGS. 54 and 55, a plating layer 820d is formed. The plating layer 820d will later become part of the first electrode 20 (the third conductive portion 25) of the semiconductor device A50. The plating layer 820d is formed by pattern formation by photolithography and electroplating similarly to the formation of the plating layer 820b. The plating layer 820d is formed on the plating layer 820b and protrudes from the plating layer 820b. Compared with the method for manufacturing the semiconductor device A10, the method for manufacturing the semiconductor device A50 mainly includes the step of forming the plating layer 820d.

Next, as shown in FIG. 56, the unnecessary underlying layer 820a is removed. In this embodiment, the base layer 820a that is not covered with the plating layer 820b and the plating layer 820d is an unnecessary portion. The method for removing the underlying layer 820a is the same as the underlying layer removing step according to the first embodiment. As a result of the underlying layer removing step, the resin layer 851 is exposed from the portion where the underlying layer 820a has been removed, as shown in FIG. Further, the first electrode 820 is formed by removing the base layer 820a. The first electrode 820 includes a first conductive portion 823 , a second conductive portion 824 and a third conductive portion 825 . The first conductive portion 823 is a portion formed on the first main surface 811a. The first conductive portion 823 includes an underlying layer 820a and a plating layer 820b. The second conductive portion 824 is a portion connected to the first conductive portion 823 and filled in the concave portion 801 . The second conductive portion 824 includes an underlying layer 820a and a plating layer 820b. The third conductive portion 825 is formed on the second conductive portion 824 and protrudes from the second conductive portion 824 in the thickness direction z. The third conductive portion 825 includes a plating layer 820d. In the present embodiment, the steps including the base layer forming step, the plated layer forming step, the step of forming the plated layer 820d, and the base layer removing step are included in the “first electrode forming step” recited in the claims. Equivalent to.

Next, as shown in FIG. 57, a semiconductor element 841 is mounted on the substrate 810, and then a sealing resin 860 covering the semiconductor element 841 is formed. A method of mounting the semiconductor element 841 is the same as the semiconductor element mounting process according to the first embodiment. A method of forming the sealing resin 860 is the same as the sealing resin forming process according to the first embodiment.

Next, as shown in FIGS. 58 and 59, the base material 810 is ground from the back surface 810b side. The grinding method of the base material 810 is the same as the grinding process according to the first embodiment. Through the grinding process, as shown in FIG. 58, the rear surface 824b of the second conductive portion 824 is exposed to the outside. At this time, in the second conductive portion 824, the base layer 820a is entirely ground, and the surface layer on the back surface 824b side is made into the plating layer 820b. A part of the base layer 820a may be left and the surface layer on the side of the back surface 824b may be used as the base layer 820a. The back surface 824a corresponds to the back surface 242 of the second conductive portion 24 of the semiconductor device A50. Further, the grinding process divides the base material 810 into a plurality of substrates 813 as shown in FIG. As shown in FIG. 58, each substrate 813 has its rear surface (back surface 813b) exposed to the outside. Each substrate 813 includes a support portion 814a and a plurality of protrusions 814b, as shown in FIG. The support portion 814 a is a portion that supports the semiconductor element 841 . The support portion 814a has a rectangular shape in plan view. Each of the plurality of protruding portions 814b is a portion protruding from the supporting portion 814a in plan view. A substrate 813 corresponds to the substrate 13 of the semiconductor device A50.

Next, as shown in FIGS. 60 and 61, a resin layer 852 is formed. The method of forming the resin layer 852 is the same as the external resin layer forming process according to the first embodiment. As shown in FIG. 61, a part of the rear surface 824b of the second conductive portion 824 (first electrode 820) is exposed from the resin layer 852 formed. The resin layer 852 may be formed so that the entire back surface 824b is exposed.

Then, as shown in FIGS. 62 and 63, grooves 869 are formed. The method of forming the grooves 869 is the same as the side exposure step according to the first embodiment. That is, half-cut dicing by blade dicing is performed to form grooves 869 . Groove 869 includes a bottom 869a and walls 869b, as shown in FIG. The bottom 869a is flat. The bottom portion 869a reaches the third conductive portion 825 in the thickness direction z, as shown in FIG. The wall portion 869b is substantially parallel to the thickness direction z and connects to the bottom portion 869a. Through the step of forming the groove 869 (groove forming step), the second side surface 824d of the second conductive portion 824 is exposed to the outside. In this embodiment, after the groove 869 is formed, the side surface (side surface 813c) of the projecting portion 814b of the substrate 813 is covered with the insulating layer 815, the resin layer 851, and the sealing resin 860. However, the width of the groove 869 is By adjusting, the side surface 813 c may be exposed from the sealing resin 860 , further exposed from the resin layer 851 , or further exposed from the insulating layer 815 .

Next, as shown in FIG. 64, a second electrode 830 is formed. A method of forming the second electrode 830 is the same as the second electrode forming process according to the first embodiment. That is, the second electrode 830 is formed by sequentially depositing a Ni layer, a Pd layer, and an Au layer by electroless plating. The second electrode 830 includes a first covering portion 835, a second covering portion 836 and a third covering portion 837, as shown in FIG. The first covering portion 835 covers the rear surface 824 b of the second conductive portion 824 . The second covering portion 836 covers the surfaces of the second conductive portion 824 and the third conductive portion 825 exposed at the wall portion 869 b of the groove 869 . The third covering portion 837 covers the surface of the third conductive portion 825 exposed at the bottom 869 a of the groove 869 . A first covering portion 835, a second covering portion 836 and a third covering portion 837 correspond to the first covering portion 35, the second covering portion 36 and the third covering portion 37 of the semiconductor device A50, respectively.

Next, as in the first embodiment, the sealing resin 860 is cut (a cutting step is performed) to separate the semiconductor elements 841 into individual pieces. Each divided piece becomes the semiconductor device A50. A method of cutting the sealing resin 860 is the same as the cutting process of the first embodiment. In the cutting step, the sealing resin 860 and the third conductive portion 825 are cut so as to pass through the widthwise center of the groove 869 . As a result, the shapes of the sealing resin 860 and the third conductive portion 825 become the shapes of the sealing resin 60 and the third conductive portion 25 shown in FIGS. 42 to 47, respectively. In this embodiment, since the bottom 869a of the groove 869 is flat, the second surface 632b of each recess 632 and the third surface 253 of each third conductive portion 25 are flat. Through the above steps, the semiconductor device A50 is manufactured.

Next, the effects of the semiconductor device A50 and its manufacturing method will be described.

The semiconductor device A50 includes the first electrode 20 formed by electrolytic plating and the second electrode 30 formed by electroless plating. Therefore, the semiconductor device A50 is wired by plating and does not use a lead frame formed of a metal plate. Plating wiring can also be made thinner when a leadframe structure is employed. Therefore, the thickness of the semiconductor device A50 can be reduced.

According to the semiconductor device A50, the second electrode 30 is formed on part of the surface of the first electrode 20 by electroless plating. As shown in the first embodiment, deposition of a metal layer by electroless plating is possible even on the surface of silicon, but metal (eg, Cu) is easier. In this embodiment, the material of the first electrode 20 is mainly Cu. Therefore, according to the semiconductor device A50, formation of the second electrode 30 becomes easier than in the semiconductor device A10.

According to the semiconductor device A50, the second electrode 30 includes a first covering portion 35, a second covering portion 36, and a third covering portion 37, all of which are shown in FIGS. , overlaps the sealing resin 60 in plan view. That is, they do not protrude outside the sealing resin 60 in plan view. By adopting such a configuration, a leadless package type semiconductor device A50 can be realized. In particular, the semiconductor device A50 has the second electrode 30 formed on each resin side surface 63 . Therefore, the semiconductor device A50 can have a QFN package structure.

According to the semiconductor device A50, the second electrode 30 includes the second covering portion . The second covering portion 36 is exposed from the resin side surface 63 of the sealing resin 60 . When the semiconductor device A50 is mounted on a circuit board or the like using solder, a fillet can be formed so that the solder covers the second covering portion 36 . Therefore, by adopting such a configuration, the connection state of the solder can be visually confirmed from the side surface of the semiconductor device A50.

According to the semiconductor device A50, the first electrode 20 includes the third conductive portion 25 projecting upward from the second conductive portion 24 in the thickness direction z. The second electrode 30 includes a second covering portion 36 that covers the first surface 251 of the third conductive portion 25 . According to this configuration, the semiconductor device A50 can have a larger dimension in the thickness direction z of the second electrode 30 than the semiconductor device A10. Therefore, confirmation of the connection state of the solder becomes easier. Further, since the contact area between the second electrode 30 and the solder is increased, the bonding strength of the semiconductor device A50 by solder can be made higher than that of the semiconductor device A10.

In the fifth embodiment, the bottom portion 869a of the groove 869 reaches the third conductive portion 825 in the thickness direction z in the groove forming step, but the present invention is not limited to this. For example, the groove forming step may be performed so that the groove 869 penetrates the third conductive portion 825 and the bottom portion 869a reaches the sealing resin 860 above the third conductive portion 825 in the thickness direction z. In this case, the semiconductor device shown in FIG. 65 is formed. 65, the third conductive portion 25 does not have the second surface 252 and the third surface 253, and the first surface 251 is connected to the fourth surface 254. In the embodiment shown in FIG.

[Sixth embodiment]
FIG. 66 shows a semiconductor device according to the sixth embodiment of the present disclosure. FIG. 66 is a cross-sectional view showing the semiconductor device A60 of the sixth embodiment, corresponding to the cross-section shown in FIG. The semiconductor device A60 differs from the semiconductor device A50 in the shape of the third conductive portion 25 of the first electrode 20 and the shape of the recess 632 formed in each resin side surface 63 of the sealing resin 60 .

The recess 632 of the semiconductor device A60 is configured similarly to the recess 632 of the semiconductor device A40. In other words, the concave portion 632 of the semiconductor device A60 has a curved second surface 632b as shown in FIG.

In the third conductive portion 25 of the semiconductor device A60, the third surface 253 is curved. Also, the second boundary edge 25b is located above the first boundary edge 25a in the thickness direction z. Therefore, the second boundary edge 25b is closer to the resin main surface 61 in the thickness direction z than the first boundary edge 25a. Since the third surface 253 is curved, the third covering portion 37 covering the third surface 253 is curved along the third surface 253 as shown in FIG. When viewed in either the first direction x or the second direction, the third surface 253 and the second surface 632b overlap.

According to the semiconductor device A60, the same effects as those of the semiconductor device A50 can be obtained.

[Seventh embodiment]
FIG. 67 shows a semiconductor device according to the seventh embodiment of the present disclosure. FIG. 67 is a cross-sectional view showing a semiconductor device A70 according to the seventh embodiment, corresponding to the cross-section shown in FIG. The semiconductor device A70 differs from the semiconductor device A60 in that it further includes a heat dissipation layer 70 . The heat dissipation layer 70 of the semiconductor device A70 is configured similarly to the heat dissipation layer 70 of the semiconductor device A20. In the embodiment shown in FIG. 67, both the third surface 253 of the third conductive portion 25 (first electrode 20) and the second surface 632b of each recess 632 are curved surfaces. There may be.

In the semiconductor device A70, the support portion 131 of the substrate 13 is formed with a through hole 133 extending from the main surface 131a to the back surface 131b in the thickness direction z. The through hole 133 has, for example, a rectangular shape in plan view. The through hole 133 is filled with the heat dissipation layer 70 . An insulating layer 15 is formed on the surface of the through hole 133 . Therefore, the insulating layer 15 is interposed between the substrate 13 and the heat dissipation layer 70 . An internal resin layer 51 may be further arranged between the substrate 13 and the heat dissipation layer 70 .

Since the semiconductor device A70 is provided with the heat dissipation layer 70, the second electrode 30 includes the heat dissipation layer back surface covering portion 34, as in the second embodiment. The heat dissipation layer rear surface covering portion 34 is separated from the first covering portion 35 , the second covering portion 36 and the third covering portion 37 .

A semiconductor device A70 shown in FIG. 67 can be formed by forming recesses 802 in the recess formation step as in the second embodiment.

The semiconductor device A70 can provide the same effects as the semiconductor device A50. Furthermore, according to the semiconductor device A70, since the heat dissipation layer 70 is provided, heat dissipation can be improved as in the second embodiment.

In the first to seventh embodiments, the semiconductor devices A10, A20, A30, A40, A50, A60, and A70 are of the QFN package type. good too. For example, by configuring the semiconductor device A10 so as not to include a plurality of substrates 12b, a SON package type semiconductor device can be realized.

The semiconductor device and manufacturing method thereof according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific technique of each step of the method for manufacturing the semiconductor device according to the present disclosure can be changed in design in various ways.

A semiconductor device and a method for manufacturing the same according to the present disclosure include embodiments related to the following notes.
[Appendix 1]
a semiconductor element;
a first substrate having a first main surface and a first back surface facing opposite sides in a thickness direction, and having the semiconductor element mounted on the first main surface;
a first conductive portion formed on a portion of the first main surface; and a second conductive portion connected to the first conductive portion and overlapping the first substrate when viewed in a first direction orthogonal to the thickness direction. a first electrode including a conductive portion;
a sealing resin covering the semiconductor element;
a second electrode exposed from the sealing resin and electrically connected to the first electrode;
and
The semiconductor device, wherein the second electrode is in contact with the second conductive portion.
[Appendix 2]
further comprising a second substrate spaced apart from the first substrate and overlapping the first substrate when viewed in the first direction;
The second conductive portion is interposed between the first substrate and the second substrate,
The semiconductor device according to appendix 1, wherein the second electrode is further in contact with the second substrate.
[Appendix 3]
The second substrate has a second main surface facing in the same direction as the first main surface and a second back surface facing in the same direction as the first back surface,
The semiconductor device according to appendix 2, wherein the second electrode includes a second back surface covering portion covering the second back surface.
[Appendix 4]
The second conductive portion has a second conductive portion back surface that is flush with the second back surface,
3. The semiconductor device according to appendix 3, wherein the second electrode includes a first electrode covering portion connected to the second back surface covering portion and covering the back surface of the second conductive portion.
[Appendix 5]
The second substrate further has an exposed side surface exposed from the sealing resin and sandwiched between the second main surface and the second back surface in the thickness direction,
5. The semiconductor device according to claim 4, wherein the second electrode further includes an exposed side surface covering portion connected to the second back surface covering portion and covering the exposed side surface.
[Appendix 6]
6. The semiconductor device according to appendix 5, wherein the exposed side covering portion overlaps the sealing resin when viewed in the thickness direction.
[Appendix 7]
7. The semiconductor device according to any one of appendices 2 to 6, wherein the first substrate and the second substrate are made of the same material.
[Appendix 8]
8. The semiconductor device according to appendix 7, wherein the material is silicon.
[Appendix 9]
a third substrate separated from the first substrate and the second substrate when viewed in the thickness direction;
a third electrode exposed from the sealing resin and in contact with the third substrate;
9. The fourth electrode according to any one of appendices 2 to 8, further comprising a fourth electrode electrically connected to the third electrode and the semiconductor element and partially interposed between the first substrate and the third substrate. semiconductor device.
[Appendix 10]
The third substrate overlaps the first substrate when viewed in the first direction, and overlaps the second substrate when viewed in a second direction orthogonal to both the first direction and the thickness direction. cage,
The semiconductor device according to appendix 9, wherein part of the sealing resin is interposed between the second substrate and the third substrate.
[Appendix 11]
the third substrate overlaps the first substrate and the second substrate when viewed in the first direction;
11. The semiconductor device according to claim 10, wherein the second substrate and the third substrate are arranged on opposite sides of each other with the first substrate interposed therebetween when viewed in the thickness direction.
[Appendix 12]
The first electrode further includes a third conductive portion connected to the second conductive portion and protruding from the second conductive portion in a direction in which the first main surface faces,
The semiconductor device according to appendix 1, wherein the second electrode is further in contact with the third conductive portion.
[Appendix 13]
The second conductive portion has a second conductive portion back surface that is flush with the first back surface,
13. The semiconductor device according to appendix 12, wherein the second electrode includes a first covering portion that covers the back surface of the second conductive portion.
[Appendix 14]
The second conductive portion is connected to the back surface of the second conductive portion, connected to a first side surface facing the first substrate, and to the back surface of the second conductive portion, and is connected to the first side surface in the first direction. having a second side facing away from the side,
14. The semiconductor device according to appendix 13, wherein the second electrode further includes a second covering portion connected to the first covering portion and covering the second side surface.
[Appendix 15]
The third conductive portion has a first surface that is flush with the second side surface,
15. The semiconductor device according to appendix 14, wherein the second cover further covers the first surface.
[Appendix 16]
The third conductive portion has a second surface that faces the same direction as the first surface in the first direction and is located outside the first surface when viewed in the thickness direction; further comprising a third surface connected to the first surface and the second surface;
16. The semiconductor device according to appendix 15, wherein the second electrode further includes a third covering portion connected to the second covering portion and covering the third surface.
[Appendix 17]
The sealing resin has a resin side surface facing the same direction as the first surface in the first direction,
17. The semiconductor device according to appendix 16, wherein the resin side surface has a flat portion that is flush with the second surface.
[Appendix 18]
The third conductive portion has a first boundary edge between the first surface and the third surface and a second boundary edge between the second surface and the third surface,
the third surface is a curved surface,
18. The semiconductor device according to appendix 16 or 17, wherein the second boundary edge is located in the direction in which the first main surface faces the first boundary edge in the thickness direction.
[Appendix 19]
19. The semiconductor device according to any one of Appendices 1 to 18, wherein the second electrode is composed of a Ni layer, a Pd layer, and an Au layer that are laminated to each other.
[Appendix 20]
19. The semiconductor device according to any one of Appendixes 1 to 19, wherein the first electrode is made of a metal containing Cu.
[Appendix 21]
21. The semiconductor device according to any one of appendices 1 to 20, further comprising a bonding layer electrically connecting the first conductive portion and the semiconductor element.
[Appendix 22]
22. The semiconductor device according to any one of appendices 1 to 21, further comprising an external resin layer made of an insulator and covering at least the first rear surface.
[Appendix 23]
23. The semiconductor device according to appendix 22, wherein the external resin layer is made of epoxy or polyimide.
[Appendix 24]
24. The semiconductor device according to any one of Appendixes 1 to 23, further comprising an internal resin layer that insulates the first substrate and the first electrode.
[Appendix 25]
25. The semiconductor device according to appendix 24, wherein the internal resin layer is made of polyimide.
[Appendix 26]
26. The semiconductor device according to any one of appendices 1 to 25, further comprising a heat dissipation layer overlapping the semiconductor element when viewed in the thickness direction.
[Appendix 27]
the first substrate has a through hole extending from the first main surface to the first back surface in the thickness direction;
27. The semiconductor device according to appendix 26, wherein the heat dissipation layer is filled in the through hole.
[Appendix 28]
The heat dissipation layer has a heat dissipation layer back surface that is flush with the first back surface,
28. The semiconductor device according to appendix 27, wherein the second electrode includes a heat-dissipating layer back surface covering portion that covers the back surface of the heat-dissipating layer.
[Appendix 29]
a substrate preparation step of preparing a substrate having a main surface and a back surface facing opposite to each other in the thickness direction;
a recess forming step of forming recesses recessed from the main surface toward the back surface in the base material;
a first electrode forming step of forming a first electrode including a first conductive portion covering a portion of the main surface and a second conductive portion accommodated in the recess;
a semiconductor element mounting step of mounting a semiconductor element electrically connected to the first electrode;
a sealing resin forming step of forming a sealing resin covering the semiconductor element;
A grinding step of grinding the base material from the back surface to the main surface side in the thickness direction to expose the second conductive portion;
a second electrode forming step of forming a second electrode in contact with the exposed second conductive portion;
A method of manufacturing a semiconductor device, comprising:
[Appendix 30]
By the grinding step, the substrate is divided into a first substrate on which the semiconductor element is mounted and a second substrate separated from the first substrate,
29. The method of manufacturing a semiconductor device according to appendix 29, wherein in the step of forming the second electrode, the second electrode is further formed so as to be in contact with the second substrate.
[Appendix 31]
Further forming a third conductive portion projecting in the thickness direction from the second conductive portion in the first electrode forming step,
29. The method of manufacturing a semiconductor device according to appendix 29, wherein the second electrode is further in contact with the third conductive portion.

A10, A20, A30, A40, A50, A60, A70: semiconductor device 11: substrate 111: first main surface 112: first rear surface 113: first side surface 114: through holes 12, 12a, 12b: substrate 121: second Main surface 122: Second back surface 123: Second side surface 123a: Exposed side surface 13: Substrate 13a: Main surface 13b: Back surface 131: Support portion 131a: Main surface 131b: Back surface 131c: Side surface 132: Protruding portion 132a: Main surface 132b: Back surface 132 c : Side surface 133 : Through hole 15 : Insulating layer 20 : First electrode 21 : First conductive part 22 : Second conductive part 221 : Connection surface 23 : First conductive part 24 : Second conductive part 241 : Main surface 242 : Back surface 243 : First side surface 244 : Second side surface 25 : Third conductive part 251 : First surface 252 : Second surface 253 : Third surface 254 : Fourth surface 255 : Fifth surface 25a : First boundary edge 25b : Second boundary edge 30 : Second electrode 31 : First electrode covering portion 32 : Second back covering portion 33 : Exposed side covering portion 34 : Heat dissipation layer back covering portion 35 : First covering portion 36 : Second covering portion 37 : Third covering portion 41 : Semiconductor element 411 : Element main surface 412 : Element back surface 413 : Electrode pad 42 : Bonding layer 51 : Internal resin layer 511 : First part 512 : Second part 512a : Through hole 52 : External resin layer 60 : sealing resin 61 : resin main surface 62 : resin back surface 63 : resin side surface 631 : flat portion 632 : concave portion 632a : first surface 632b : second surfaces 632c, 632d: boundary edge 70 : heat dissipation layer 72 : heat dissipation layer back surface 80: base material 801, 802, 803: concave portion 801a, 802a, 803a: bottom surface 801b, 802b, 803b: standing surface 810: base material 810a: main surface 810b: back surface 811: substrate 811a: first main surface 812: substrate 812a : Second major surface 812b : Second back surface 812c : Second side surface 813 : Substrate 813b : Back surface 813c : Side surface 814a : Supporting portion 814b : Protruding portion 815 : Insulating layer 820 : First electrode 820a : Base layers 820b, 820c, 820d : Plated layer 821 : First conductive portion 822 : Second conductive portion 822a : Exposed surface 823 : First conductive portion 824 : Second conductive portion 824a : Main surface 824b : Back surface 824d : Second side surface 825 : Third conductive portion 830 : Second electrode 831 : First electrode covering portion 832 : Second back covering portion 833 : Exposed side covering portion 834 : Heat dissipation layer back covering portion 841 : Semiconductor element 841a : Element main surface 842 : Bonding layer 851 : Resin layer 851a : First part 851b : Second part 851d : Through hole 852 : Resin layer 852b : Second part 860 : Sealing resin 869 : Groove 869a : Bottom 869b : Wall 870 : Heat dissipation layer 872 : Back of heat dissipation layer

Claims (25)

a semiconductor element;
a first substrate having a first main surface and a first back surface facing opposite sides in a thickness direction, and having the semiconductor element mounted on the first main surface;
a first conductive portion formed on a portion of the first main surface; and a second conductive portion connected to the first conductive portion and overlapping the first substrate when viewed in a first direction orthogonal to the thickness direction. a first electrode including a conductive portion;
a sealing resin covering the semiconductor element;
a second electrode exposed from the sealing resin and electrically connected to the first electrode;
a second substrate separated from the first substrate and overlapping the first substrate when viewed in the first direction;
and
The second electrode is in contact with the second conductive portion,
The second conductive portion is interposed between the first substrate and the second substrate,
the second electrode is further in contact with the second substrate;
A semiconductor device characterized by: The second substrate has a second main surface facing in the same direction as the first main surface and a second back surface facing in the same direction as the first back surface,
The second electrode includes a second back surface covering portion covering the second back surface,
A semiconductor device according to claim 1 . The second conductive portion has a second conductive portion back surface that is flush with the second back surface,
The second electrode includes a first electrode covering portion connected to the second back surface covering portion and covering the back surface of the second conductive portion,
3. The semiconductor device according to claim 2 . The second substrate further has an exposed side surface exposed from the sealing resin and sandwiched between the second main surface and the second back surface in the thickness direction,
The second electrode further includes an exposed side covering portion that connects to the second backside covering portion and covers the exposed side surface.
4. The semiconductor device according to claim 3 . The exposed side surface covering portion overlaps the sealing resin when viewed in the thickness direction,
5. The semiconductor device according to claim 4 . The first substrate and the second substrate are made of the same material,
6. The semiconductor device according to claim 1 . The material is silicon,
7. The semiconductor device according to claim 6 . a third substrate separated from the first substrate and the second substrate when viewed in the thickness direction;
a third electrode exposed from the sealing resin and in contact with the third substrate;
a fourth electrode electrically connected to the third electrode and the semiconductor element and partly interposed between the first substrate and the third substrate;
further comprising
8. The semiconductor device according to claim 1 . The third substrate overlaps the first substrate when viewed in the first direction, and overlaps the second substrate when viewed in a second direction orthogonal to both the first direction and the thickness direction. cage,
Part of the sealing resin is interposed between the second substrate and the third substrate,
9. The semiconductor device according to claim 8 . the third substrate overlaps the first substrate and the second substrate when viewed in the first direction;
The second substrate and the third substrate are arranged on opposite sides of each other with the first substrate interposed therebetween when viewed in the thickness direction.
10. The semiconductor device according to claim 9 . a semiconductor element;
a first substrate having a first main surface and a first back surface facing opposite sides in a thickness direction, and having the semiconductor element mounted on the first main surface;
a first conductive portion formed on a portion of the first main surface; and a second conductive portion connected to the first conductive portion and overlapping the first substrate when viewed in a first direction orthogonal to the thickness direction. a first electrode including a conductive portion;
a sealing resin covering the semiconductor element;
a second electrode exposed from the sealing resin and electrically connected to the first electrode;
and
The second electrode is in contact with the second conductive portion,
The first electrode further includes a third conductive portion connected to the second conductive portion and protruding from the second conductive portion in a direction in which the first main surface faces,
The second electrode is further in contact with the third conductive portion,
The second conductive portion includes a second conductive portion back surface flush with the first back surface, a first side surface connected to the second conductive portion back surface and facing the first substrate, and the second conductive portion. a second side surface connected to the back surface of the part and facing the opposite side to the first side surface in the first direction;
The second electrode includes a first covering portion that covers the back surface of the second conductive portion, and a second covering portion that is connected to the first covering portion and covers the second side surface,
The third conductive portion has a first surface that is flush with the second side surface,
The second covering part further covers the first surface,
The third conductive portion has a second surface that faces the same direction as the first surface in the first direction and is located outside the first surface when viewed in the thickness direction; further comprising a third surface connected to the first surface and the second surface;
The second electrode further includes a third covering portion connected to the second covering portion and covering the third surface ,
semiconductor device. The sealing resin has a resin side surface facing the same direction as the first surface in the first direction,
The resin side surface has a flat portion that is flush with the second surface,
12. The semiconductor device according to claim 11 . The third conductive portion has a first boundary edge between the first surface and the third surface and a second boundary edge between the second surface and the third surface,
the third surface is a curved surface,
The second boundary edge is located in the direction in which the first main surface faces, relative to the first boundary edge, in the thickness direction.
13. The semiconductor device according to claim 11 or 12 . 14. The semiconductor device according to claim 1, wherein said second electrode is composed of a Ni layer, a Pd layer, and an Au layer which are laminated to each other. The first electrode is composed of a metal containing Cu,
15. The semiconductor device according to claim 1. further comprising a bonding layer that electrically connects the first conductive portion and the semiconductor element,
16. The semiconductor device according to claim 1. Covering at least the first back surface and further comprising an external resin layer made of an insulator,
17. The semiconductor device according to claim 1. The external resin layer is made of epoxy or polyimide,
18. The semiconductor device according to claim 17 . further comprising an internal resin layer that insulates the first substrate and the first electrode,
19. The semiconductor device according to claim 1. The internal resin layer is made of polyimide,
20. The semiconductor device according to claim 19 . Further comprising a heat dissipation layer overlapping the semiconductor element when viewed in the thickness direction,
21. The semiconductor device according to claim 1. the first substrate has a through hole extending from the first main surface to the first back surface in the thickness direction;
The heat dissipation layer is filled in the through holes,
22. The semiconductor device according to claim 21 . The heat dissipation layer has a heat dissipation layer back surface that is flush with the first back surface,
The second electrode includes a heat dissipation layer back surface covering portion covering the back surface of the heat dissipation layer,
23. The semiconductor device according to claim 22 . a substrate preparation step of preparing a substrate having a main surface and a back surface facing opposite to each other in the thickness direction;
a recess forming step of forming recesses recessed from the main surface toward the back surface in the base material;
a first electrode forming step of forming a first electrode including a first conductive portion covering a portion of the main surface and a second conductive portion accommodated in the recess;
a semiconductor element mounting step of mounting a semiconductor element electrically connected to the first electrode;
a sealing resin forming step of forming a sealing resin covering the semiconductor element;
A grinding step of grinding the base material from the back surface to the main surface side in the thickness direction to expose the second conductive portion;
a second electrode forming step of forming a second electrode in contact with the exposed second conductive portion;
has
By the grinding step, the substrate is divided into a first substrate on which the semiconductor element is mounted and a second substrate separated from the first substrate,
In the second electrode forming step, the second electrode is further brought into contact with the second substrate.
Form,
A method of manufacturing a semiconductor device, characterized by: a substrate preparation step of preparing a substrate having a main surface and a back surface facing opposite to each other in the thickness direction;
a recess forming step of forming recesses recessed from the main surface toward the back surface in the base material;
a first electrode forming step of forming a first electrode including a first conductive portion covering a portion of the main surface and a second conductive portion accommodated in the recess;
a semiconductor element mounting step of mounting a semiconductor element electrically connected to the first electrode;
a sealing resin forming step of forming a sealing resin covering the semiconductor element;
A grinding step of grinding the base material from the back surface to the main surface side in the thickness direction to expose the second conductive portion;
a second electrode forming step of forming a second electrode in contact with the exposed second conductive portion;
has
A first substrate is formed from the base material by the grinding step,
the first substrate has a first main surface and a first back surface facing opposite sides in the thickness direction, and the semiconductor element is mounted on the first main surface;
the second conductive portion overlaps the first substrate when viewed in a first direction orthogonal to the thickness direction;
In the step of forming the first electrode, a third conductive portion protruding from the second conductive portion in the thickness direction is further formed on the first electrode ,
The second electrode is further in contact with the third conductive portion,
The second conductive portion includes a second conductive portion back surface flush with the first back surface, a first side surface connected to the second conductive portion back surface and facing the first substrate, and the second conductive portion. It has a second side surface connected to the back surface of the part and facing the opposite side to the first side surface in the first direction,
In the second electrode forming step, the second electrode is formed with a first covering portion covering the back surface of the second conductive portion and a second covering portion connected to the first covering portion and covering the second side surface. death,
The third conductive part has a first surface that is flush with the second side surface, faces in the same direction as the first surface in the first direction, and is arranged from the first surface when viewed in the thickness direction. a second surface positioned outward from the second surface; and a third surface connecting the first surface and the second surface;
The second covering part further covers the first surface,
In the step of forming the second electrode, a third covering portion connected to the second covering portion and covering the third surface is further formed on the second electrode,
A method of manufacturing a semiconductor device.

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