TWI804195B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a substrate structure, a chip and a reinforcing layer. The substrate structure includes a core layer, a patterned circuit layer disposed on the core layer and a solder resist layer. The solder resist layer is disposed on the patterned circuit layer and exposes at least a part of the patterned circuit layer. The chip is disposed on a chip disposing region of the substrate structure and electrically connected the patterned circuit layer. The reinforcing layer is disposed on the solder resist layer, extended through the solder resist layer and stops at the core layer. The reinforcing layer covers a peripheral region of the chip disposing region. The molding compound at least encapsulates the chip, at least a part of the substrate structure and the reinforcing layer.

Description

Semiconductor package structure and manufacturing method thereof

The present disclosure relates to a semiconductor package structure and a manufacturing method of the semiconductor package structure.

Integrated circuits are usually formed on a substrate, such as a semiconductor wafer. After the wafer is singulated, conductive terminals need to be used to conduct signals to an external carrier (such as a substrate) for subsequent use in end products. Commonly used conductive terminal connection methods mostly use bonding bumps or wire bonding as the medium of electrical conduction. However, since the chip and the external carrier (such as the substrate) are composed of different materials, they have different coefficients of thermal expansion (CTE). Therefore, the package body is likely to become more fragile due to the mismatch of the thermal expansion coefficients, causing the external carrier (such as the substrate) to break. Line and/or film layer separation (delamination) and other issues.

The disclosure provides a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure, which can improve the structural strength of the semiconductor packaging, thereby reducing problems such as disconnection and delamination in high-stress regions in the semiconductor packaging structure.

A semiconductor packaging structure disclosed in the present disclosure includes a substrate structure, a chip and a strengthening layer. The substrate structure includes a core layer, a patterned circuit layer disposed on the core layer, and a solder resist layer, wherein the solder resist layer is disposed on the patterned circuit layer and exposes at least part of the patterned circuit layer. The wafer is disposed on the wafer disposition area of the substrate structure, and is electrically connected to the patterned circuit layer. The strengthening layer is arranged on the solder resist layer, extends through the solder resist layer and abuts against the core layer, and the strengthening layer covers the peripheral area of the chip setting area. The encapsulant at least covers the chip, at least part of the substrate structure and the strengthening layer.

A manufacturing method of a semiconductor package structure disclosed in the present disclosure includes the following steps: providing a substrate structure having a chip setting area, wherein the substrate structure includes a core layer, a patterned circuit layer disposed on the core layer, and a patterned circuit layer disposed on the core layer. A solder resist layer on the patterned circuit layer, wherein the solder resist layer includes a plurality of through holes located in a peripheral region of the chip installation area; a patterned photoresist layer is formed on the solder resist layer, wherein the pattern The patterned photoresist layer at least exposes the plurality of through holes and the peripheral region; using the patterned photoresist layer as a mask, an electroplating process is performed to form a strengthening layer, wherein the strengthening layer fills the plurality of through holes and covers the and removing the patterned photoresist layer and exposing the strengthening layer; disposing a chip on a chip setting area of the substrate structure, wherein the chip is electrically connected to the patterned circuit layer, and a chip of the chip is The edge portion at least partially overlaps with the strengthening layer in the direction of the orthographic projection; forming a colloid to cover the chip, the patterned circuit layer and at least part of the substrate structure.

Based on the above, in the semiconductor package structure of the present disclosure, a reinforcement layer covering at least the peripheral area of the chip installation area is formed on the solder resist layer to strengthen the structural strength of the peripheral area of the chip installation area, thereby reducing the thermal expansion coefficient mismatch. The adverse effects caused by thermal stress, such as cracking of the chip, disconnection of the circuit layer on the substrate structure under the chip, or delamination of the substrate structure, etc. Therefore, the semiconductor packaging structure disclosed in this disclosure can effectively improve the semiconductor packaging structure. production yield and product reliability.

The aforementioned and other technical contents, features and effects of the present disclosure will be clearly presented in the following detailed descriptions of the embodiments with reference to the drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the attached drawings. Accordingly, the directional terms used are for illustration, not for limitation of the present disclosure. Also, in the following embodiments, the same or similar components will be given the same or similar symbols.

1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. In some embodiments, the manufacturing process of the semiconductor package structure may include the following steps. Referring first to FIG. 1 , a substrate structure 110 as shown in FIG. 1 is provided, wherein the substrate structure 110 has a wafer placement region R1 for disposing a wafer (such as the wafer 120 shown in FIG. 6 ) on the wafer placement region R1 . In one embodiment, the substrate structure 110 includes a core layer 112 , a patterned circuit layer 114 disposed on the core layer 112 , and a solder resist layer 116 disposed on the patterned circuit layer 114 . In this embodiment, the chip can be disposed on the substrate structure 110, for example, by wire bonding. Accordingly, the patterned circuit layer 114 further includes a plurality of pads (also called wire bonding pads) 1141, which can surround It is arranged around the chip arrangement region R1 and electrically connected to other circuit contacts.

Referring to FIG. 1 , in some embodiments, the solder resist layer 116 may cover at least part of the patterned circuit layer 114 and expose at least part of the pad portion 1141 . In this embodiment, the pad portion 1141 is exposed by a plurality of openings 1164 defined by the solder resist layer 116 for subsequent electrical connection. Specifically, the patterned wiring layer 114 may include a plurality of pads 1141 and a plurality of wirings 1142 electrically connected to the pads 1141, wherein the solder resist layer 116 covers the wirings 1142 and exposes at least part of the wirings. Pad 1141 . In some embodiments, the solder resist layer 116 may further include a plurality of through holes 1163 located in the peripheral area of the chip placement region R1. In this embodiment, the through holes 1163 respectively extend through the solder resist layer 116 and abut against the core layer 112 . Moreover, the through hole 1163 and the patterned circuit layer 114 are isolated and insulated from each other by the solder resist layer 116 . In this embodiment, the plurality of openings 1164 and the plurality of through holes 1163 in the solder resist layer 116 for exposing the pads 1141 can be formed in the same patterning process. Here, it is worth noting that the other surface of the substrate 110 has a plurality of pads that can be electrically connected to the external, and appropriate external terminals can be connected according to actual needs. In this disclosure, the external terminals are, for example, solder balls. (I won't go into details about its subsequent application here).

Next, referring to FIG. 2 , a patterned photoresist layer 170 is formed on the solder resist layer 116 , wherein the patterned photoresist layer 170 includes a plurality of photoresist openings 172 at least exposing a plurality of through holes 1163 . Specifically, a photoresist layer can be formed on the structure in FIG. 1 by spin on coating, and then patterned by processes such as exposure and development to form The photoresist layer 170 is patterned as shown in FIG. 2 . Next, the patterned photoresist layer 170 is used as a mask to form the penetrating portion 132 in the strengthening layer (such as the strengthening layer 130 shown in FIG. 4 ). In this embodiment, the material of the penetrating portion 132 includes copper, aluminum, tin , silver or its alloy and other metal materials are formed in the photoresist opening 172 and the through hole 1163 through, for example, an electroplating process, so as to fill the photoresist opening 172 and the through hole 1163 . In this embodiment, the through portion 132 can be formed through two electroplating processes. For example, after forming the through hole 1163 of the solder resist layer 116, the first electroplating process can be performed to fill the through hole 1163, and then, after forming the photoresist opening 172 of the patterned photoresist layer 170, then A second electroplating process is performed to continue filling the photoresist opening 172 . Of course, in other embodiments, after forming the patterned photoresist layer 170 , the penetrating portion 132 can directly fill the photoresist opening 172 and the through hole 1163 with one electroplating process, and the present disclosure is not limited thereto.

Next, please refer to FIG. 3 and FIG. 4, as shown in FIG. Layer 170 exposes the peripheral area. And, for example, an electroplating process is performed to form the strengthening layer 130 covering the peripheral region and connecting the through portion 132 . In this embodiment, the reinforcing layer 130 includes the through portion 132 filling the through hole 1163 and covers the peripheral region of the solder resist layer 116 in the chip placement region R1 . In an alternative embodiment, the strengthening layer 130 may also be electroplated once in the step of FIG. 3 to form the strengthening layer 130 including the through portion 132 , and the present disclosure is not limited thereto. It should be noted that the fabrication flow charts in Figures 1 to 6 are cross-sectional views taken along the peripheral area surrounding the wafer installation region R1 (for example, the peripheral area P1 shown in Figure 7). Therefore, the reinforcement in Figure 4 The layer 130 is shown as extending to cover the entire die placement region R1 , but actually, the strengthening layer 130 may only cover the peripheral area of the die placement region R1 as shown in FIG. 7 . Next, referring to FIG. 5 , the patterned photoresist layer 170 is removed to expose the strengthening layer 130 and the pad portion 1141 . A method of removing the patterned photoresist layer 170 is, for example, using an organic solvent to remove the patterned photoresist layer 170 .

FIG. 7 is a schematic top view of a semiconductor package structure according to an embodiment of the disclosure. It should be noted that at least some components of the semiconductor package structure in the top views of the present disclosure (such as FIGS. 7 to 10 ) are shown in a perspective manner to clearly present the configuration relationship of the components. Please refer to FIG. 6 and FIG. 7, and then, the wafer 120 is set on the wafer installation region R1 of the substrate structure 110, wherein the wafer 120 is electrically connected to the patterned circuit layer 114, and the edge portion of the wafer 120 (corresponding to the peripheral area P1 ) at least partially overlaps with the reinforcement layer 130 in the orthographic projection direction. In other words, viewed from the direction of the top view, the edge portion of the wafer 120 (corresponding to the peripheral region P1 ) at least partially overlaps with the reinforcement layer 130 . In this embodiment, the chip 120 is bonded to the substrate structure 110 by, for example, wire bonding. For example, the chip 120 may have a plurality of I/O pads 121 , which may be arranged at each edge of the chip 120 , for example. The input/output pads 121 can be respectively electrically connected to the pad portions 1141 of the substrate structure 110 through a plurality of bonding wires 160 , so that the chip 120 can be electrically connected to the patterned circuit layer 114 . Next, an encapsulant 150 is formed to cover the chip 120 , the patterned circuit layer 114 and at least part of the substrate structure 110 .

Generally speaking, when manufacturing a semiconductor package structure, due to the difference in the coefficient of thermal expansion (coefficient of thermal expansion, CTE) mismatch between different component materials, thermal stress will be generated in the semiconductor package structure, and the edge of the chip (die edge ) has the most severe impact. This kind of thermal stress can easily lead to problems such as cracking of the wafer, disconnection or delamination of the underlying circuit layer. In view of this, in this embodiment, a strengthening layer 130 covering the peripheral region P1 of the chip placement region R1 is formed on the solder resist layer 116 to strengthen the structural strength of the peripheral region of the chip placement region R1, thereby reducing thermal stress. It can improve the production yield and reliability of the semiconductor packaging structure.

In some embodiments, the structural rigidity of the strengthening layer 130 may be greater than that of the solder resist layer 116 to strengthen the protection of the underlying patterned circuit layer 114 . In this embodiment, the strengthening layer 130 may include copper, aluminum or other suitable metal materials, and is formed by electroplating. In other embodiments, the material of the strengthening layer 130 may further include ceramics, silicon nitride or other suitable materials, and may be formed by suitable methods such as deposition, and the present disclosure is not limited thereto. In some embodiments, the strengthening layer 130 overlaps at least the line portion 1142 located below the peripheral region P1 in the direction of the orthographic projection. In other words, viewed from a top view, the reinforcement layer 130 at least partially overlaps the line portion 1142 located below the peripheral region P1. Moreover, the strengthening layer 130 is electrically insulated from the patterned circuit layer 114 .

In some embodiments, as shown in FIG. 7 , in addition to covering the peripheral region P1 of the wafer placement region R1, the strengthening layer 130 can also extend along the same plane to a direction other than the wafer placement region R1, so as to further strengthen the periphery of the wafer 120. Structural strength of the area. That is to say, in the direction of the orthographic projection, in addition to overlapping the peripheral region P1 of the wafer placement region R1 , the strengthening layer 130 can also overlap the peripheral region surrounding the periphery of the wafer placement region R1 . In this embodiment, the strengthening layer 130 may include a plurality of strengthening patterns separated from each other as shown in FIG. ) are respectively disposed on opposite ends of each strengthening pattern to penetrate the solder resist layer 116 . Moreover, the strengthening layer 130 does not overlap with corners of the wafer 120 in the direction of the orthographic projection.

8 to 10 are schematic top views of a semiconductor package structure according to different embodiments of the present disclosure. It must be noted here that the semiconductor package structure 100a, 100b, 100c of this embodiment is similar to the semiconductor package structure 100 of the preceding embodiment, therefore, this embodiment follows the component numbers and part of the content of the previous embodiment, wherein the same numbers are used to represent the same or similar elements, and descriptions of the same technical contents are omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and this embodiment will not be repeated. The differences between the semiconductor package structure 100a, 100b, 100c of this embodiment and the semiconductor package structure 100 of the previous embodiment will be described below.

Referring to FIG. 8 , in this embodiment, the chip 120 is bonded to the substrate structure 110 through flip-chip bonding. The upper surface of the substrate structure 110 is connected to the substrate structure 110 through a plurality of conductive bumps 122 . In this embodiment, the pad portion 1141 in the patterned circuit layer 114 is located in the central area of the chip placement region R1 to connect with the conductive bump 122 on the chip 120, and the circuit portion 1142 is connected to the pad portion 1141 and can extend to A region other than the wafer setting region R1. Under this configuration, the strengthening layer 130 can have a plurality of strengthening patterns separated from each other similar to the configuration of the foregoing embodiments, so as to be respectively disposed on a plurality of sides of the peripheral region P1 of the wafer setting region R1, and the penetrating portion 132 (in the form of Dotted lines) are respectively arranged at opposite ends of each strengthening pattern. Moreover, the strengthening layer 130 overlaps at least the line portion 1142 located below the peripheral region P1 in the direction of the orthographic projection. In other words, viewed from a top view, the reinforcement layer 130 at least partially overlaps the line portion 1142 located below the peripheral region P1. In this embodiment, the strengthening layer 130 does not overlap with multiple corners of the wafer 120 in the orthographic projection direction.

Referring to FIG. 9 , in this embodiment, the reinforcement layer 130b is a ring structure surrounding the peripheral region P1 , that is, the reinforcement layer 130b can completely surround the peripheral region of the wafer placement region R1 . Specifically, in the orthographic projection direction, the strengthening layer 130 b not only overlaps multiple sides of the wafer 120 , but also overlaps multiple corners of the wafer 120 . In this embodiment, the penetrating portion 132 can be configured to penetrate through the opposite ends of each side of the chip installation region R1 of the solder resist layer 116, so as to avoid the main wiring area of the wiring portion 1142 of the patterned wiring layer 114 . In some embodiments, the reinforcement layer 130b may not only cover the peripheral region of the wafer placement region R1, but also extend along the same plane to a direction other than the wafer placement region R1, so as to further strengthen the structural strength of the peripheral region of the wafer 120 . That is to say, in the direction of the orthographic projection, in addition to overlapping with the peripheral region of the wafer placement region R1 , the reinforcement layer 130 b can partially overlap with the peripheral region surrounding the periphery of the wafer placement region R1 .

Referring to FIG. 10 , in this embodiment, the strengthening layer 130 c can completely cover the chip placement region R1 of the solder resist layer 116 . That is to say, in the direction of the orthographic projection, the wafer 120 can be completely located within the setting range of the strengthening layer 130c. In this embodiment, the penetrating portion 132c may be configured to penetrate through each corner of the chip placement region R1 of the solder resist layer 116 to avoid the main wiring area of the wiring portion 1142 of the patterned wiring layer 114 . In some embodiments, the strengthening layer 130 c can not only completely cover the chip setting region R1 , but also extend along the same plane to a direction other than the chip setting region R1 , so as to further strengthen the structural strength of the periphery of the chip 120 . That is to say, in the direction of the orthographic projection, in addition to overlapping with the wafer placement region R1 , the strengthening layer 130c can partially overlap with the peripheral area surrounding the periphery of the wafer placement region R1 .

To sum up, in the semiconductor package structure of the present disclosure, a strengthening layer is formed on the solder resist layer to at least cover the peripheral area of the chip placement area, so as to strengthen the structural strength of the peripheral area of the chip placement area, thereby reducing the thermal expansion coefficient. Adverse effects caused by thermal stress caused by mismatching, such as cracking of the chip, disconnection of the circuit layer under the chip, or delamination of the substrate structure, etc. Therefore, the semiconductor package structure disclosed in this disclosure can effectively improve the production of the semiconductor package structure yield and product reliability.

100, 100a, 100b, 100c: package structure 110: Substrate structure 112: core layer 114: Patterned circuit layer 1141: pad part 1142: Line Department 116: Solder mask 1163: through hole 1164: opening 120: chip 122: Conductive bump 130, 130b, 130c: strengthening layer 132, 132c: penetrating part 150: sealant 160: welding wire 170: Patterned photoresist layer 172: photoresist opening R1: chip setting area P1: Peripheral area

1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. FIG. 7 is a schematic top view of a semiconductor package structure according to an embodiment of the disclosure. 8 to 10 are schematic top views of a semiconductor package structure according to different embodiments of the present disclosure.

100: Package structure

110: Substrate structure

112: core layer

114: Patterned circuit layer

1141: pad part

1142: Line Department

116: Solder mask

1163: through hole

1164: opening

120: chip

130: strengthening layer

132: Penetrating part

150: sealant

160: welding wire

R1: chip setting area

Claims (9)

A semiconductor packaging structure, comprising: a substrate structure, including a core layer, a patterned circuit layer disposed on the core layer, and a solder resist layer, wherein the solder resist layer is disposed on the patterned circuit layer and exposes at least A portion of the patterned circuit layer; a chip disposed on a chip placement area of the substrate structure and electrically connected to the patterned circuit layer; a reinforcement layer disposed on the solder resist layer and extending through the solder resist Layer and butted against the core layer, the strengthening layer covers the peripheral area of the wafer setting area; and a sealant covers at least the wafer, at least part of the substrate structure and the strengthening layer, wherein the strengthening layer Structural rigidity is substantially greater than that of the solder mask. The semiconductor package structure as claimed in claim 1, wherein the reinforcement layer at least partially overlaps an edge of the wafer in an orthographic projection direction. The semiconductor package structure as claimed in claim 1, wherein the strengthening layer is made of copper, aluminum, ceramic or silicon nitride. The semiconductor package structure according to claim 1, wherein the patterned wiring layer includes a plurality of pads and a plurality of wirings electrically connected to the pads, wherein the solder resist layer covers the plurality of wirings and expose the plurality of pads. The semiconductor package structure as claimed in claim 1, wherein the strengthening layer overlaps at least the plurality of circuit portions located below the peripheral region in the direction of the orthographic projection. The semiconductor package structure as claimed in claim 1, wherein the strengthening layer comprises a plurality of strengthening patterns separated from each other, respectively disposed on a plurality of sides of the peripheral region. The semiconductor package structure as claimed in claim 1, wherein the strengthening layer is a ring structure surrounding the peripheral area. The semiconductor package structure as claimed in claim 1, wherein the reinforcement layer completely covers the wafer placement area. A method for manufacturing a semiconductor package structure, comprising: providing a substrate structure having a wafer setting area, wherein the substrate structure includes a core layer, a patterned circuit layer disposed on the core layer, and a patterned circuit layer disposed on the patterned circuit layer A solder resist layer on the solder resist layer, wherein the solder resist layer includes a plurality of through holes located in a peripheral area of the chip installation area; a patterned photoresist layer is formed on the solder resist layer, wherein the patterned photoresist layer At least exposing the plurality of through holes and the peripheral area; using the patterned photoresist layer as a mask, electroplating forms a strengthening layer, wherein the strengthening layer fills the plurality of through holes and covers the peripheral area; removes the patterned The photoresist layer exposes the strengthening layer; a chip is arranged on a chip setting area of the substrate structure, wherein the chip is electrically connected to the patterned circuit layer, and an edge portion of the chip is in the normal projection direction with the The strengthening layer overlaps at least partially; and forms an encapsulation to cover the chip, the patterned circuit layer and at least part of the substrate structure, wherein the structural rigidity of the strengthening layer is substantially greater than that of the solder resist layer.

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