JP7416607B2 - semiconductor equipment - Google Patents

Description

The present disclosure relates to a semiconductor device .

Conventionally, electronic components including semiconductor chips include a substrate on which an element is mounted and a sealing resin that covers the element. For example, Patent Document 1 describes a wiring body having external connection terminals on one side and a semiconductor chip mounted on the other side, and a sealing resin formed on the other side of the wiring body to seal the semiconductor chip. A semiconductor device including the following is disclosed.

JP2013-197263A

By the way, various circuits using the above-mentioned electronic components are configured to include passive elements such as resistors along with the electronic components. Therefore, it is necessary to mount passive elements in addition to electronic components on a circuit board for configuring the circuit.

An object of the present disclosure is to provide a semiconductor device mounting a plurality of elements.

A semiconductor device according to an embodiment of the present disclosure includes a substrate having a main surface and a back surface facing opposite to each other in the thickness direction, main surface wiring provided on the main surface of the substrate, and main surface wiring facing the main surface of the substrate. and a first element electrode provided on the element main surface, a first element having a lower surface facing the substrate main surface, and a second element electrode provided on the lower surface. a first joint portion that joins the main surface wiring and the first element; and a second joint portion that joins the main surface wiring and the second element, the first joint portion has a first solder layer interposed between the first element and the main surface wiring, and the second joint part has a first solder layer interposed between the second element and the main surface wiring. There are two solder layers, and the first solder layer is thicker than the second solder layer.

According to this configuration, it is possible to provide a semiconductor device in which a plurality of elements are mounted.
A method for manufacturing a semiconductor device, which is another aspect of the present disclosure, includes the steps of forming a first substrate-side solder layer and a second substrate-side solder layer on a base material on which main surface wiring is formed. , Temporarily fixing an element-side solder layer connected to a first element electrode of the first element to the first substrate-side solder layer, and temporarily fixing a second element electrode of the second element to the second substrate-side solder layer. a first bonding portion that includes a first solder layer constituted by the first substrate-side solder layer and the element-side solder layer and that bonds the main surface wiring and the first element by a reflow process; forming a second bonding portion including a second solder layer configured from the second substrate side solder layer and bonding the main surface wiring to the second element.

According to this configuration, it is possible to provide a method for manufacturing a semiconductor device in which a plurality of elements are mounted.

According to one aspect of the present disclosure, it is possible to provide a semiconductor device in which a plurality of elements can be suitably mounted.

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view showing the first joint. FIG. 3 is a cross-sectional view showing the second joint. FIG. 3 is a cross-sectional view showing the manufacturing process of the first joint part and the second joint part. FIG. 3 is a cross-sectional view showing the manufacturing process of the first joint part and the second joint part. FIG. 3 is a cross-sectional view showing the manufacturing process of the first joint part and the second joint part. FIG. 3 is a cross-sectional view showing the manufacturing process of the first joint part and the second joint part. FIG. 3 is a cross-sectional view showing the manufacturing process of the first joint part and the second joint part. FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to a modified example. FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to a modified example. FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to a modified example.

Embodiments and modified examples will be described below with reference to the drawings. The embodiments and modified examples shown below are examples of configurations and methods for embodying technical ideas, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are limited to the following. It's not something you do. Various changes can be made to each of the following embodiments and modified examples. Moreover, the following embodiments and modifications can be implemented in combination with each other within a technically consistent range.

(First embodiment)
Hereinafter, the semiconductor device A1 of the first embodiment will be described based on FIGS. 1 to 9.
As shown in FIGS. 1 and 2, the semiconductor device A1 of the first embodiment includes a substrate 10, a wiring section 20, a protective film 30, a first bonding section 40, a second bonding section 50, a first element 60, a second It includes an element 70, a sealing resin 80, and an external conductive film 90.

FIG. 1 is a plan view of the semiconductor device A1, and for convenience of understanding, the protective film 30 and the sealing resin 80 are shown. FIG. 2 is a schematic cross-sectional view of the semiconductor device A1, and clearly shows the connection between the first element 60 and the second element 70. FIG. 3 is a cross-sectional view showing the first joint portion 40. As shown in FIG. FIG. 4 is a cross-sectional view showing the second joint portion 50. As shown in FIG. 5 to 8 are cross-sectional views showing the manufacturing process of the first joint portion 40. As shown in FIG. FIG. 9 is a cross-sectional view showing the manufacturing process of the second joint portion 50. As shown in FIG.

A semiconductor device A1 shown in these figures is a device that is surface mounted on circuit boards of various electronic devices. Here, for convenience of explanation, the thickness direction of the semiconductor device A1 will be referred to as the thickness direction Z. Further, a direction along one side of the semiconductor device A1 (left-right direction in the plan view) orthogonal to the thickness direction Z is referred to as a first direction X. Further, a direction (vertical direction in the plan view) perpendicular to both the thickness direction Z and the first direction X is referred to as a second direction Y.

The substrate 10 is a support member that mounts the first element 60 and the second element 70 and serves as the basis of the semiconductor device A1. The shape of the substrate 10 when viewed from the thickness direction Z is a rectangle whose long sides extend along the first direction X, as shown in FIG.

The substrate 10 has a main substrate surface 101, a substrate back surface 102, and a plurality of substrate side surfaces 103. The main surface 101 of the substrate and the back surface 102 of the substrate face opposite to each other in the thickness direction Z. The main surface 101 of the substrate is flat. The back surface 102 of the substrate is flat. The substrate side surface 103 faces in a direction intersecting the thickness direction Z. Each substrate side surface 103 intersects with the substrate main surface 101 and the substrate back surface 102, and in the first embodiment, perpendicularly intersects with the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 is sandwiched between the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 is flat. In this embodiment, the substrate side surface 103 includes a pair of substrate side surfaces 103x that face oppositely to each other in the first direction X, and a pair of substrate side surfaces 103y that face oppositely to each other in the second direction Y.

The substrate 10 is made of, for example, an electrically insulating material. As the material of the substrate 10, for example, a synthetic resin mainly composed of epoxy resin, ceramics, glass, etc. can be used. The substrate 10 has a plurality of through holes 11 that penetrate the substrate 10 from the substrate main surface 101 to the substrate back surface 102 in the thickness direction Z. As shown in FIG. 1, in the first embodiment, the substrate 10 has five through holes 11 along each of the pair of substrate side surfaces 103y. The through hole 11 has, for example, a rectangular shape when viewed from the thickness direction Z. Note that the shape of the through hole 11 may be circular or polygonal.

The wiring section 20 includes a plurality of through wirings 21 and a plurality of main surface wirings 22. The through wiring 21 is arranged in each through hole 11 of the substrate 10. The main surface wiring 22 is provided on the substrate main surface 101 of the substrate 10. The main surface wiring 22 is electrically connected to the through wiring 21.

The through wiring 21 has an upper surface 211, a lower surface 212, and a plurality of side surfaces 213. The upper surface 211 and the lower surface 212 face oppositely to each other in the thickness direction Z. Each side surface 213 faces in a direction intersecting the thickness direction Z. Each side surface 213 is sandwiched between an upper surface 211 and a lower surface 212. In the first embodiment, the upper surface 211 of the through wiring 21 is flush with the main substrate surface 101 of the substrate 10 . Further, in the first embodiment, the lower surface 212 of the through wiring 21 is flush with the substrate back surface 102 of the substrate 10. This lower surface 212 is an exposed surface exposed from the substrate back surface 102 of the substrate 10. Note that at least one of the upper surface 211 and the lower surface 212 of the through wiring 21 may not be flush with the substrate main surface 101 and the substrate back surface 102 of the substrate 10. Further, the side surface 213 of the through wiring 21 is in contact with the inner wall surface 113 of the through hole 11 . The through wiring 21 is made of an electrically conductive material. As a material for the through wiring 21, for example, Cu (copper), an alloy containing Cu, or the like can be used.

The main surface wiring 22 has an upper surface 221, a lower surface 222, and a side surface 223. The upper surface 221 and the lower surface 222 face opposite sides in the thickness direction Z. The side surface 223 faces in a direction intersecting the thickness direction Z. The upper surface 221 of the main surface wiring 22 faces in the same direction as the main substrate surface 101 of the substrate 10 . The lower surface 222 of the main surface wiring 22 faces the same direction as the substrate back surface 102 of the substrate 10 and faces the substrate main surface 101 of the substrate 10 . The side surface 223 of the main surface wiring 22 faces in the same direction as the substrate side surface 103 of the substrate 10 . Further, the side surface 223 of the main surface wiring 22 intersects with the upper surface 221 and the lower surface 222 of the main surface wiring 22.

The main surface wiring 22 is made of an electrically conductive material. As shown in FIGS. 3 and 4, the main surface wiring 22 includes a metal layer 22a and a conductive layer 22b. The metal layer 22a and the conductive layer 22b are laminated in this order on the main surface 101 of the substrate 10. The metal layer 22a includes, for example, a Ti (titanium) layer in contact with the main surface 101 of the substrate 10 and the upper surface 211 of the through wiring 21 shown in FIG. 1, and a Cu layer in contact with the Ti layer. Metal layer 22a is formed as a seed layer for forming conductive layer 22b. The metal layer 22a has an upper surface and a lower surface facing oppositely to each other in the thickness direction Z. The conductive layer 22b is formed on the upper surface of the metal layer 22a. The conductive layer 22b is made of Cu or an alloy containing Cu. The conductive layer 22b has an upper surface and a lower surface facing oppositely to each other in the thickness direction Z. The thickness of the conductive layer 22b is, for example, 15 μm or more and 20 μm or less. In this embodiment, the lower surface of the metal layer 22a is the lower surface 222 of the main surface wiring 22, the upper surface of the metal layer 22a is in contact with the lower surface of the conductive layer 22b, and the upper surface of the conductive layer 22b is the upper surface 221 of the main surface wiring 22. . The side surfaces of the metal layer 22a and the conductive layer 22b constitute the side surfaces 223 of the main surface wiring 22.

As shown in FIG. 1, the first element 60 and the second element 70 are connected to the main surface wiring 22. In this embodiment, the main surface wiring 22 includes a first wiring 23 to which the first element 60 is connected, and a second wiring 24 to which the second element 70 is connected. The first wiring 23 is a main surface wiring between the first element 60 and the through wiring 21. The second wiring 24 is a main surface wiring between the second element 70 and the first wiring 23. The upper surface 221, lower surface 222, and side surface 223 of the main surface wiring 22 are the upper surface, lower surface, and side surface of the first wiring 23 and the second wiring 24.

The protective film 30 is formed on the main substrate surface 101 of the substrate 10 . The protective film 30 covers the substrate main surface 101 and the main surface wiring 22.
The protective film 30 has an upper surface 301, a lower surface 302, and side surfaces 303. The upper surface 301 and the lower surface 302 face oppositely to each other in the thickness direction Z. The side surface 303 faces in a direction intersecting the thickness direction Z. The upper surface 301 of the protective film 30 faces in the same direction as the main substrate surface 101 of the substrate 10. The lower surface 302 of the protective film 30 faces the main substrate surface 101 of the substrate 10 . The protective film 30 is made of a material that has electrical insulation and heat resistance. As the material of the protective film 30, for example, polyimide resin can be used.

As shown in FIG. 2, the protective film 30 has a first opening 31 that exposes a part of the upper surface of the first wiring 23 and a second opening 32 that exposes a part of the upper surface of the second wiring 24. have.
As shown in FIG. 3, the first opening 31 penetrates the protective film 30 from the upper surface 301 to the lower surface 302 of the protective film 30. The inner surface 313 of the first opening 31 is inclined such that the inner dimension of the first opening 31 increases from the lower surface 302 of the protective film 30 toward the upper surface 301 of the protective film 30. The shape of the first opening 31 is, for example, square when viewed from the thickness direction Z. Note that the first opening 31 can have various shapes when viewed from the thickness direction Z, such as a rectangular shape, a circular shape, and a polygonal shape.

As shown in FIG. 4, the second opening 32 penetrates the protective film 30 from the upper surface 301 to the lower surface 302 of the protective film 30. The inner side surface 323 of the second opening 32 is inclined such that the inner dimension of the second opening 32 increases from the lower surface 302 of the protective film 30 toward the upper surface 301 of the protective film 30. The shape of the second opening 32 is, for example, square when viewed from the thickness direction Z. Note that the shape of the second opening 32 can be various, such as a rectangular shape, a circular shape, a polygonal shape, etc. when viewed from the thickness direction Z.

As shown in FIGS. 2 and 3, the first joint 40 is provided in the first opening 31 of the protective film 30. The first joint portion 40 is formed on the upper surface 221 of the first wiring 23 (main surface wiring 22). The first wiring 23 is electrically connected to the first wiring 23 (main surface wiring 22). The first joint 40 connects the first element 60 to the first wiring 23.

The first joint 40 includes a conductive layer 41 , a plating layer 42 , and a solder layer 43 . The conductive layer 41, the plating layer 42, and the solder layer 43 are laminated in this order on the first wiring 23 (main surface wiring 22).

As shown in FIG. 3, the conductive layer 41 has an upper surface 411, a lower surface 412, and side surfaces 413. The upper surface 411 and the lower surface 412 face opposite to each other in the thickness direction Z. The upper surface 411 of the conductive layer 41 faces the same side as the upper surface 221 of the first wiring 23 (main surface wiring 22). The lower surface 412 of the conductive layer 41 is in contact with the upper surface 221 of the first wiring 23 (main surface wiring 22). A side surface 413 of the conductive layer 41 faces in a direction intersecting the thickness direction Z. Side surfaces 413 of the conductive layer 41 are inclined such that the upper surface 411 of the conductive layer 41 is larger than the lower surface 412 of the conductive layer 41 . In this embodiment, the side surface 413 of the conductive layer 41 is in contact with the inner surface 313 of the first opening 31 of the protective film 30 .

The plating layer 42 has an upper surface 421, a lower surface 422, and side surfaces 423. The upper surface 421 and the lower surface 422 face opposite to each other in the thickness direction Z. The upper surface 421 of the plating layer 42 faces the same side as the upper surface 411 of the conductive layer 41. The lower surface 422 of the plating layer 42 faces the upper surface 411 of the conductive layer 51 and is in contact with the upper surface 411 of the conductive layer 41 . A side surface 423 of the plating layer 42 faces in a direction intersecting the thickness direction Z. Side surfaces 423 of the plating layer 42 are inclined such that the top surface 421 of the plating layer 42 is larger than the bottom surface 422 of the plating layer 42 . In this embodiment, the side surface 423 of the plating layer 42 is in contact with the inner surface 313 of the first opening 31 of the protective film 30 . The size of the upper surface 421 of the plating layer 42 is equal to the size of the element electrode 65 in the first element 60 when viewed from the thickness direction.

The upper surface 421 of the plating layer 42 is located closer to the upper surface 221 of the first wiring 23 than the upper surface 301 of the protective film 30 . That is, the total thickness of the conductive layer 41 and the plating layer 42 is thinner than the thickness of the protective film 30 on the upper surface 221 of the first wiring 23 .

Solder layer 43 is interposed between plating layer 42 and first element 60. Solder layer 43 has an upper surface 431, a lower surface 432, and side surfaces 433. The upper surface 431 and the lower surface 432 face opposite to each other in the thickness direction Z. The upper surface 431 of the solder layer 43 faces the first element 60 and is in contact with the element electrode 65 of the first element 60 . The lower surface 432 of the solder layer 43 faces the main substrate surface 101 of the substrate 10 and is in contact with the upper surface 421 of the plating layer 42 .
In this embodiment, the solder layer 43 protrudes from the upper surface 301 of the protective film 30 in the thickness direction Z. The side surface 433 of the solder layer 43 of this embodiment has a first side surface 433a on the side of the plating layer 42 and a second side surface 433b on the side of the first element 60. The first side surface 433 a is located inside the first opening 31 of the protective film 30 and contacts the inner side surface 313 of the first opening 31 of the protective film 30 . The second side surface 433b is located closer to the first element 60 than the upper surface 301 of the protective film 30, and extends toward the first element 60 in the thickness direction Z from the upper end of the first side surface 433a. The solder layer 43 of this embodiment has a columnar shape extending in the thickness direction Z.

The conductive layer 41 is made of Cu or an alloy containing Cu. The plating layer 42 is made of Ni (nickel). The solder layer 43 is made of Sn (tin) and an alloy containing Sn. This alloy is, for example, a Sn--Ag (silver) alloy, a Sn--Sb (antimony)-based alloy, or the like.

As shown in FIGS. 2 and 3, the second joint 50 is provided in the second opening 32 of the protective film 30. The second joint portion 50 is formed on the upper surface 221 of the second wiring 24 (main surface wiring 22). The second wiring 24 is electrically connected to the second wiring 24 (main surface wiring 22). The second joint 50 connects the second element 70 to the second wiring 24.

The second joint 50 includes a conductive layer 51, a plating layer 52, and a solder layer 53. The conductive layer 51, the plating layer 52, and the solder layer 53 are laminated in this order on the second wiring 24 (main surface wiring 22).

As shown in FIG. 4, the conductive layer 51 has an upper surface 511, a lower surface 512, and side surfaces 513. The upper surface 511 and the lower surface 512 face opposite to each other in the thickness direction Z. The upper surface 511 of the conductive layer 51 faces the same side as the upper surface 221 of the second wiring 24 (main surface wiring 22). The lower surface 512 of the conductive layer 51 is in contact with the upper surface 221 of the second wiring 24 (main surface wiring 22). A side surface 513 of the conductive layer 51 faces in a direction intersecting the thickness direction Z. Side surfaces 513 of the conductive layer 51 are inclined such that the upper surface 511 of the conductive layer 51 is larger than the lower surface 512 of the conductive layer 51. In this embodiment, the side surface 513 of the conductive layer 51 is in contact with the inner surface 323 of the second opening 32 of the protective film 30 .

Plating layer 52 has an upper surface 521, a lower surface 522, and side surfaces 523. The upper surface 521 and the lower surface 522 face opposite to each other in the thickness direction Z. The upper surface 521 of the plating layer 52 faces the same side as the upper surface 511 of the conductive layer 51. The lower surface 522 of the plating layer 52 faces the upper surface 511 of the conductive layer 51 and is in contact with the upper surface 511 of the conductive layer 51 . A side surface 523 of the plating layer 52 faces in a direction intersecting the thickness direction Z. Side surfaces 523 of the plating layer 52 are inclined such that the top surface 521 of the plating layer 52 is larger than the bottom surface 522 of the plating layer 52. In this embodiment, the side surface 523 of the plating layer 52 is in contact with the inner surface 323 of the second opening 32 of the protective film 30. The size of the upper surface 521 of the plating layer 52 is larger than the size of the element electrode 71 in the second element 70 when viewed from the thickness direction.

The upper surface 521 of the plating layer 52 is located closer to the upper surface 221 of the second wiring 24 than the upper surface 301 of the protective film 30 . That is, the total thickness of the conductive layer 51 and the plating layer 52 is thinner than the thickness of the protective film 30 on the upper surface 221 of the second wiring 24 .

Solder layer 53 is interposed between plating layer 42 and second element 70 . Solder layer 53 has an upper surface 531, a lower surface 532, and side surfaces 533. The upper surface 531 and the lower surface 532 face opposite to each other in the thickness direction Z. The upper surface 531 of the solder layer 53 faces the second element 70 and is in contact with the element electrode 71 of the second element 70 . The lower surface 532 of the solder layer 53 faces the main substrate surface 101 of the substrate 10 and is in contact with the upper surface 521 of the plating layer 52 . A side surface 533 of the solder layer 53 faces in a direction intersecting the thickness direction Z.

In this embodiment, the size of the lower surface 532 of the solder layer 53 is equal to the size of the upper surface 521 of the plating layer 52. The size of the upper surface 531 of the solder layer 53 is smaller than the size of the lower surface 532 of the solder layer 53 and is equal to the size of the element electrode 71 of the second element 70 . Therefore, in the solder layer 53 of this embodiment, the cross section in the plane along the thickness direction Z is trapezoidal. The side surface 533 of the solder layer 53 in this embodiment is curved so as to be depressed toward the inside of the solder layer 53. Note that the side surface 533 does not need to be curved.

The conductive layer 51 is made of Cu or an alloy containing Cu. The plating layer 52 is made of Ni. The solder layer 53 is made of Sn or an alloy containing Sn. This alloy is, for example, a Sn-Ag alloy, a Sn-Sb alloy, or the like.

As shown in FIG. 1, the first element 60 has a rectangular shape when viewed from the thickness direction Z. As shown in FIGS. 1 and 2, the first element 60 has an element main surface 601, an element rear surface 602, and an element side surface 603. The element main surface 601 and the element back surface 602 face opposite sides in the thickness direction Z. The element side surface 603 faces in a direction intersecting the thickness direction Z. The element side surface 603 intersects the element main surface 601 and the element back surface 602. The element main surface 601 faces the substrate main surface 101 of the substrate 10 . The element back surface 602 faces in the same direction as the main substrate surface 101 of the substrate 10. In this embodiment, the element side surface 603 includes a pair of substrate side surfaces 603x facing oppositely to each other in the first direction X, and a pair of substrate side surfaces 603y facing oppositely to each other in the second direction Y.

The first element 60 is, for example, an integrated circuit (IC) such as an LSI (Large Scale Integration). The integrated circuit constituted by the first element 60 is, for example, a voltage control circuit such as an LDO (Low Drop Out). Note that the integrated circuit constituted by the first element 60 may be an amplifier circuit such as an operational amplifier, a driving circuit for a switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like.

The main element surface 601 of the first element 60 is a surface on which structural members for the functions of the first element 60 are formed. For example, the first element 60 has a power transistor 60T formed on the element main surface 601 side.

As shown in FIG. 3, the first element 60 includes an element substrate 61, an electrode pad 62, an insulating film 63, a protective film 64, an element electrode 65, and an element-side solder layer 66. The electrode pad 62 is made of Al (aluminum), for example. The insulating film 63 covers the surface of the element substrate 61 and the periphery of the electrode pad 62 . The insulating film 63 is made of SiN, for example. The protective film 64 covers the surface of the insulating film 63 and a portion of the electrode pad 62, and exposes a portion of the surface of the electrode pad 62 as a connection terminal. The protective film 64 is made of polyimide resin, for example.

The element electrode 65 is connected to a connection terminal that is an exposed portion of the electrode pad 62. The element electrode 65 includes, for example, a metal layer 65a, a conductive layer 65b, and a barrier layer 65c. The metal layer 65a is formed to cover the exposed portion of the electrode pad 62 and the end of the opening in the protective film 64 that exposes the electrode pad 62. The metal layer 65a is made of Ti/Cu, for example, and is formed as a seed layer for forming the conductive layer 65b. Conductive layer 65b is formed to cover the lower surface of metal layer 65a. The conductive layer 65b is made of, for example, CU or a Cu alloy. Barrier layer 65c is formed to cover the lower surface of conductive layer 65b. The barrier layer 65c is made of Ni, an alloy containing Ni, or a plurality of metal layers containing Ni. As the barrier layer 65c, for example, Ni, Pd, Au, an alloy containing two or more of these metals, or the like can be used. The lower surface of the barrier layer 65c is the lower surface 652 of the element electrode 65.

The element side solder layer 66 is formed on the lower surface 652 of the element electrode 65. The element-side solder layer 66 is formed on the lower surface 652 of the element electrode 65 in the first element 60 before mounting, and is, for example, a solder bump. This element side solder layer 66 constitutes the solder layer 43 of the first joint section 40 together with the substrate side solder layer 44 formed on the upper surface 421 of the plating layer 42 of the first joint section 40 . The solder layer 43 configured in this manner connects the element electrode 65 of the first element 60 to the plating layer 42 of the first joint 40 . Thereby, the first element 60 is mounted with the element main surface 601 facing the substrate 10. Therefore, the element main surface 601 can be said to be an element mounting surface for mounting the first element 60. The first element 60 is a so-called flip-chip type element connected to the first wiring 23 through an element electrode 65.

As shown in FIG. 1, the second element 70 has a rectangular shape when viewed from the thickness direction Z. As shown in FIGS. 1 and 2, the second element 70 has an upper surface 701, a lower surface 702, and a side surface 703. The upper surface 701 and the lower surface 702 face opposite to each other in the thickness direction Z. The side surface 703 faces in a direction intersecting the thickness direction Z. The side surface 703 intersects the upper surface 701 and the lower surface 702. The upper surface 701 of the second element 70 faces in the same direction as the main substrate surface 101 of the substrate 10 . The lower surface 702 of the second element 70 faces the main substrate surface 101 of the substrate 10 .

The second element 70 is an element connected to the first element 60, and is, for example, a passive element such as a diode. Note that the second element 70 may be an element formed of a single component such as a diode, a resistor, a capacitor, an inductor, or the like. Furthermore, the second element 70 may be an element in which a plurality of structural members are formed.

In this embodiment, the second element 70 is an element connected to the functional element included in the first element 60. This second element 70 is preferably mounted near the functional elements included in the first element 60. For example, the first element 60 includes a power transistor as a functional element. The second element 70 is a diode connected to the power transistor 60T of the first element 60.

As shown in FIGS. 2 and 4, the second element 70 has two element electrodes 71 on the lower surface 702. The element electrode 71 has an upper surface 711, a lower surface 712, and a side surface 713. The upper surface 711 and the lower surface 712 face oppositely to each other in the thickness direction Z. The side surface 713 faces in a direction intersecting the thickness direction Z. The upper surface 711 of the element electrode 71 is in contact with the lower surface 702 of the second element 70 . The lower surface 712 of the element electrode 71 is in contact with the upper surface 531 of the solder layer 53 of the second joint portion 50 . Note that the side surface 713 of the element electrode 71 may be in contact with the solder layer 53. This second element 70 is a so-called flip-chip type element connected to the second wiring 24 through an element electrode 71. The element electrode 71 is composed of, for example, a plurality of metal layers stacked on each other. Examples of the metal layer include a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. Note that the material of the element electrode 71 is not limited, but may be composed of, for example, a Ni layer and an Au layer, or may be Sn.

As shown in FIG. 2, the sealing resin 80 is formed to be in contact with the upper surface 301 of the protective film 30 and to cover the first element 60 and the second element 70. Specifically, the sealing resin 80 covers the element main surface 601, the element rear surface 602, and the element side surface 603 of the first element 60, and also covers the upper surface 701, the lower surface 702, and the side surface 703 of the second element 70. Furthermore, in the first embodiment, the sealing resin 80 covers the first joint 40 and the second joint 50.

The sealing resin 80 overlaps the substrate 10 when viewed from the thickness direction Z. The sealing resin 80 has a resin top surface 801 facing in the same direction as the substrate main surface 101 of the substrate 10 and a resin side surface 803 facing in the same direction as the substrate side surface 103. The sealing resin 80 is made of, for example, a resin having electrical insulation properties. As this resin, for example, a synthetic resin based on epoxy resin can be used. Furthermore, the sealing resin 80 is colored, for example, black.

The external conductive film 90 is formed on the back surface 102 of the substrate 10 . The external conductive film 90 is formed to cover the lower surface 212 of the through wiring 21 . The external conductive film 90 becomes an external connection terminal of the semiconductor device A1. The external conductive film 90 is composed of, for example, a plurality of metal layers stacked on each other. Examples of the metal layer include a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. Note that the material of the external conductive film 90 is not limited, but may be composed of, for example, a stack of a Ni layer and an Au layer, or may be made of Sn.

(Manufacturing process)
Next, an example of the manufacturing process of the semiconductor device A1 will be described.
First, a support substrate is prepared. The support substrate is made of, for example, a single crystal material of Si. Note that a substrate made of a synthetic resin material such as epoxy resin may be used as the support substrate. Terminal pillars serving as through wiring 21 are formed on the upper surface of the support substrate. The terminal pillar is made of, for example, Cu or an alloy containing Cu. The terminal pillar includes, for example, a seed layer formed on the upper surface of the support substrate and a plated metal formed on the upper surface of the seed layer. Note that the terminal pillar may be formed of a columnar material of Cu.

Next, a base material is formed that is in contact with the upper surface of the support substrate and covers the terminal pillars. The base material is formed to cover the upper surface of the terminal pillar. As the material of this base material, the material constituting the substrate 10 shown in FIG. 2 can be used. In this embodiment, as the material of the base material, a synthetic resin mainly composed of epoxy resin or the like can be used.

Next, a portion of the base material and the terminal pillar are ground to form the through wiring 21 exposed on the upper surface of the base material and the upper surface 211 of the through wiring 21. In grinding the base material, the base material is made to have the same thickness as the substrate 10.

Next, the main surface wiring 22 that contacts the upper surface of the base material and the upper surface 211 of the through wiring 21 is formed. Main surface wiring 22 includes a metal layer 22a and a conductive layer 22b. First, the metal layer 22a is formed by, for example, a sputtering method. For example, the metal layer 22a including a Ti layer and a Cu layer includes a Ti layer formed on the upper surface of the base material and the upper surface 211 of the through wiring 21, and a Cu layer in contact with the Ti layer. Next, a conductive layer 22b is formed by depositing plating metal on the surface of the metal layer 22a, for example, by electrolytic plating using the metal layer 22a as a conductive path.

Next, a resin layer is formed on the entire upper surface of the base material. The resin layer is formed, for example, by spray coating a photosensitive resin, such as a polyimide resin. The resin layer is formed to cover the main surface wiring 22. Note that the resin layer can also be formed by pasting a film-like photosensitive resin. Next, the resin layer is exposed to light using a photomask and developed, thereby forming the protective film 30. A first opening 31 and a second opening 32 are formed in the protective film 30 by exposure and development.

Next, the first bonding portion 40 and the second bonding portion 50 are formed on the main surface wiring 22. Details of the process of forming the first joint portion 40 and the second joint portion 50 will be described later.
Next, the first element 60 and the second element 70 are mounted. The first element 60 and the second element 70 are mounted by flip chip bonding (FCB). For example, using a flip-chip bonder, flux is applied by pin transfer to the element-side solder layer 66 of the first element 60, and flip-chip mounting is performed. Thereby, the first element 60 is temporarily attached to the first joint portion 40. Further, using a flip-chip bonder, flux is applied by pin transfer onto the element electrode 71 of the second element 70, and flip-chip mounting is performed. Thereby, the second element 70 is temporarily attached to the second joint portion 50.

Thereafter, after the substrate-side solder layer 44 of the first joint portion 40, the element-side solder layer 66 of the first element 60, and the substrate-side solder layer 53 of the second joint portion 50 are brought into a liquid phase by reflow treatment, cooling is performed. A solder layer 43 of the first joint portion 40 and a solder layer 53 of the second joint portion 50 are formed. The first element 60 and the second element 70 are mounted on the substrate 10 by these solder layers 43 and 53.

Next, a resin layer is formed to cover the upper surface 301 of the protective film 30, the first element 60, and the second element 70. The resin layer is a member that becomes the sealing resin 80 shown in FIG. The resin layer is, for example, a synthetic resin whose main material is epoxy resin. For example, the resin layer is formed by transfer molding.

Next, the support substrate is removed, for example by grinding. Note that it is also possible to use a method in which a release film is formed in advance between the support substrate and the base material, and the support substrate is removed by a peeling method.
Next, an external conductive film 90 is formed on the surface of the through wiring 21 exposed from the base material (lower surface 212 shown in FIG. 2). The external conductive film 90 is made of, for example, plated metal. For example, the external conductive film 90 is formed by depositing plating metals such as Ni, Pd, and Au in this order by electroless plating. Note that the structure and formation method of the external conductive film 90 are not limited.

Next, a dicing tape is attached to the resin layer, and the base material and the resin layer are cut and divided into individual pieces. In dividing, for example, a dicing blade is used to cut from the base material side to the dicing tape, thereby cutting the base material and the resin layer. The individual piece is a semiconductor device A1.

Next, an example of the manufacturing process of the first joint portion 40 and the second joint portion 50 will be described based on FIGS. 5 to 9.
5 to 9 are cross-sectional views for explaining an example of the manufacturing process of the first joint portion 40 and the second joint portion 50.

As shown on the left side of FIG. 5, the first wiring 23 of the main surface wiring 22 consists of a metal layer 22a and a conductive layer 22b, which are laminated on the upper surface S101 of the base material S10, which becomes the substrate 10. Further, as shown on the right side of FIG. 5, the second wiring 24 of the main surface wiring 22 is composed of a metal layer 22a and a conductive layer 22b, which are laminated on the upper surface S101 of the base material S10, which becomes the substrate 10.

A metal layer 22a and a conductive layer 22b are laminated in this order on the upper surface S101 of the base material S10. First, the metal layer 22a is formed by, for example, a sputtering method. When the metal layer 22a is composed of a Ti layer and a Cu layer stacked on each other, first a Ti layer is formed in contact with the upper surface S101 of the base material S10, and then a Cu layer is formed in contact with this Ti layer. Next, the conductive layer 22b is formed by, for example, electrolytic plating. In the electrolytic plating method, the conductive layer 22b is formed by using the metal layer 22a as a conductive path, using the metal layer 22a as a seed layer, and depositing Cu as a plating metal on the upper surface of the metal layer 22a. By forming a resist mask (not shown) on the upper surface of the metal layer 22a serving as a seed layer, the conductive layer 22b can be formed only in the portion that will become the main surface wiring 22. After removing the resist mask described above, the exposed metal layer 22a is removed by etching, for example, to obtain the first wiring 23 and the second wiring 24 (main surface wiring 22) made of the metal layer 22a and the conductive layer 22b. It will be done.

As shown in FIG. 6, a protective film 30 is formed to cover the conductive layer 22b (main surface wiring 22) and the surface of the base material S10. The protective film 30 is formed, for example, by photolithography using a photosensitive resist layer. A photosensitive resist layer is formed in contact with the conductive layer 22b and the surface of the base material S10. The resist layer is formed by, for example, spraying a liquid photoresist. Note that a film-like photoresist may also be used. By exposing and developing the resist layer, a protective film 30 having a first opening 31 shown on the left side of FIG. 6 and a second opening 32 shown on the right side of FIG. 6 is formed.

As shown on the left side of FIG. 7, a conductive layer 41 and a plating layer 42 are laminated in this order on the upper surface of the conductive layer 22b exposed through the first opening 31 of the protective film 30. Further, as shown on the right side of FIG. 7, a conductive layer 51 and a plating layer 52 are laminated in this order on the upper surface 221 of the conductive layer 22b exposed through the second opening 32 of the protective film 30.

First, a conductive layer 41 is formed on the upper surface 221 of the conductive layer 22b exposed from the first opening 31 of the protective film 30, and a conductive layer 41 is formed on the upper surface 221 of the conductive layer 22b exposed from the second opening 32 of the protective film 30. Form 51. The conductive layers 41 and 51 are formed, for example, by electrolytic plating. The conductive layers 41 and 51 are formed by depositing Cu as a plating metal on the upper surface 221 of the conductive layer 22b, using the conductive layer 22b as a conductive path.

Next, a plating layer 42 is formed on the upper surface of the conductive layer 41 exposed from the first opening 31 of the protective film 30, and a plating layer 52 is formed on the upper surface of the conductive layer 51 exposed from the second opening 32 of the protective film 30. form. The plating layers 42 and 52 are formed by, for example, electrolytic plating. Using the conductive layers 41 and 51 as conductive paths, Ni is deposited as a plating metal on the upper surfaces 411 and 511 of the conductive layers 41 and 51 to form plating layers 42 and 52.

As shown in FIG. 8, a substrate-side solder layer 44 is formed on the upper surface 421 of the plating layer 42 exposed from the first opening 31 of the protective film 30, and the plating layer exposed from the second opening 32 of the protective film 30 is A solder layer 53 is formed on the upper surface 521 of 52 . The substrate-side solder layers 44 and 53 are formed, for example, by electrolytic plating. A mask (not shown) is formed on the upper surface 301 of the protective film 30. The mask is formed, for example, by photolithography using a photosensitive resist layer. A photosensitive resist layer is formed on the upper surface of the protective film 30, and the resist layer is exposed and developed to form an opening that communicates with each of the first opening 31 and the second opening 32. do. Then, using the plating layers 42, 52 as conductive paths, an alloy containing Sn as a plating metal is deposited on the upper surfaces 421, 521 of the plating layers 42, 52 to form substrate-side solder layers 44, 53. Then, the mask (not shown) is removed.

As shown on the left side of FIG. 9, an element-side solder layer 66 is formed on the element electrode 65 of the first element 60. This element side solder layer 66 is a solder bump with respect to the element electrode 65. This element-side solder layer 66 is bonded to the substrate-side solder layer 44 by reflow processing, and constitutes the solder layer 43 shown in FIG. 3. For example, using a flip-chip bonder, flux is applied by pin transfer to the element-side solder layer 66 of the first element 60, and flip-chip mounting is performed to the substrate-side solder layer 44 of the first joint portion 40. Thereby, the first element 60 is temporarily attached to the first joint portion 40. Thereafter, the substrate-side solder layer 44 of the first joint portion 40 and the element-side solder layer 66 of the first element 60 are brought into a liquid phase by a reflow process, and then the solder layer 43 shown in FIG. 3 is formed by cooling.

As shown on the right side of FIG. 9, no solder layer is formed on the element electrode 71 of the second element 70. Note that in some cases, a thin solder film is formed on the surface of the element electrode 71. This element electrode 71 is directly bonded to the solder layer 53 by a reflow process. For example, using a flip chip bonder equipped with the first element 60 , flux is applied by pin transfer to the element electrode 71 of the second element 70 , and the second element 70 is flipped onto the solder layer 53 of the second joint 50 . Mount the chip. Thereby, the second element 70 is temporarily attached to the second joint portion 50. Thereafter, after the solder layer 53 of the second joint part 50 is brought into a liquid phase state by a reflow process, the solder layer 53 of the second joint part 50 shown in FIG. 4 is formed by cooling.

(effect)
The semiconductor device A1 includes a substrate 10, a main surface wiring 22, a first element 60, a second element 70, a first joint 40, and a second joint 50. The substrate 10 has a substrate main surface 101 and a substrate back surface 102 facing oppositely to each other in the thickness direction Z. The main surface wiring 22 is provided on the substrate main surface 101 of the substrate 10. The first element 60 has an element main surface 601 facing the substrate main surface 101 and an element electrode 65 provided on the element main surface 601. The second element 70 has a lower surface 702 facing the substrate main surface 101 and an element electrode 71 provided on the lower surface 702. The first joint portion 40 joins the main surface wiring 22 and the first element 60. The second joint portion 50 joins the main surface wiring 22 and the second element 70. The first joint 40 has a solder layer 43 interposed between the first element 60 and the main surface wiring 22, and the second joint 50 has a solder layer 43 interposed between the second element 70 and the main surface wiring 22. It has a solder layer 53 interposed therebetween. The thickness of the solder layer 43 of the first joint part 40 is thicker than the thickness of the solder layer 53 of the second joint part 50.

In this way, the semiconductor device A1 includes the first element 60 and the second element 70 mounted on the main surface wiring 22. Therefore, it is not necessary to separately mount the second element 70 connected to the first element 60 on the circuit board on which the semiconductor device A1 is mounted.

In the first embodiment, the first element 60 is, for example, an LSI, and the second element 70 is, for example, a discrete component such as a diode. In this way, the first element 60 and the second element 70 having different functions can be mounted on the main surface wiring 22 of the semiconductor device A1.

The height of the first joint 40 that joins the first element 60 to the substrate 10 is higher than the height of the second joint 50 that joins the second element 70 to the substrate 10. Therefore, the sealing resin 80 covering the first element 60 is easily filled between the substrate 10 and the first element 60. Then, generation of voids (holes) between the element main surface 601 of the first element 60 and the substrate 10 (protective film 30) is suppressed, and the first element 60 and the first joint portion 40 are sealed with the sealing resin 80. Can be covered. This suppresses the corrosion of the first joint portion 40 and the influence on the first element 60 caused by moisture stored in the voids (holes).

The second element 70 is supported by the two second joints 50. Therefore, even if the solder layer 53 of the second joint portion 50 is thin, the sealing resin 80 can be filled between the protective film 30 and the second element 70. The size of the second joint 50 viewed from the thickness direction Z is smaller than the size of the element electrode 71 of the second element 70, and the solder layer 53 of the second joint 50 is connected to the element electrode 71. The upper surface 531 side of the solder layer 53 connected to the plating layer 52 is smaller than the lower surface 532 side of the solder layer 53 connected to the plating layer 52, and has a truncated pyramid shape (for example, a truncated pyramid shape). Therefore, the sealing resin 80 easily enters the second opening 32 of the protective film 30, and the entire side surface 533 of the solder layer 53 of the second joint portion 50 can be covered with the sealing resin 80.

When viewed from the thickness direction Z, the upper surface 421 of the plating layer 42 of the first joint portion 40 has the same size as the lower surface 652 of the element electrode 65 of the first element 60. Therefore, by the reflow process, the substrate-side solder layer 44 of the first bonding section 40 and the element-side solder layer 66 of the first element 60 in a liquid phase state become a liquid phase state, and the second bonding layer 42 of the first bonding section 40 becomes A self-alignment effect is obtained in which the position of the element electrode 65 of one element 60 is automatically corrected. Thereby, positional shift of the second element can be suppressed.

When viewed from the thickness direction Z, the upper surface 521 of the plating layer 52 of the second joint portion 50 is larger than the element electrode 71 of the second element 70 . Therefore, even if a positional shift occurs in the mounting position of the second element 70 when the second element 70 is mounted, the second element 70 can be reliably joined to the second joint portion 50. This reduces mounting defects of the second element 70.

The first joint portion 40 includes a conductive layer 41 on the upper surface 221 of the main surface wiring 22 , a plating layer 42 on the conductive layer 41 , and a solder layer 43 on the plating layer 42 . The main surface wiring 22 and the conductive layer 41 are made of Cu or an alloy containing Cu, and the solder layer 43 is made of Sn or an alloy containing Sn. Since the plating layer 42 made of Ni is a barrier metal, it prevents alloying of Cu of the conductive layer 41 and Sn of the solder layer 43. Thereby, the generation of voids (Kirkendall voids) between Sn and Cu can be suppressed. The second joint 50 includes a conductive layer 51, a plating layer 52, and a solder layer 53 similar to the first joint 40. Therefore, the plating layer 52, which is a barrier metal, can suppress the generation of voids between the Cu of the conductive layer 51 and the Sn of the solder layer 53.

The conductive layer 41 of the first joint 40 and the conductive layer 51 of the second joint 50 are formed simultaneously in the same process. The plating layer 42 of the first joint portion 40 and the plating layer 52 of the second joint portion 50 are formed simultaneously in the same process. Further, the substrate-side solder layer 44 of the first joint portion 40 and the solder layer 53 of the second joint portion 50 are formed simultaneously in the same process. Therefore, the first joint portion 40 for joining the first element 60 and the second joint portion 50 for joining the second element 70 can be formed efficiently.

The first joint 40 includes a conductive layer 41, a plating layer 42, and a solder layer 43. The solder layer 43 includes a substrate-side solder layer 44 on the plating layer 42 and an element-side solder layer 66 of the first element 60 . The second joint 50 includes a conductive layer 51, a plating layer 52, and a solder layer 53. The thickness of the solder layer 53 of the second joint portion 50 is equal to the thickness of the substrate-side solder layer 44 that constitutes the solder layer 43 of the first joint portion 40 . Therefore, the solder layer 53 of the first joint part 40 can be formed efficiently, which is thicker than the solder layer 53 of the second joint part 50.

As described above, according to this embodiment, the following effects are achieved.
(1-1) The semiconductor device A1 includes a substrate 10, a main surface wiring 22, a first element 60, a second element 70, a first joint 40, and a second joint 50. The first joint 40 has a solder layer 43 interposed between the first element 60 and the main surface wiring 22, and the second joint 50 has a solder layer 43 interposed between the second element 70 and the main surface wiring 22. It has a solder layer 53 interposed therebetween. The thickness of the solder layer 43 of the first joint part 40 is thicker than the thickness of the solder layer 53 of the second joint part 50.

In this way, the semiconductor device A1 includes the first element 60 and the second element 70 mounted on the main surface wiring 22. Therefore, it is not necessary to separately mount the second element 70 connected to the first element 60 on the circuit board on which the semiconductor device A1 is mounted.

(1-2) In the first embodiment, the first element 60 is, for example, an LSI, and the second element 70 is, for example, a discrete component such as a diode. In this way, the first element 60 and the second element 70 having different functions can be mounted on the main surface wiring 22 of the semiconductor device A1.

(1-3) The height of the first joint 40 that joins the first element 60 to the substrate 10 is higher than the height of the second joint 50 that joins the second element 70 to the substrate 10. Therefore, the sealing resin 80 covering the first element 60 is easily filled between the substrate 10 and the first element 60. Then, generation of voids (holes) between the element main surface 601 of the first element 60 and the substrate 10 (protective film 30) is suppressed, and the first element 60 and the first joint portion 40 are sealed with the sealing resin 80. Can be covered. Thereby, corrosion of the first joint portion 40 and the influence on the first element 60 caused by moisture stored in the voids (holes) can be suppressed.

(1-4) The second element 70 is supported by the two second joints 50. Therefore, even if the solder layer 53 of the second joint portion 50 is thin, the sealing resin 80 can be filled between the protective film 30 and the second element 70. The size of the second joint 50 viewed from the thickness direction Z is smaller than the size of the element electrode 71 of the second element 70, and the solder layer 53 of the second joint 50 is connected to the element electrode 71. The upper surface 531 side of the solder layer 53 connected to the plating layer 52 is smaller than the lower surface 532 side of the solder layer 53 connected to the plating layer 52, and has a truncated pyramid shape (for example, a truncated pyramid shape). Therefore, the sealing resin 80 easily enters the second opening 32 of the protective film 30, and the entire side surface 533 of the solder layer 53 of the second joint portion 50 can be covered with the sealing resin 80.

(1-5) When viewed from the thickness direction Z, the upper surface 421 of the plating layer 42 of the first joint portion 40 has the same size as the lower surface 652 of the element electrode 65 of the first element 60. Therefore, by the reflow process, the substrate-side solder layer 44 of the first bonding section 40 and the element-side solder layer 66 of the first element 60 in a liquid phase state become a liquid phase state, and the second bonding layer 42 of the first bonding section 40 becomes A self-alignment effect is obtained in which the position of the element electrode 65 of one element 60 is automatically corrected. Thereby, positional shift of the second element can be suppressed.

(1-6) When viewed from the thickness direction Z, the upper surface 521 of the plating layer 52 of the second joint portion 50 is larger than the element electrode 71 of the second element 70. Therefore, even if a positional shift occurs in the mounting position of the second element 70 when the second element 70 is mounted, the second element 70 can be reliably joined to the second joint portion 50. This reduces mounting defects of the second element 70.

(1-7) The first joint portion 40 includes a conductive layer 41 on the upper surface 221 of the main surface wiring 22, a plating layer 42 on the conductive layer 41, and a solder layer 43 on the plating layer 42. The main surface wiring 22 and the conductive layer 41 are made of Cu or an alloy containing Cu, and the solder layer 43 is made of Sn or an alloy containing Sn. Since the plating layer 42 made of Ni is a barrier metal, it prevents alloying of Cu of the conductive layer 41 and Sn of the solder layer 43. Thereby, the generation of voids (Kirkendall voids) between Sn and Cu can be suppressed. The second joint 50 includes a conductive layer 51, a plating layer 52, and a solder layer 53 similar to the first joint 40. Therefore, the plating layer 52, which is a barrier metal, can suppress the generation of voids between the Cu of the conductive layer 51 and the Sn of the solder layer 53.

(1-8) The conductive layer 41 of the first joint 40 and the conductive layer 51 of the second joint 50 are formed simultaneously in the same process. The plating layer 42 of the first joint portion 40 and the plating layer 52 of the second joint portion 50 are formed simultaneously in the same process. Further, the substrate-side solder layer 44 of the first joint portion 40 and the solder layer 53 of the second joint portion 50 are formed simultaneously in the same process. Therefore, the first joint portion 40 for joining the first element 60 and the second joint portion 50 for joining the second element 70 can be formed efficiently.

(1-9) The first joint portion 40 includes a conductive layer 41, a plating layer 42, and a solder layer 43. The solder layer 43 includes a substrate-side solder layer 44 on the plating layer 42 and an element-side solder layer 66 of the first element 60 . The second joint 50 includes a conductive layer 51, a plating layer 52, and a solder layer 53. The thickness of the solder layer 53 of the second joint portion 50 is equal to the thickness of the substrate-side solder layer 44 that constitutes the solder layer 43 of the first joint portion 40 . Therefore, the solder layer 53 of the first joint part 40 can be formed efficiently, which is thicker than the solder layer 53 of the second joint part 50.

(Second embodiment)
The semiconductor device A2 of the second embodiment will be described below based on FIG. 10.
In the description of the second embodiment, components that are the same as or similar to those of the semiconductor device A1 of the first embodiment are given the same reference numerals as those of the semiconductor device A1 of the first embodiment, and the description thereof will be omitted. May be omitted.

As shown in FIG. 10, the semiconductor device A2 of the second embodiment includes a substrate 10, a wiring section 20, a first bonding section 40, a second bonding section 50, a protective film 30, a first element 60, a second element 70, It includes a sealing resin 80 and an external conductive film 90.

The substrate 10 has a thin plate shape and has no through holes formed therein. The substrate 10 has a main substrate surface 101, a substrate back surface 102, and a plurality of substrate side surfaces 103. The substrate main surface 101 and the substrate back surface 102 face opposite sides in the thickness direction Z. The substrate main surface 101 and the substrate back surface 102 are flat. As the material of this substrate 10, for example, a synthetic resin mainly composed of epoxy resin, ceramics, glass, semiconductor materials such as Si, etc. can be used. Note that in the case of the substrate 10 made of a semiconductor material such as Si, an insulating layer covering the main surface 101 of the substrate is provided. As the insulating layer, for example, an oxide film such as SiO ₂ or a resin film such as polyimide resin is used.

The wiring section 20 has a main surface wiring 22 and a through wiring 25.
The main surface wiring 22 is formed on the main surface 101 of the substrate 10 . The upper surface 221 of the main surface wiring 22 faces in the same direction as the main substrate surface 101 of the substrate 10 . The lower surface 222 of the main surface wiring 22 faces the same direction as the substrate back surface 102 of the substrate 10 and faces the substrate main surface 101 of the substrate 10 . The side surface 223 of the main surface wiring 22 faces in the same direction as the substrate side surface 103 of the substrate 10 .

The protective film 30 is formed on the main substrate surface 101 of the substrate 10 . The protective film 30 covers the substrate main surface 101 and the main surface wiring 22.
The sealing resin 80 is formed to be in contact with the upper surface 301 of the protective film 30 and to cover the first element 60 and the second element 70. The sealing resin 80 has a plurality of through holes 81 that penetrate the sealing resin 80 in the thickness direction Z. The through hole 81 extends from the resin upper surface 801 of the sealing resin 80 to the upper surface 221 of the main surface wiring 22. The shape of the through hole 81 is, for example, rectangular when viewed from the thickness direction Z. Note that the shape of the through hole 81 may be any shape such as a circular shape or a polygonal shape when viewed from the thickness direction Z.

The through wiring 25 is arranged in each through hole 81. The through wiring 25 has an upper surface 251, a lower surface 252, and a plurality of side surfaces 253. The upper surface 251 of the through wiring 25 is flush with the resin upper surface 801 of the sealing resin 80 . The upper surface 251 of the through wiring 25 is exposed from the sealing resin 80. The lower surface 252 of the through wiring 25 is in contact with the upper surface 221 of the main surface wiring 22 . A side surface 253 of the through wiring 25 is in contact with an inner wall surface 813 of the through hole 81 of the sealing resin 80 .

The external conductive film 90 is formed to cover the upper surface 251 of the through wiring 25 exposed on the resin upper surface 801 of the sealing resin 80 . The external conductive film 90 becomes an external connection terminal of the semiconductor device A2.

(effect)
This semiconductor device A2 is mounted on a mounting board with the external conductive film 90 facing the mounting board, that is, with the element main surface 601 of the first element 60 facing the opposite direction to the mounting board. In this semiconductor device A2 as well, effects similar to those of the first embodiment can be obtained.

In the semiconductor device A2 of this embodiment, the substrate 10 may have a thickness necessary to support the first element 60 and the second element 70. Therefore, in this semiconductor device A2, the thickness of the substrate 10 can be made thinner than the substrate 10 of the semiconductor device A1 of the first embodiment, so that the semiconductor device A2 can be made thinner.

As described above, according to this embodiment, the following effects are achieved.
The semiconductor device A2 of (2-1) is mounted on the mounting board with the external conductive film 90 facing the mounting board, that is, with the element main surface 601 of the first element 60 facing in the opposite direction to the mounting board. be done. In this semiconductor device A2 as well, effects similar to those of the first embodiment can be obtained.

(2-2) In the semiconductor device A2, since the thickness of the substrate 10 can be made thinner than the substrate 10 of the semiconductor device A1 of the first embodiment, the semiconductor device A2 can be made thinner.
(Example of change)
This embodiment can be modified and implemented as follows.

- In contrast to the semiconductor device A1 of the first embodiment, the semiconductor device A11 shown in FIG. ing.

- The semiconductor device A12 shown in FIG. 12 has an electrode bump 95 in contact with the lower surface 212 of the through wiring 21, unlike the semiconductor device A1 of the first embodiment. The shape of the electrode bump 95 is, for example, semicircular when viewed from a direction perpendicular to the thickness direction Z. In addition, the shape of the electrode bump 95 can also be made into arbitrary shapes, such as a trapezoid shape, when seen from the direction orthogonal to the thickness direction Z. The electrode bumps 95 are made of, for example, Sn or an alloy containing Sn. This alloy is, for example, a Sn-Ag alloy, a Sn-Sb alloy, or the like.

- In the semiconductor device A13 shown in FIG. 13, the through wiring 21 extends to the substrate side surface 103y of the substrate 10, unlike the semiconductor device A1 of the first embodiment. In other words, the side surface 214 of the through wiring 21 is flush with the substrate side surface 103y of the substrate 10. That is, the lower surface 212 of the through wiring 21 is exposed on the substrate back surface 102 of the substrate 10, and the side surface 214 of the through wiring 21 is exposed on the substrate side surface 103y of the substrate 10.

The external conductive film 90 is formed to cover the through wiring 21 exposed from the substrate 10. The external conductive film 90 includes a lower conductive film 91 that covers the lower surface 212 of the through wiring 21 and a side conductive film 92 that covers the side surface 214 of the through wiring 21 . The external conductive film 90 having the lower surface conductive film 91 and the side conductive film 92 serves as an external connection terminal of the semiconductor device A13, similar to the external conductive film 90 of the first embodiment. The external conductive film 90 is composed of, for example, a plurality of metal layers stacked on each other. Examples of the metal layer include a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. Note that the material of the external conductive film 90 is not limited, but may be composed of, for example, a stack of a Ni layer and an Au layer, or may be made of Sn.

In this semiconductor device A13, when mounted on a mounting board, the solder that connects the external conductive film 90 to the connection pad of the mounting board is interposed between the lower surface side conductive film 91 and the connection pad, and the solder connects to the side surface side conductive film 92. It also sticks. In other words, the solder that has become a liquid phase through the reflow process creeps up the side conductive film 92 and forms a solder fillet between the side conductive film 92 and the connection pad. In the semiconductor device A13 of this modification, solder fillets are easily formed. This solder fillet increases the solder joint area and further increases the connection strength. Moreover, the soldering state of the semiconductor device A13 can be confirmed from the outside by the solder fillet.

- The protective film 30 may be omitted.
- The protective film 30 may have a frame shape surrounding each of the first joint portion 40 and the second joint portion 50.

- When forming the conductive layers 41, 51 and plating layers 42, 52 of the first joint 40 and the second joint 50, a plating mask covering the main surface wiring 22 is used to form the conductive layers 41, 51 and the plating layers 42, 52. The plating mask may be removed after the formation of the plating mask.
(Additional note 1)
a substrate having a main surface and a back surface facing opposite to each other in the thickness direction;
main surface wiring provided on the main surface of the substrate;
a first element having an element main surface facing the substrate main surface, and a first element electrode provided on the element main surface;
a second element having a lower surface facing the main surface of the substrate and a second element electrode provided on the lower surface;
a first joint portion that joins the main surface wiring and the first element;
a second joint portion that joins the main surface wiring and the second element;
Equipped with
The first joint portion includes a first solder layer interposed between the first element and the main surface wiring,
The second joint portion includes a second solder layer interposed between the second element and the main surface wiring,
The thickness of the first solder layer is thicker than the thickness of the second solder layer.
Semiconductor equipment.
(Additional note 2)
The first element has an element main surface facing the substrate main surface, and a first element electrode on the element main surface,
the first solder layer is connected to the first element electrode;
The semiconductor device according to supplementary note 1.
(Additional note 3)
The second element has a lower surface facing the main surface of the substrate, and a second element electrode on the lower surface,
the second solder layer is connected to the second element;
The semiconductor device according to supplementary note 1 or supplementary note 2.
(Additional note 4)
The first solder layer is formed by joining a substrate-side solder layer provided on the substrate side and an element-side solder layer provided on the first element side,
The second solder layer is configured by connecting a substrate-side solder layer provided on the substrate side to the second element.
The semiconductor device according to any one of Supplementary notes 1 to 3.
(Appendix 5)
The first joint portion and the second joint portion each include a conductive layer provided on the main surface wiring and a plating layer provided on the conductive layer,
The first solder layer is provided on the plating layer of the first joint,
The second solder layer is provided on the plating layer of the second joint,
The semiconductor device according to any one of Supplementary Notes 1 to 4.
(Appendix 6)
The upper surface of the plating layer of the first joint portion has the same size as the first element electrode when viewed from the thickness direction,
The semiconductor device according to appendix 5.
(Appendix 7)
The first solder layer is formed in a columnar shape extending in the thickness direction.
The semiconductor device according to any one of Supplementary notes 1 to 6.
(Appendix 8)
The upper surface of the plating layer of the second joint portion is larger than the second element electrode when viewed from the thickness direction.
The semiconductor device according to supplementary note 5 or supplementary note 6.
(Appendix 9)
The second solder layer has a lower surface facing the main surface wiring and an upper surface facing the second element, and the size of the lower surface when viewed from the thickness direction is the same as the size of the upper surface. bigger than that,
The semiconductor device according to any one of Supplementary Notes 1 to 8.
(Appendix 10)
The semiconductor device according to appendix 9, wherein the second solder layer has a side surface sandwiched between the upper surface and the lower surface, and the side surface is curved so as to be recessed toward the inside of the second solder layer. .
(Appendix 11)
The first joint portion and the second joint portion each include a conductive layer provided on the main surface wiring and a plating layer provided on the conductive layer,
The thickness of the conductive layer of the first joint portion and the thickness of the conductive layer of the second joint portion are equal to each other,
The thickness of the plating layer of the first joint portion and the thickness of the plating layer of the second joint portion are equal to each other,
The semiconductor device according to any one of Supplementary Notes 1 to 10.
(Appendix 12)
The conductive layer has an upper surface facing the same side as the main surface of the substrate, a lower surface connected to the main surface wiring, and a side surface sandwiched between the upper surface and the lower surface, and the side surface is closer to the bottom surface than the bottom surface. is also inclined so that the upper surface becomes larger,
The semiconductor device according to appendix 11.
(Appendix 13)
The plating layer has an upper surface facing the same side as the main surface of the substrate, a lower surface connected to the conductive layer, and a side surface sandwiched between the upper surface and the lower surface, and the side surface is larger than the lower surface. the upper surface is inclined to become larger;
The semiconductor device according to supplementary note 11 or supplementary note 12.
(Appendix 14)
The conductive layer is made of Cu,
The plating layer is made of Ni.
The semiconductor device according to any one of attachments 11 to 13.
(Appendix 15)
The first element is an LSI in which components are formed on the side of the element main surface opposite to the substrate main surface,
The second element is an element connected to the component,
The semiconductor device according to any one of Supplementary notes 1 to 14.
(Appendix 16)
The substrate has a through hole that penetrates the substrate from the main surface of the substrate to the back surface of the substrate,
The semiconductor device has a through wiring provided in the through hole and connected to the main surface wiring.
The semiconductor device according to any one of Supplementary notes 1 to 15.
(Appendix 17)
The through wiring has an exposed surface exposed from the substrate,
The semiconductor device further includes an external conductive film that covers the exposed surface of the through wiring.
The semiconductor device according to appendix 16.
(Appendix 18)
comprising a sealing resin that covers the first element and the second element;
The semiconductor device according to any one of Supplementary notes 1 to 15.
(Appendix 19)
The sealing resin has an upper surface facing the same side as the main surface of the substrate, and a through hole penetrating from the upper surface of the main surface wiring to the upper surface of the sealing resin,
The semiconductor device has a through wiring provided in the through hole and connected to the main surface wiring.
The semiconductor device according to appendix 18.
(Additional note 20)
The through wiring has an exposed surface exposed from the sealing resin,
The semiconductor device further includes an external conductive film that covers the exposed surface of the through wiring.
The semiconductor device according to appendix 19.
(Additional note 21)
forming a first board-side solder layer and a second board-side solder layer on a base material on which main surface wiring is formed;
Temporarily fixing an element-side solder layer connected to a first element electrode of a first element to the first substrate-side solder layer, and temporarily fixing a second element electrode of a second element to the second substrate-side solder layer. and,
By reflow processing, a first joint portion including a first solder layer constituted of the first substrate side solder layer and the element side solder layer and joining the main surface wiring and the first element; forming a second joint portion including a second solder layer configured from a substrate-side solder layer and joining the main surface wiring and the second element;
A method for manufacturing a semiconductor device comprising:
(Additional note 22)
forming a first conductive layer and a second conductive layer on the main surface wiring;
forming a first plating layer on the first conductive layer and forming a second plating layer on the second conductive layer;
Equipped with
In the step of forming the first substrate-side solder layer and the second substrate-side solder layer, the first substrate-side solder layer is formed on the first plating layer, and the first substrate-side solder layer is formed on the second plating layer. forming a second board side solder layer;
The method for manufacturing a semiconductor device according to appendix 21.

A1, A2, A11 to A13 Semiconductor device 10 Substrate 11 Through hole 20 Wiring portion 21 Through wiring 22 Main surface wiring 22a Metal layer 22b Conductive layer 23 First wiring 24 Second wiring 25 Through wiring 30 Protective film 31 First opening 32 Second opening 40 First joint 41 Conductive layer (first conductive layer)
42 Plating layer (first plating layer)
43 Solder layer (first solder layer)
44 Board side solder layer (first board side solder layer)
50 Second joint portion 51 Conductive layer (second conductive layer)
52 Plating layer (second plating layer)
53 Board side solder layer (second solder layer, second board side solder layer)
60 First element 60T power transistor 61 Element substrate 62 Electrode pad 63 Insulating film 64 Protection 65 Element electrode (first element electrode)
65a Metal layer 65b Conductive layer 65c Barrier layer 66 Element side solder layer 70 Second element 71 Element electrode (second element electrode)
80 Sealing resin 81 Through hole 90 External conductive film 91 Lower surface side conductive film 92 Side surface side conductive film 95 Electrode bump 101 Main surface of substrate 102 Back surface of substrate 103 Side surface of substrate 103x Side surface of substrate 103y Side surface of substrate 113 Inner wall surface 211 Top surface 212 Bottom surface 213 Side surface 214 Side surface 221 Top surface 222 Bottom surface 223 Side surface 251 Top surface 252 Bottom surface 253 Side surface 301 Top surface 302 Bottom surface 303 Side surface 313 Inside surface 323 Inside surface 411 Top surface 412 Bottom surface 413 Side surface 421 Top surface 422 Bottom surface 423 Side surface 431 Top surface 432 Bottom surface 433 Side surface 433a First side surface 433b Second side Side surface 511 Top surface 512 Bottom surface 513 Side surface 521 Top surface 522 Bottom surface 523 Side surface 531 Top surface 532 Bottom surface 533 Side surface 601 Element main surface 602 Element back surface 603 Element side surface 603x Board side surface 603y Board side surface 652 Bottom surface 701 Top surface 702 Bottom Surface 703 Side surface 801 Resin top surface 803 Resin side surface 813 Inner wall surface S10 Base material S101 Top surface X First direction Y Second direction Z Thickness direction

Claims (18)

a substrate having a main surface and a back surface facing opposite to each other in the thickness direction;
main surface wiring provided on the main surface of the substrate;
a first element having an element main surface facing the substrate main surface, and a first element electrode provided on the element main surface;
a second element having a lower surface facing the main surface of the substrate and a second element electrode provided on the lower surface;
a first opening that covers the main surface wiring and exposes the main surface wiring at a position corresponding to the first element electrode; and a second opening that exposes the main surface wiring at a position corresponding to the second element electrode. A protective film having electrical insulation properties,
a first joint portion that joins the main surface wiring exposed by the first opening and the first element electrode ;
a second joint portion that joins the main surface wiring exposed by the second opening and the second element electrode ;
Equipped with
The first joint portion includes a first solder layer interposed between the first element electrode and the main surface wiring exposed by the first opening ,
The second joint portion includes a second solder layer interposed between the second element electrode and the main surface wiring exposed by the second opening ,
Viewed from the thickness direction of the substrate, the area of the first element electrode is smaller than the area of the second element electrode,
When viewed from the thickness direction of the substrate, the opening area of the first opening is smaller than the opening area of the second opening,
The thickness of the first solder layer is thicker than the thickness of the second solder layer,
The second element has two second element electrodes on the lower surface,
The two second element electrodes are arranged at both ends of the second element in the length direction,
The protective film includes two second openings corresponding to the two second element electrodes,
The two second openings are larger than the two second element electrodes when viewed from the thickness direction of the substrate, and are arranged closer to the inside of the second element with respect to the two second element electrodes. There is,
Semiconductor equipment. The first solder layer is formed by joining a substrate-side solder layer provided on the substrate side and an element-side solder layer provided on the first element side,
The second solder layer is configured by connecting a substrate-side solder layer provided on the substrate side to the second element.
The semiconductor device according to claim 1 . The first joint portion and the second joint portion each include a conductive layer provided on the main surface wiring and a plating layer provided on the conductive layer,
The first solder layer is provided on the plating layer of the first joint,
The second solder layer is provided on the plating layer of the second joint,
The semiconductor device according to claim 1 or claim 2 . The upper surface of the plating layer of the first joint portion has the same size as the first element electrode when viewed from the thickness direction,
The semiconductor device according to claim 3 . The first solder layer is formed in a columnar shape extending in the thickness direction.
The semiconductor device according to any one of claims 1 to 4 . The upper surface of the plating layer of the second joint portion is larger than the second element electrode when viewed from the thickness direction.
The semiconductor device according to claim 3 or 4 . The second solder layer has a lower surface facing the main surface wiring and an upper surface facing the second element, and the size of the lower surface when viewed from the thickness direction is equal to the upper surface. larger than the size of
The semiconductor device according to any one of claims 1 to 6 . 8. The semiconductor according to claim 7 , wherein the second solder layer has a side surface sandwiched between the upper surface and the lower surface, and the side surface is curved so as to be recessed toward the inside of the second solder layer. Device. The first joint portion and the second joint portion each include a conductive layer provided on the main surface wiring and a plating layer provided on the conductive layer,
The thickness of the conductive layer of the first joint portion and the thickness of the conductive layer of the second joint portion are equal to each other,
The thickness of the plating layer of the first joint portion and the thickness of the plating layer of the second joint portion are equal to each other,
The semiconductor device according to any one of claims 1 to 8 . The conductive layer has an upper surface facing the same side as the main surface of the substrate, a lower surface connected to the main surface wiring, and a side surface sandwiched between the upper surface and the lower surface, and the side surface is closer to the bottom surface than the bottom surface. is also inclined so that the upper surface becomes larger,
The semiconductor device according to claim 9 . The plating layer has an upper surface facing the same side as the main surface of the substrate, a lower surface connected to the conductive layer, and a side surface sandwiched between the upper surface and the lower surface, and the side surface is larger than the lower surface. the upper surface is inclined to become larger;
The semiconductor device according to claim 9 or claim 10 . The conductive layer is made of Cu,
The plating layer is made of Ni.
The semiconductor device according to any one of claims 9 to 11 . The first element is an LSI in which components are formed on the side of the element main surface opposite to the substrate main surface,
The second element is an element connected to the component,
The semiconductor device according to any one of claims 1 to 12 . The substrate has a through hole that penetrates the substrate from the main surface of the substrate to the back surface of the substrate,
The semiconductor device has a through wiring provided in the through hole and connected to the main surface wiring.
The semiconductor device according to any one of claims 1 to 13 . The through wiring has an exposed surface exposed from the substrate,
The semiconductor device further includes an external conductive film that covers the exposed surface of the through wiring.
The semiconductor device according to claim 14 . comprising a sealing resin that covers the first element and the second element;
The semiconductor device according to any one of claims 1 to 13 . The sealing resin has an upper surface facing the same side as the main surface of the substrate, and a through hole penetrating from the upper surface of the main surface wiring to the upper surface of the sealing resin,
The semiconductor device has a through wiring provided in the through hole and connected to the main surface wiring.
The semiconductor device according to claim 16 . The through wiring has an exposed surface exposed from the sealing resin,
The semiconductor device further includes an external conductive film that covers the exposed surface of the through wiring.
The semiconductor device according to claim 17 .