JP2018088505A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of further thinning and improving reliability, and a manufacturing method for the same.SOLUTION: There are provided: a first semiconductor element 12 which has an element main surface 121 and an element back surface 122 facing opposite from each other in a thickness direction Z; a first columnar body 13 extending from the element main surface 121 along the thickness direction Z; a wiring layer 21 conducting to the first columnar body 13; a second semiconductor element 23 mounted on the wiring layer 21; a second columnar body 22 which is conductive to the wiring layer 21, is arranged away from the first columnar body 13 in a planar view, and extends along the thickness direction Z; and a sealing resin 3 which covers the first semiconductor element 12, the first columnar body 13, the wiring layer 21, and the second semiconductor element 23. The second columnar body 22 has a side surface 221 along the thickness direction Z and an end surface 222 crossing the side surface 221. The side surface 221 is covered with the sealing resin 3 and the end surface 222 is exposed from the sealing resin 3.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a package-on-package type semiconductor device in which a plurality of semiconductor elements are stacked and mounted, and a method for manufacturing the same.

  With recent downsizing and higher functionality of electronic devices, downsizing of semiconductor devices and advancement of functions are being promoted. One of such semiconductor devices is a package on package (POP) type semiconductor device in which a plurality of semiconductor elements are stacked and mounted.

  Here, Patent Document 1 discloses a package-on-package semiconductor device. The semiconductor device includes a first semiconductor element mounted on a first substrate, a second semiconductor element mounted on a second substrate located above the first substrate, and a gap between the first substrate and the second substrate. With intervening solder balls. The first substrate and the second substrate are electrically connected to each other through solder balls. A solder ball for connecting the semiconductor device to the circuit board of the electronic device is separately arranged on the lower surface of the first substrate.

  The semiconductor device disclosed in Patent Document 1 includes a first substrate on which a first semiconductor element is mounted and a second substrate on which a second semiconductor element is mounted. According to such a configuration, when the thickness of the semiconductor device is reduced, the presence of these substrates prevents the length from being reduced, and it is difficult to further reduce the thickness of the semiconductor device. In the semiconductor device, the solder ball interposed between the first substrate and the second substrate is exposed to the outside. According to such a configuration, when the semiconductor device is mounted on the circuit board, the solder ball is melted by thermal shock, and there is a possibility that a failure occurs in the conduction path inside the semiconductor device.

JP 2010-80609 A

  In view of the above-described circumstances, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that can further reduce the thickness and improve the reliability.

  The semiconductor device provided by the first aspect of the present invention includes a first semiconductor element having an element main surface and an element back surface facing opposite to each other in the thickness direction, and the thickness of the first semiconductor element from the element main surface. A first columnar body extending along the vertical direction, a wiring layer conducting to the first columnar body, a second semiconductor element mounted on the wiring layer, conducting to the wiring layer, and in plan view A second columnar body that is disposed apart from the first columnar body and extends along a thickness direction of the first semiconductor element; the first semiconductor element; the first columnar body; and the wiring. And a sealing resin that covers the layer and the second semiconductor element, and the second columnar body has a side surface along the thickness direction of the first semiconductor element and an end surface intersecting the side surface, The side surface is covered with the sealing resin, and the end surface is the sealing resin. It is characterized in that it is al exposed.

  In the embodiment of the present invention, preferably, the sealing resin includes a resin back surface facing in the same direction as the element back surface of the first semiconductor element, and a first bonding surface facing away from the resin back surface. 1 sealing resin; a resin main surface facing in the same direction as the element main surface of the first semiconductor element; and a second bonding surface facing the side opposite to the resin main surface and in contact with the first bonding surface The first sealing resin covers the first semiconductor element and the first columnar body, and the second sealing resin includes the wiring layer and the second sealing resin. The semiconductor element is covered.

  In the practice of the present invention, preferably, both the first sealing resin and the second sealing resin are synthetic resins mainly composed of an epoxy resin.

  In the practice of the present invention, preferably, the first sealing resin is provided with a protective layer that is disposed in contact with the resin back surface and is an insulator.

  In the practice of the present invention, the protective layer is preferably made of polyimide.

  In the embodiment of the present invention, preferably, an adhesive layer is provided between the protective layer and the first semiconductor element.

  In the embodiment of the present invention, preferably, the side surface of the second columnar body is covered with the second sealing resin, and the end surface of the second columnar body is exposed from the resin main surface of the second sealing resin. ing.

  In the embodiment of the present invention, preferably, the side surface of the second columnar body is covered with the first sealing resin, and the end surface of the second columnar body is exposed from an opening formed in the protective layer. .

  Preferably, in the implementation of the present invention, the wiring layer is composed of a base layer and a plating layer laminated on each other, and the base layer is provided on the first joint surface of the first columnar body and the first sealing resin. The thickness is set smaller than the plating layer.

  Preferably, in the implementation of the present invention, the base layer includes a first base layer in contact with the first columnar body and the first bonding surface of the first sealing resin, and the first base layer and the plating layer. The second underlayer and the plating layer are both made of the same material.

  In the practice of the present invention, preferably, the second underlayer and the plating layer are both made of Cu.

  In the practice of the present invention, preferably, the first underlayer is made of Ti.

  In the practice of the present invention, the second columnar body is preferably made of the same material as the second underlayer and the plating layer.

  Preferably, the present invention includes a bonding layer interposed between the second semiconductor element and the wiring layer.

  In the practice of the present invention, the bonding layer is preferably composed of an Ni layer and an alloy layer containing Sn stacked on each other.

  In the practice of the present invention, a frame-like body that surrounds the bonding layer and is an insulator is preferably provided.

  In the practice of the present invention, the frame body is preferably made of polyimide.

  In the practice of the present invention, a pad layer that is in contact with the end face of the second columnar body and exposed to the outside is preferably provided.

  In the practice of the present invention, the pad layer is preferably composed of a Ni layer, a Pd layer, and an Au layer stacked on each other.

  In the practice of the present invention, a passive element mounted on the wiring layer is preferably provided.

  A manufacturing method of a semiconductor device provided by the second aspect of the present invention has an element main surface and an element back surface facing opposite sides in the thickness direction, and extends from the element main surface along the thickness direction. A step of preparing a first semiconductor element on which a first columnar body to be formed is formed; a step of mounting the first semiconductor element on the base so that the back surface of the element faces the base; and the first Forming a first sealing resin covering the semiconductor element and the first columnar body; forming a wiring layer in contact with the first columnar body and the first sealing resin; and a second semiconductor in the wiring layer A step of mounting an element, a step of forming a second sealing resin in contact with the first sealing resin and covering the wiring layer and the second semiconductor element, and a step of removing the substrate. In the step of forming the wiring layer, the wiring layer is formed. The step of forming includes a step of forming a second columnar body extending along the thickness direction of the base material. In the step of forming the second sealing resin, the second columnar body includes the base. An end face that intersects the thickness direction of the material and is exposed from the second sealing resin is formed.

  In the implementation of the present invention, preferably, the end surface of the second columnar body exposed from the second sealing resin is in contact between the step of forming the second sealing resin and the step of removing the base material. A step of forming the pad layer by electroless plating.

  In the implementation of the present invention, preferably, between the step of preparing the first semiconductor element and the step of mounting the first semiconductor element, the base material is covered, and the back surface of the first semiconductor element is disposed on the element back surface. A step of forming an opposing protective layer by coating.

  A manufacturing method of a semiconductor device provided by the third aspect of the present invention has an element main surface and an element back surface facing opposite sides in the thickness direction, and extends from the element main surface along the thickness direction. A step of preparing a first semiconductor element on which a first columnar body to be formed is formed; a step of forming a protective layer covering the base material and having an opening; and from the opening to the thickness direction of the base Forming a second columnar body extending along the substrate, mounting the first semiconductor element on the protective layer so that the back surface of the element faces the protective layer, and the first Forming a first sealing resin covering the semiconductor element, the first columnar body, and the second columnar body; and a wiring layer in contact with the first columnar body, the second columnar body, and the first sealing resin. Forming and mounting the second semiconductor element on the wiring layer A step of forming a second sealing resin in contact with the first sealing resin and covering the wiring layer and the second semiconductor element, and a step of removing the base material, and removing the base material The step of performing is characterized in that an end surface that intersects the thickness direction of the base material and is exposed from the opening of the protective layer appears in the second columnar body.

  In the implementation of the present invention, preferably, after the step of removing the base material, a step of forming a pad layer in contact with the end face of the second columnar body exposed from the opening of the protective layer by electroless plating is provided. .

  Preferably, in the embodiment of the present invention, in the step of forming the protective layer, a columnar base layer that is interposed between the base material and the protective layer and exposed from the opening of the protective layer is formed by a sputtering method. Forming.

  In the practice of the present invention, preferably, in the step of forming the protective layer, the protective layer is formed by photolithography.

  In the implementation of the present invention, preferably, in the step of forming the second columnar body, the second columnar body is formed by electrolytic plating.

  In the practice of the present invention, preferably, in the step of removing the base material, the columnar base layer is removed together with the base material.

  In the embodiment of the present invention, preferably, in the step of forming the wiring layer, a step of forming a wiring base layer in contact with the first columnar body and the first sealing resin by a sputtering method, and plating in contact with the wiring base layer Forming a layer by electrolytic plating.

  Preferably, in the embodiment of the present invention, in the step of forming the wiring layer, after forming the plating layer, a step of forming a bonding layer in contact with the plating layer and mounting the second semiconductor element by electrolytic plating Including.

  Preferably, in the embodiment of the present invention, the step of forming the wiring layer includes a step of forming a frame-like body in contact with the plating layer and surrounding the periphery of the bonding layer by photolithography.

  In the embodiment of the present invention, preferably, in the step of mounting the second semiconductor element, a passive element is mounted on the wiring layer together with the second semiconductor element.

  A semiconductor device according to the present invention includes a first semiconductor element, a first columnar body formed in the first semiconductor element, a wiring layer conducting to the first columnar body, a second semiconductor element mounted on the wiring layer, And a sealing resin that covers the first semiconductor element, the first columnar body, the wiring layer, and the second semiconductor element. In addition, the semiconductor device includes a second columnar body that has a side surface and an end surface, is electrically connected to the wiring layer, and is spaced apart from the first columnar body in plan view, and the side surface is covered with the sealing resin. The end surface is exposed from the sealing resin. By adopting such a configuration, a substrate on which each of the first semiconductor element and the second semiconductor element is mounted becomes unnecessary, and the apparatus can be further reduced in thickness. In addition, the first columnar body and the second columnar body, which are conductive paths in the thickness direction in the semiconductor device, are all covered with the sealing resin except for the end surface of the second columnar body. There is no possibility of a failure occurring in the conductive path inside the semiconductor device. Therefore, according to the semiconductor device, it is possible to further reduce the thickness and improve the reliability.

  According to the semiconductor device manufacturing method of the present invention, the step of mounting the first semiconductor element on the base material, the step of forming the first sealing resin covering the first columnar body, and the first sealing resin are in contact with each other. And the process of forming the wiring layer which mounts a 2nd semiconductor element, and the process of peeling a base material are provided. By including such a process, the semiconductor device can be dispensed with a substrate on which each of the first semiconductor element and the second semiconductor element is mounted. Moreover, according to the manufacturing method of the semiconductor device, a step of forming the second sealing resin that covers the second semiconductor element and the second columnar body is provided in accordance with the above steps. By providing such a process, the semiconductor device can have a structure in which both the first columnar body and the second columnar body are covered with the sealing resin.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention (through a second sealing resin). 2 is a plan view of the semiconductor device shown in FIG. 1 (through a second sealing resin). FIG. It is the top view which omitted the 2nd semiconductor element, the passive element, and the solder layer from FIG. FIG. 2 is a plan view of a protective layer, a first semiconductor element, a first columnar body, and an adhesive layer of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which follows the VI-VI line of FIG. It is sectional drawing which follows the VII-VII line of FIG. It is the elements on larger scale of FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. FIG. 6 is a plan view of a semiconductor device according to a second embodiment of the present invention (through a second sealing resin). FIG. 30 is a bottom view of the semiconductor device shown in FIG. 29. FIG. 30 is a plan view of a protective layer, a first semiconductor element, a first columnar body, and an adhesive layer of the semiconductor device shown in FIG. 29. It is sectional drawing which follows the XXXII-XXXII line | wire of FIG. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29.

  A mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
A semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. The semiconductor device A10 includes a protective layer 11, a first semiconductor element 12, a first columnar body 13, an adhesive layer 14, a wiring layer 21, a second columnar body 22, a second semiconductor element 23, a bonding layer 24, a frame-shaped body 25, A passive element 26, a sealing resin 3 and a pad layer 4 are provided. The sealing resin 3 includes a first sealing resin 31 and a second sealing resin 32.

  FIG. 1 is a perspective view of the semiconductor device A10 and transmits the second sealing resin 32 for convenience of understanding. FIG. 2 is a plan view of the semiconductor device A10 and transmits the second sealing resin 32 for convenience of understanding. FIG. 3 is a plan view of the semiconductor device A10 from which the second semiconductor element 23, the passive element 26, and the solder layer 261 are omitted from FIG. 4 is a plan view showing the protective layer 11, the first semiconductor element 12, the first columnar body 13, and the adhesive layer 14 of the semiconductor device A10. FIG. 5 is a cross-sectional view taken along line VV in FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 2 (the chain line shown in FIG. 2). 7 is a cross-sectional view taken along line VII-VII in FIG. FIG. 8 is a partially enlarged view of FIG. In addition, the external shape of the 2nd sealing resin 32 which permeate | transmitted in FIG. 1 is shown with the imaginary line (two-dot chain line).

  The semiconductor device A10 shown in these drawings is of a resin package type that is surface-mounted on circuit boards of various electronic devices. As shown in FIGS. 1 and 2, the shape of the first semiconductor element 12 of the semiconductor device A <b> 10 in the thickness direction Z (hereinafter referred to as “plan view”) is a rectangular shape. Here, for convenience of explanation, the long side direction of the semiconductor device A10 that is perpendicular to the thickness direction Z of the first semiconductor element 12 is referred to as a first direction X. The short side direction of the semiconductor device A10 that is perpendicular to the thickness direction Z and the first direction X of the first semiconductor element 12 is referred to as a second direction Y.

  As shown in FIGS. 1 and 4 to 7, the protective layer 11 is disposed in contact with a resin back surface 311 of a first sealing resin 31 described later, and is an insulating member. In the present embodiment, the first semiconductor element 12 is mounted on the protective layer 11 via the adhesive layer 14. The protective layer 11 is made of a synthetic resin having electrical insulation, and is made of polyimide in this embodiment. Note that the protective layer 11 may be omitted depending on the properties of the first semiconductor element 12.

  The first semiconductor element 12 is a semiconductor element serving as a functional center of the semiconductor device A10, and is, for example, an integrated circuit (IC). The first semiconductor element 12 can employ various semiconductor elements according to functions required for the semiconductor device A10. As shown in FIGS. 5 to 7, the first semiconductor element 12 has an element main surface 121 and an element back surface 122 that face opposite sides in the thickness direction Z. The element main surface 121 is an upper surface of the first semiconductor element 12 shown in FIGS. A plurality of first columnar bodies 13 are formed on the element main surface 121. The element back surface 122 is a bottom surface of the first semiconductor element 12 shown in FIGS. The element back surface 122 faces the protective layer 11 and is in contact with the adhesive layer 14.

  As shown in FIGS. 1 to 8, the first columnar body 13 is a conductive member that extends from the element main surface 121 of the first semiconductor element 12 along the thickness direction Z of the first semiconductor element 12. The first columnar body 13 is made of Cu, for example. The 1st columnar body 13 concerning this embodiment is comprised by two or more. Each of the first columnar bodies 13 has a cylindrical shape and the same shape. The first columnar body 13 is electrically connected to the wiring layer 21 and a circuit (not shown) formed in a portion including the element main surface 121 of the first semiconductor element 12. The first columnar body 13 has a top surface 131 that intersects the thickness direction Z of the first semiconductor element 12 and faces in the same direction as the element main surface 121 of the first semiconductor element 12. The shape of the top surface 131 according to the present embodiment is a circular shape. The top surface 131 is in contact with the wiring layer 21.

  The adhesive layer 14 is a member that is interposed between the protective layer 11 and the element back surface 122 of the first semiconductor element 12 as shown in FIGS. The first semiconductor element 12 is mounted on the protective layer 11 by being bonded to the protective layer 11 by the adhesive layer 14. The adhesive layer 14 is composed of a film adhesive or a paste adhesive. The film adhesive is, for example, a die attach film (DAF). The paste adhesive is, for example, a conductive paste such as an Ag paste or an electrically insulating paste mainly composed of polyimide.

  As shown in FIGS. 1 to 3 and FIGS. 5 to 8, the wiring layer 21 is a conductive member that conducts to the first columnar body 13. The wiring layer 21 according to the present embodiment is disposed in contact with a first bonding surface 312 of the first sealing resin 31 described later. The wiring layer 21 includes a base layer 211 and a plating layer 212 that are stacked on each other. The foundation layer 211 is in contact with the top surface 131 of the first columnar body 13 and the first bonding surface 312 of the first sealing resin 31 and is covered with the plating layer 212. The plating layer 212 is covered with the second sealing resin 32 except for portions that are in contact with the second semiconductor element 23, the bonding layer 24, and the frame body 25. In this embodiment, the thickness of the foundation layer 211 is 200 to 300 nm, and the thickness of the plating layer 212 is 3 to 10 μm. For this reason, the base layer 211 is set to be thinner than the plating layer 212.

  As shown in FIG. 8, the base layer 211 includes a first base layer 211 a in contact with the top surface 131 of the first columnar body 13 and the first bonding surface 312 of the first sealing resin 31, the first base layer 211 a, and plating. A second underlayer 211b interposed between the layer 212 and the layer 212 is included. In the present embodiment, the first base layer 211a is made of Ti, and the second base layer 211b is made of Cu. The plating layer 212 is made of Cu. For this reason, both the 2nd base layer 211b and the plating layer 212 are comprised from the same material.

  As shown in FIGS. 1 to 3 and FIGS. 5 to 7, the second columnar body 22 is electrically connected to the wiring layer 21 and is spaced apart from the first columnar body 13 in plan view. 1 is a conductive member extending along the thickness direction Z of the semiconductor element 12. The second columnar body 22 is made of the same material as the second base layer 211 b and the plating layer 212 of the wiring layer 21. For this reason, the 2nd columnar body 22 concerning this embodiment is comprised from Cu. Moreover, the 2nd columnar body 22 concerning this embodiment is comprised by multiple similarly to the 1st columnar body 13. FIG. Each of the second columnar bodies 22 has a prismatic shape and the same shape.

  As shown in FIGS. 3 and 5 to 7, the second columnar body 22 has a side surface 221 along the thickness direction Z of the first semiconductor element 12 and an end surface 222 intersecting the side surface 221. The end surface 222 according to the present embodiment is a surface facing in the same direction as the element main surface 121 of the first semiconductor element 12. The side surface 221 is covered with the sealing resin 3. In the present embodiment, the side surface 221 is covered with the second sealing resin 32. The end surface 222 is exposed from the sealing resin 3. In the present embodiment, the end surface 222 is exposed from the resin main surface 321 of the second sealing resin 32 described later. For this reason, in the present embodiment, the second columnar body 22 is arranged in contact with the plating layer 212 of the wiring layer 21. Further, the end surface 222 according to the present embodiment is rectangular. The end surface 222 is in contact with the pad layer 4.

  The second semiconductor element 23 is a semiconductor element that is mounted on the wiring layer 21 and serves as a functional center of the semiconductor device A10 together with the first semiconductor element 12. The second semiconductor element 23 is, for example, an integrated circuit, and various semiconductor elements can be adopted according to the functions required for the semiconductor device A10 as with the first semiconductor element 12. As shown in FIGS. 1 and 2, the second semiconductor element 23 according to the present embodiment is a so-called flip chip type semiconductor element. A plurality of electrode bumps 231 are arranged on the lower surface of the second semiconductor element 23 shown in FIGS. Each electrode bump 231 is in contact with the bonding layer 24. The electrode bump 231 according to the present embodiment is made of Al.

  As shown in FIGS. 2, 3, and 5 to 8, the bonding layer 24 is a conductive member that is interposed between the electrode bumps 231 of the second semiconductor element 23 and the plating layer 212 of the wiring layer 21. The second semiconductor element 23 is mounted on the wiring layer 21 by being fixed to the wiring layer 21 by the bonding layer 24. In addition, conduction between the second semiconductor element 23 and the wiring layer 21 is ensured by the bonding layer 24. The bonding layer 24 according to the present embodiment is composed of an Ni layer and an alloy layer containing Sn stacked on each other. The alloy layer is a lead-free solder such as a Sn—Sb alloy or a Sn—Ag alloy.

  As shown in FIGS. 2, 3, and 5 to 8, the frame-like body 25 surrounds the periphery of the bonding layer 24 and is an insulating member. In the present embodiment, the frame body 25 is in contact with both the plating layer 212 and the bonding layer 24 of the wiring layer 21. The frame-like body 25 is made of a synthetic resin having electrical insulation, and is made of polyimide in this embodiment.

  As shown in FIGS. 1, 2, and 6, the passive element 26 is an element that is mounted on the wiring layer 21 together with the second semiconductor element 23. The passive element 26 is fixed to the wiring layer 21 with a solder layer 261. The passive element 26 according to the present embodiment is a resistor. In addition to the resistor, the passive element 26 can employ various elements such as a capacitor, an inductor, and a crystal resonator according to the circuit of the semiconductor device A10 configured by the first semiconductor element 12 and the second semiconductor element 23. . Moreover, the solder layer 261 according to the present embodiment is composed of a lead-free cream solder such as a Sn—Sb alloy or a Sn—Ag alloy.

  As shown in FIGS. 1 to 3 and FIGS. 5 to 7, the sealing resin 3 is an insulating member that covers the first semiconductor element 12, the first columnar body 13, the wiring layer 21, and the second semiconductor element 23. Yes, including a first sealing resin 31 and a second sealing resin 32. Both the first sealing resin 31 and the second sealing resin 32 according to the present embodiment are black synthetic resins mainly composed of an epoxy resin.

  As shown in FIGS. 1 to 3 and FIGS. 5 to 7, the first sealing resin 31 is a part of the sealing resin 3 that covers the first semiconductor element 12 and the first columnar body 13. The first sealing resin 31 has a resin back surface 311 facing the same direction as the element back surface 122 of the first semiconductor element 12 and a first bonding surface 312 facing the side opposite to the resin back surface 311. The top surface 131 of the first columnar body 13 is exposed from the first joint surface 312.

  As shown in FIGS. 1 to 3 and FIGS. 5 to 7, the second sealing resin 32 is a part of the sealing resin 3 that covers the wiring layer 21 and the second semiconductor element 23. The second sealing resin 32 has a resin main surface 321 facing in the same direction as the element main surface 121 of the first semiconductor element 12, and faces the opposite side of the resin main surface 321, and the first sealing resin 31 has a first sealing resin 31. The second bonding surface 322 is in contact with the bonding surface 312.

  As shown in FIGS. 1 to 3 and FIGS. 5 to 7, the pad layer 4 is a conductive member that contacts the end surface 222 of the second columnar body 22 and is exposed to the outside of the semiconductor device A10. The pad layer 4 is a part used as a terminal of the semiconductor device A10 when the semiconductor device A10 is mounted on a circuit board. The pad layer 4 according to this embodiment is configured to be exposed from the resin main surface 321 of the second sealing resin 32 to the outside of the semiconductor device A10. In addition, the pad layer 4 according to the present embodiment is composed of a Ni layer, a Pd layer, and an Au layer stacked on each other. The Ni layer is in contact with the end face 222, the Pd layer is in contact with the Ni layer, and the Au layer is in contact with the Pd layer.

  Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS.

  9 to 27 are cross-sectional views illustrating the manufacturing process of the semiconductor device A10. FIG. 28 is a plan view for explaining the manufacturing process for the semiconductor device A10. 9 to 27 correspond to the cross-sectional position of FIG. 5 showing the semiconductor device A10. In addition, the thickness direction Z, the first direction X, and the second direction Y of the first semiconductor element 80 (or base material 81) to be described later shown in FIGS. 9 to 28 are the first shown in FIGS. This corresponds to the thickness direction Z, the first direction X, and the second direction Y of the semiconductor element 12.

  First, as shown in FIG. 9, a first semiconductor element 80 having an element main surface 801 and an element back surface 802 facing each other in the thickness direction Z is prepared. The first semiconductor element 80 corresponds to the first semiconductor element 12 of the semiconductor device A10. The first semiconductor element 80 can be obtained by dicing along the cutting line CL on a silicon wafer on which a circuit is formed in the previous process for manufacturing the semiconductor device A10. In the first semiconductor element 80, a first columnar body 803 extending from the element main surface 801 along the thickness direction Z is formed. The first columnar body 803 corresponds to the first columnar body 13 of the semiconductor device A10. The first columnar body 803 is formed by electrolytic plating after a mask is formed on the element main surface 801 by photolithography. The first columnar body 803 according to the present embodiment is made of Cu.

Next, as illustrated in FIG. 10, an insulating film 811 is formed on the base material 81. The substrate 81 according to this embodiment is a silicon wafer made of single crystal Si. Further, the insulating film 811 according to the present embodiment is made of C ₄ F ₈ . The insulating film 811 can be formed by utilizing a protective film forming step in a Bosch process which is a typical example of deep RIE (Reactive Ion Etching). In this case, the insulating film 811 is formed on the substrate 81 by generating radicals from the C ₄ F ₈ gas by plasma. The insulating film 811 is formed on one side of the base material 81.

  Next, as shown in FIG. 11, a release layer 812 that covers the base material 81 and is in contact with both the insulating film 811 and a protective layer 82 described later is formed. The release layer 812 according to this embodiment is made of Ti. The peeling layer 812 is formed by a sputtering method.

  Next, as illustrated in FIG. 12, a protective layer 82 that covers the base material 81 and is in contact with the release layer 812 is formed. The protective layer 82 corresponds to the protective layer 11 of the semiconductor device A10. The protective layer 82 according to this embodiment is made of polyimide. The protective layer 82 is formed by coating using a spin coater (rotary coating device) or the like.

  Next, as shown in FIG. 13, the first semiconductor element 80 is mounted on the base material 81 so that the element back surface 802 faces the base material 81. In the present embodiment, the first semiconductor element 80 is mounted on the substrate 81 by die bonding in which an adhesive layer 804 is interposed between the element back surface 802 and the substrate 81. At this time, the protective layer 82 faces the element back surface 802 and the adhesive layer 804 is in contact with both the protective layer 82 and the element back surface 802. The adhesive layer 804 is composed of a film adhesive or a paste adhesive. The film adhesive is, for example, a die attach film (DAF). The paste adhesive is, for example, a conductive paste such as an Ag paste or an electrically insulating paste mainly composed of polyimide.

  Depending on the properties of the first semiconductor element 80, the formation of the protective layer 82 can be omitted. In this case, for example, a heat release sheet is applied to the release layer 812 described above. The thermal release sheet has adhesiveness at room temperature and has a property of peeling from an object at high temperature. Moreover, when the peeling layer 812 is comprised from the said heat peeling sheet, the contact bonding layer 804 is unnecessary in the process of mounting the 1st semiconductor element 80 on the base material 81 shown in FIG.

  Next, as shown in FIG. 14, a first sealing resin 83 that covers the first semiconductor element 80 and the first columnar body 803 is formed. The first sealing resin 83 corresponds to the first sealing resin 31 of the semiconductor device A10. The first sealing resin 83 is a black synthetic resin mainly composed of an epoxy resin. In forming the first sealing resin 83, first, the entire surface of the first semiconductor element 80 and the first columnar body 803 is in contact with the protective layer 82 (the peeling layer 812 when the protective layer 82 is omitted) by compression molding. First sealing resin 83 is formed so as to cover. Thereafter, in the thickness direction Z of the base material 81, the end portion of the first sealing resin 83 located on the side opposite to the base material 81 is removed by mechanical grinding. At this time, a first top surface 803 a exposed from the first sealing resin 83 is formed in the first columnar body 803.

  Next, as shown in FIGS. 15 to 23, the wiring layer 84 that contacts the first top surface 803 a of the first columnar body 803 and the first sealing resin 83 is formed. The wiring layer 84 corresponds to the wiring layer 21 of the semiconductor device A10. In the step of forming the wiring layer 84, a step of forming the wiring base layer 841 in contact with the first top surface 803a of the first columnar body 803 and the first sealing resin 83, and a plating layer 842 in contact with the wiring base layer 841 are formed. The process of carrying out is included. Further, in the step of forming the wiring layer 84, after forming the plating layer 842, a step of forming a second columnar body 85 described later in contact with the plating layer 842, a frame-shaped body 862 described later in contact with the plating layer 842, and Forming a bonding layer 863; The wiring layer 84, the second columnar body 85, the frame-shaped body 862, and the bonding layer 863 are formed by the following procedure.

  First, as shown in FIG. 15, the wiring base layer 841 in contact with the first top surface 803 a of the first columnar body 803 and the first sealing resin 83 is formed. The wiring base layer 841 corresponds to the base layer 211 of the wiring layer 21 of the semiconductor device A10. The wiring base layer 841 is formed by sputtering to cover the entire surface of the first sealing resin 83 where the first top surface 803a of the first columnar body 803 is exposed. The wiring foundation layer 841 according to the present embodiment is composed of a Ti layer and a Cu layer laminated on each other, and the total thickness is 200 to 300 nm. In forming the wiring base layer 841, after forming a Ti layer in contact with the first sealing resin 83, a Cu layer in contact with the Ti layer is formed.

  Next, as shown in FIG. 16, a first mask layer 891 for forming the plating layer 842 is formed by photolithography on the wiring base layer 841. After a photosensitive resist is applied so as to cover the entire surface of the wiring base layer 841, the first mask layer 891 is formed by exposing and developing the photosensitive resist. The photosensitive resist is applied using, for example, a spin coater. At this time, a part of the wiring base layer 841 is exposed from the first mask layer 891.

  Next, as shown in FIG. 17, a plating layer 842 that is in contact with the wiring base layer 841 exposed from the first mask layer 891 is formed. The plating layer 842 corresponds to the plating layer 212 of the wiring layer 21 of the semiconductor device A10. The plating layer 842 according to the present embodiment is formed by electrolytic plating using the wiring base layer 841 as a conductive path. Moreover, the plating layer 842 according to the present embodiment is made of Cu and has a thickness of 3 to 10 μm. After the plating layer 842 is formed, the entire first mask layer 891 is removed.

  Next, as shown in FIG. 18, a frame-like body 862 that is in contact with the plating layer 842 and surrounds a bonding layer 863 to be described later is formed by photolithography. The frame body 862 corresponds to the frame body 25 of the semiconductor device A10. The frame body 862 is formed by applying photosensitive polyimide so as to cover the entire surface of the wiring base layer 841 and the plating layer 842, and then exposing and developing the photosensitive polyimide. The photosensitive polyimide is applied using, for example, a spin coater.

  Next, as illustrated in FIGS. 19 and 20, a bonding layer 863 that is in contact with the plating layer 842 and on which a second semiconductor element 861 described later is mounted is formed. The bonding layer 863 corresponds to the bonding layer 24 of the semiconductor device A10.

  As shown in FIG. 19, a second mask layer 892 for forming the bonding layer 863 is formed by photolithography on the wiring base layer 841, the plating layer 842, and the frame body 862. A photosensitive resist is applied so as to cover the entire surface of the wiring base layer 841, the plating layer 842, and the frame body 862, and then the second mask layer 892 is formed by exposing and developing the photosensitive resist. . The photosensitive resist used for forming the second mask layer 892 and the method for forming the second mask layer 892 are both the same as those for the first mask layer 891. At this time, the second mask layer 892 is formed with a cavity 892a that includes a portion surrounded by the frame-like body 862 and exposes a part of the plating layer 842. The shape of the cavity 892a according to the present embodiment is a rectangular parallelepiped (not shown).

  After the second mask layer 892 is formed, a bonding layer 863 is formed as shown in FIG. The bonding layer 863 according to this embodiment is formed so as to fill the cavity 892a of the second mask layer 892 by electrolytic plating using the wiring base layer 841 and the plating layer 842 as conductive paths. Further, the bonding layer 863 according to the present embodiment is composed of an Ni layer and an alloy layer containing Sn stacked on each other. The alloy layer is a lead-free solder such as a Sn—Sb alloy or a Sn—Ag alloy. After the bonding layer 863 is formed, the entire second mask layer 892 is removed.

  Next, as shown in FIGS. 21 and 22, a second columnar body 85 that contacts the plating layer 842 and extends along the thickness direction Z of the base material 81 is formed. The second columnar body 85 corresponds to the second columnar body 22 of the semiconductor device A10.

  As shown in FIG. 21, a third mask layer 893 for forming the second columnar body 85 is formed by photolithography on the wiring base layer 841, the plating layer 842, the frame-shaped body 862, and the bonding layer 863. After applying a photosensitive resist so as to cover the entire surface of the wiring base layer 841, the plating layer 842, the frame-like body 862, and the bonding layer 863, the third mask layer 893 is exposed and developed on the photosensitive resist. Is formed. The photosensitive resist used for forming the third mask layer 893 and the method for forming the third mask layer 893 are both the same as those for the first mask layer 891. At this time, the third mask layer 893 is formed with a cavity 893a in which a part of the plating layer 842 is exposed. The shape of the cavity 893a according to the present embodiment is a prismatic shape (not shown).

  After forming the third mask layer 893, the second columnar body 85 is formed as shown in FIG. The second columnar body 85 according to the present embodiment is formed so as to fill the cavity 893a of the third mask layer 893 by electrolytic plating using the wiring base layer 841 and the plating layer 842 as the conductive paths in the same manner as the bonding layer 863. The Moreover, the 2nd columnar body 85 concerning this embodiment is comprised from Cu. After the second columnar body 85 is formed, the entire third mask layer 893 is removed.

Next, as shown in FIG. 23, all the wiring base layer 841 that is not covered by the plating layer 842 or the frame-like body 862 is removed. The wiring base layer 841 is removed by wet etching, for example. In the wet etching, for example, a mixed solution of H ₂ SO ₄ (sulfuric acid) and H ₂ O ₂ (hydrogen peroxide) is used. At this time, a part of the first sealing resin 83 is exposed from the portion where the wiring base layer 841 is removed. In this state, the wiring base layer 841 and the plating layer 842 that are stacked on each other are the wiring layer 84. The wiring layer 84, the second columnar body 85, the frame-shaped body 862, and the bonding layer 863 are formed by the above procedure.

  Next, as shown in FIG. 24, the second semiconductor element 861 is mounted on the wiring layer 84. The second semiconductor element 861 corresponds to the second semiconductor element 23 of the semiconductor device A10. The second semiconductor element 861 is mounted by FCB (Flip Chip Bonding). After flux is applied to the electrode bumps 861a of the second semiconductor element 861, the second semiconductor element 861 is temporarily attached to the bonding layer 863 using a flip chip bonder. At this time, the bonding layer 863 is sandwiched between both the wiring layer 84 and the electrode bump 861a. Thereafter, the bonding layer 863 is melted by reflow, and then the bonding layer 863 is solidified by cooling, whereby the mounting of the second semiconductor element 861 is completed.

  As shown in FIG. 24, in the step of mounting the second semiconductor element 861 on the wiring layer 84, the passive element 864 is mounted on the wiring layer 84 together with the second semiconductor element 861. The passive element 864 according to the present embodiment is a resistor. The passive element 864 is mounted by disposing the passive element 864 on the solder layer 865 made of cream solder and melting and solidifying the solder layer 865 simultaneously with the bonding layer 863.

  Next, as shown in FIG. 25, a second sealing resin 87 that contacts the first sealing resin 83 and covers the wiring layer 84 and the second semiconductor element 861 is formed. The second sealing resin 87 corresponds to the second sealing resin 32 of the semiconductor device A10. The second sealing resin 87 is a black synthetic resin having an epoxy resin as a main component, like the first sealing resin 83. In forming the second sealing resin 87, first, the second sealing resin 87 is contacted with the first sealing resin 83 by compression molding and covers the entire surface of the wiring layer 84, the second columnar body 85, and the second semiconductor element 861. A sealing resin 87 is formed. Thereafter, in the thickness direction Z of the base material 81, the end portion of the second sealing resin 87 located on the side opposite to the first sealing resin 83 is removed by mechanical grinding. At this time, an end surface 851 that intersects the thickness direction Z of the base material 81 and is exposed from the second sealing resin 87 is formed on the second columnar body 85.

  Next, as shown in FIG. 26, a pad layer 88 that contacts the end surface 851 of the second columnar body 85 exposed from the second sealing resin 87 is formed. The pad layer 88 corresponds to the pad layer 4 of the semiconductor device A10. The pad layer 88 according to this embodiment is formed by depositing each layer in the order of Ni layer, Pd layer, and Au layer by electroless plating.

  Next, as shown in FIG. 27, the base material 81 is removed from the protective layer 82. In the step according to the present embodiment, the insulating film 811 and the release layer 812 are removed from the protective layer 82 together with the base material 81. First, the base material 81 and the insulating film 811 are removed from the protective layer 82. At this time, the base material 81 is peeled together with the insulating film 811 at the interface between the insulating film 811 and the peeling layer 812. After the base material 81 and the insulating film 811 are removed, the peeling layer 812 attached to the protective layer 82 is removed by wet etching. At this time, the protective layer 82 is exposed to the outside. When the protective layer 82 is omitted, the substrate 81 is heated with a heater or the like, and then the substrate 81 integrated with the insulating film 811 from the first semiconductor element 80 and the first sealing resin 83, and the release layer 812 is peeled off.

  Finally, as shown in FIG. 28, the protective layer 82, the first sealing resin 83, and the second sealing resin 87 are cut along the cutting line CL, and the first semiconductor covered with the first sealing resin 83 is obtained. The element 80 and the second semiconductor element 861 covered with the second sealing resin 87 are divided into individual pieces. In cutting, the protective layer 82, the first sealing resin 83, and the second sealing resin 87 are cut by, for example, plasma dicing. The individual pieces divided in this process become the semiconductor device A10. The semiconductor device A10 is manufactured through the above steps.

  Next, functions and effects of the semiconductor device A10 and its manufacturing method will be described.

  The semiconductor device A10 includes a first semiconductor element 12, a first columnar body 13 formed in the first semiconductor element 12, a wiring layer 21 that conducts to the first columnar body 13, and a second mounted on the wiring layer 21. A semiconductor element 23 is provided. The first semiconductor element 12, the first columnar body 13, the wiring layer 21 and the second semiconductor element 23 are all covered with the sealing resin 3. The semiconductor device A10 includes a second columnar body 22 that has a side surface 221 and an end surface 222, is electrically connected to the wiring layer 21, and is spaced apart from the first columnar body 13 in plan view. In this case, the side surface 221 is covered with the sealing resin 3, and the end surface 222 is exposed from the sealing resin 3. By adopting such a configuration, a substrate on which each of the first semiconductor element 12 and the second semiconductor element 23 is mounted becomes unnecessary, and the apparatus can be further reduced in thickness. Further, in the semiconductor device A10, the first columnar body 13 and the second columnar body 22 which are the conduction paths in the thickness direction Z of the first semiconductor element 12 are all encapsulating resin 3 except for the end surface 222 of the second columnar body 22. Covered with For this reason, there is no possibility that a failure occurs in the conductive path inside the semiconductor device A10 due to the thermal shock when the semiconductor device A10 is mounted on the circuit board. Therefore, according to the semiconductor device A10, it is possible to further reduce the thickness and improve the reliability.

  Here, according to the manufacturing method of the semiconductor device A10, the step of mounting the first semiconductor element 80 on the base material 81, the step of forming the first sealing resin 83 covering the first columnar body 803, and the first sealing A step of forming a wiring layer 84 in contact with the stop resin 83 and a step of peeling the base material 81 are provided. The wiring layer 84 mounts the second semiconductor element 861. By providing such a process, it is possible to eliminate the need for a substrate on which each of the first semiconductor element 12 and the second semiconductor element 23 is mounted in the semiconductor device A10. Moreover, according to the manufacturing method of semiconductor device A10, the process of forming the 2nd sealing resin 87 which covers the 2nd semiconductor element 23 and the 2nd columnar body 22 is provided with the said process. By providing such a process, in the semiconductor device A10, both the first columnar body 13 and the second columnar body 22 can be configured to be covered with the sealing resin 3.

  The semiconductor device A10 includes a protective layer 11 that is disposed in contact with the resin back surface 311 of the first sealing resin 31 and that is an insulator. The protective layer 11 according to this embodiment is made of polyimide. By providing the protective layer 11, it is possible to further improve the reliability against thermal shock when the semiconductor device A10 is mounted.

  The conductive portion 20 of the semiconductor device A <b> 10 includes a base layer 211 and a plating layer 212 stacked on each other, and the base layer 211 is in contact with the first sealing resin 31. The underlayer 211 is made of Ti and is made of a first underlayer 211a that is in contact with the first sealing resin 31, and Cu, and is formed between the first underlayer 211a and the plating layer 212. 2 base layers 211b. By adopting such a configuration, the second base layer 211b and the plating layer 212 are diffused into the base material 81 for manufacturing the semiconductor device A10, and the second base layer 211b is formed from the protective layer 11 or the base material 81. Both can be prevented from peeling off. Further, in the step of forming the wiring layer 84 related to the manufacture of the semiconductor device A10 by the second base layer 211b, the plating layer 842, the second columnar body 85, and the bonding layer 863 can be efficiently formed by electrolytic plating.

  The semiconductor device A10 includes a bonding layer 24 interposed between the second semiconductor element 23 and the wiring layer 21. By providing the bonding layer 24, the second semiconductor element 861 can be accurately mounted on the wiring layer 84 by FCB in the step of mounting the second semiconductor element 861 related to the manufacture of the semiconductor device A10. Compared with the case where the second semiconductor element 861 is mounted on the wiring layer 84 by wire bonding, the size of the semiconductor device A10 in plan view can be reduced. This contributes to miniaturization of the semiconductor device A10.

  The semiconductor device A10 includes a frame 25 that surrounds the bonding layer 24 and is an insulator. By providing the frame-like body 25, when the bonding layer 863 is melted by reflow in the step of mounting the second semiconductor element 861 related to the manufacture of the semiconductor device A10, the bonding layer 863 is dammed by the frame-like body 862. it can. For this reason, it is possible to prevent an unintended conductive path from being formed in the wiring layer 84 due to melting of the bonding layer 863.

  The semiconductor device A10 includes a pad layer 4 that is in contact with the end surface 222 of the second columnar body 22 and exposed to the outside. The pad layer 4 according to the present embodiment is composed of a Ni layer, a Pd layer, and an Au layer that are laminated together. By adopting such a configuration, the second columnar body 22 can be protected from the thermal shock when the semiconductor device A10 is mounted by the Ni layer and the Pd layer. In addition, the wettability of the lead-free cream solder with respect to the pad layer 4 can be improved by the Au layer when the semiconductor device A10 is mounted.

  The semiconductor device A10 includes a passive element 26 mounted on the wiring layer 21. For this reason, since various circuits can be configured in the semiconductor device A10, the range of functions of the semiconductor device A10 can be expanded.

[Second Embodiment]
A semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. In these drawings, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 29 is a plan view of the semiconductor device A20 and transmits the second sealing resin 32 for convenience of understanding. FIG. 30 is a bottom view of the semiconductor device A20. FIG. 31 is a plan view showing the protective layer 11, the first semiconductor element 12, the first columnar body 13, and the adhesive layer 14 of the semiconductor device A20. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG.

  The semiconductor device A20 according to this embodiment is different from the semiconductor device A10 in the configuration of the protective layer 11, the second columnar body 22, and the pad layer 4. As shown in FIG. 29, the shape of the semiconductor device A20 in plan view is a rectangular shape.

  As shown in FIGS. 30 to 32, the protective layer 11 according to the present embodiment is formed with a plurality of openings 111 penetrating in the thickness direction Z of the first semiconductor element 12. Each opening 111 has a rectangular shape. In the present embodiment, the second columnar body 22 is disposed in a state of penetrating the opening 111. The protective layer 11 according to this embodiment is made of polyimide.

  As shown in FIGS. 29, 30, and 32, in the second columnar body 22 according to the present embodiment, the side surface 221 is covered with the first sealing resin 31. Further, the end face 222 is exposed from the opening 111 of the protective layer 11. The end surface 222 according to the present embodiment faces the same direction as the element back surface 122 of the first semiconductor element 12. For this reason, in the present embodiment, the second columnar body 22 is arranged in contact with the base layer 211 of the wiring layer 21.

  As shown in FIGS. 30 and 32, the pad layer 4 according to the present embodiment is exposed to the outside of the semiconductor device A10 from the surface of the protective layer 11 facing the same direction as the resin back surface 311 of the first sealing resin 31. It has become.

  Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to FIGS.

  33 to 41 are cross-sectional views illustrating the manufacturing process of the semiconductor device A20. The cross-sectional positions in FIGS. 33 to 41 correspond to the cross-sectional positions in FIG. 32 showing the semiconductor device A20.

  First, a first semiconductor element 80 having an element main surface 801 and an element back surface 802 facing each other in the thickness direction Z is prepared. The first semiconductor element 80 corresponds to the first semiconductor element 12 of the semiconductor device A20. The process of preparing the first semiconductor element 80 according to the present embodiment is the same as the process of preparing the first semiconductor element 80 according to the manufacture of the semiconductor device A10 shown in FIG. Further, the first semiconductor element 80 is formed with a first columnar body 803 extending from the element main surface 801 along the thickness direction Z. The first columnar body 803 according to the present embodiment is the same as the first columnar body 803 according to the manufacture of the semiconductor device A10. For this reason, the first columnar body 803 corresponds to the first columnar body 13 of the semiconductor device A20.

  Next, an insulating film 811 is formed on the base material 81. The configuration of the substrate 81 according to the present embodiment is the same as the configuration of the substrate 81 according to the manufacture of the semiconductor device A10. Further, the process of forming the insulating film 811 according to the present embodiment is the same as the process of forming the insulating film 811 according to the manufacture of the semiconductor device A10 shown in FIG.

  Next, a peeling layer 812 that covers the base material 81 and is in contact with both the insulating film 811 and a columnar base layer 813 described later is formed. Since the process of forming the peeling layer 812 concerning this embodiment is the same as the process of forming the peeling layer 812 concerning manufacture of semiconductor device A10 shown in FIG. 11, description here is abbreviate | omitted.

  Next, as shown in FIGS. 33 and 34, a protective layer 82 that covers the base material 81 and has an opening 821 is formed. The step of forming the protective layer 82 includes a step of forming a columnar body base layer 813 that is interposed between the base material 81 and the protective layer 82 and is exposed from the opening 821 of the protective layer 82. The protective layer 82 corresponds to the protective layer 11 of the semiconductor device A20.

  As shown in FIG. 33, a columnar base layer 813 is formed before the protective layer 82 is formed. The columnar base layer 813 according to the present embodiment is made of Cu and is in contact with the release layer 812. The columnar base layer 813 is formed by a sputtering method.

  After the columnar base layer 813 is formed, a protective layer 82 is formed by photolithography as shown in FIG. The protective layer 82 is formed by applying photosensitive polyimide so as to cover the entire surface of the columnar base layer 813 and then exposing and developing the photosensitive polyimide. The photosensitive polyimide is applied using, for example, a spin coater. At this time, an opening 821 is formed in the protective layer 82, and a part of the columnar body base layer 813 is exposed from the opening 821. The shape of the opening 821 according to this embodiment in a plan view is a rectangular shape (not shown).

  Next, as shown in FIGS. 35 and 36, a second columnar body 85 extending from the opening 821 of the protective layer 82 along the thickness direction Z of the base material 81 is formed. The second columnar body 85 corresponds to the second columnar body 22 of the semiconductor device A20.

  As shown in FIG. 35, the first mask layer 891 for forming the second columnar body 85 is formed by photolithography on the protective layer 82 and the columnar base layer 813. After a photosensitive resist is applied so as to cover the entire surface of the protective layer 82 and the columnar body base layer 813, the first mask layer 891 is formed by exposing and developing the photosensitive resist. The photosensitive resist is applied using, for example, a spin coater. At this time, the first mask layer 891 is formed with a cavity 891a in which a part of the columnar body base layer 813 is exposed. The shape of the cavity 891a according to the present embodiment is a prismatic shape (not shown).

  After forming the first mask layer 891, the second columnar body 85 is formed as shown in FIG. The second columnar body 85 according to the present embodiment is formed so as to fill the cavity 891a of the first mask layer 891 by electrolytic plating using the columnar body underlayer 813 as a conductive path. Moreover, the 2nd columnar body 85 concerning this embodiment is comprised from Cu. After forming the second columnar body 85, the first mask layer 891 is completely removed.

  Next, as shown in FIG. 37, the first semiconductor element 80 is mounted on the protective layer 82 so that the element back surface 802 faces the protective layer 82. In the present embodiment, the first semiconductor element 80 is mounted on the protective layer 82 by die bonding using the adhesive layer 804 that contacts both the element back surface 802 and the protective layer 82. The configuration of the adhesive layer 804 is the same as the configuration of the adhesive layer 804 according to the manufacture of the semiconductor device A10.

  Next, as shown in FIG. 38, a first sealing resin 83 that covers the first semiconductor element 80, the first columnar body 803, and the second columnar body 85 is formed. The first sealing resin 83 corresponds to the first sealing resin 31 of the semiconductor device A20. The first sealing resin 83 is a black synthetic resin mainly composed of an epoxy resin. In forming the first sealing resin 83, first, a first sealing is performed by compression molding so as to be in contact with the protective layer 82 and cover the entire surface of the first semiconductor element 80, the first columnar body 803, and the second columnar body 85. A stop resin 83 is formed. Thereafter, in the thickness direction Z of the base material 81, the end portion of the first sealing resin 83 located on the side opposite to the protective layer 82 is removed by mechanical grinding. At this time, a first top surface 803 a exposed from the first sealing resin 83 is formed in the first columnar body 803. In addition, a second top surface 852 exposed from the first sealing resin 83 is formed in the second columnar body 85.

  Next, the first top surface 803a of the first columnar body 803, the second top surface 852 of the second columnar body 85, and the wiring layer 84 in contact with the first sealing resin 83 are formed. The wiring layer 84 corresponds to the wiring layer 21 of the semiconductor device A20. In the step of forming the wiring layer 84, a step of forming the wiring base layer 841 in contact with the first top surface 803a of the first columnar body 803 and the first sealing resin 83, and a plating layer 842 in contact with the wiring base layer 841 are formed. The process of carrying out is included. Further, the step of forming the wiring layer 84 includes a step of forming the frame body 862 and the bonding layer 863 in contact with the plating layer 842 after the plating layer 842 is formed. The frame body 862 corresponds to the frame body 25 of the semiconductor device A20, and the bonding layer 863 corresponds to the bonding layer 24 of the semiconductor device A20. The step of forming the wiring layer 84 according to the present embodiment is a step of forming the wiring layer 84 according to the manufacture of the semiconductor device A10 shown in FIGS. 15 to 20 and 23 (excluding the step of forming the second columnar body 85). ), The description here is omitted.

  Next, the second semiconductor element 861 is mounted on the wiring layer 84. The second semiconductor element 861 corresponds to the second semiconductor element 23 of the semiconductor device A20. The process of mounting the second semiconductor element 861 according to the present embodiment is the same as the process of mounting the second semiconductor element 861 according to the manufacture of the semiconductor device A10 shown in FIG. In this process, the passive element 864 is mounted on the wiring layer 84 together with the second semiconductor element 861. The mounting method of the passive element 864 is the same as the mounting method of the passive element 864 according to the manufacture of the semiconductor device A10 shown in FIG.

  Next, as shown in FIG. 39, a second sealing resin 87 that contacts the first sealing resin 83 and covers the wiring layer 84 and the second semiconductor element 861 is formed. The second sealing resin 87 corresponds to the second sealing resin 32 of the semiconductor device A20. The second sealing resin 87 is a black synthetic resin having an epoxy resin as a main component, like the first sealing resin 83. In forming the second sealing resin 87, first, the second sealing resin 87 is formed by compression molding so as to be in contact with the first sealing resin 83 and cover the entire surface of the wiring layer 84 and the second semiconductor element 861. To do.

  Next, as shown in FIG. 40, the base material 81 is removed from the protective layer 82. In the step according to the present embodiment, the insulating film 811, the release layer 812, and the columnar body base layer 813 are removed from the protective layer 82 together with the base material 81. First, the base material 81 and the insulating film 811 are removed from the protective layer 82. At this time, the base material 81 is peeled together with the insulating film 811 at the interface between the insulating film 811 and the peeling layer 812. After the base material 81 and the insulating film 811 are removed, the peeling layer 812 and the columnar base layer 813 attached to the protective layer 82 are removed by wet etching. At this time, the protective layer 82 is exposed to the outside, and an end face 851 that intersects the thickness direction Z of the base material 81 and is exposed from the opening 821 of the protective layer 82 appears in the second columnar body 85.

  Next, as shown in FIG. 41, a pad layer 88 that contacts the end surface 851 of the second columnar body 85 exposed from the opening 821 of the protective layer 82 is formed. The pad layer 88 corresponds to the pad layer 4 of the semiconductor device A20. The pad layer 88 according to this embodiment is formed by depositing each layer in the order of Ni layer, Pd layer, and Au layer by electroless plating.

  Finally, the protective layer 82, the first sealing resin 83, and the second sealing resin 87 are cut, and the first semiconductor element 80 covered with the first sealing resin 83 and the second sealing resin 87 are covered. The second semiconductor element 861 is divided into individual pieces. The cutting method is the same as the cutting method for manufacturing the semiconductor device A10 shown in FIG. The individual pieces divided in this process become the semiconductor device A20. The semiconductor device A20 is manufactured through the above steps.

  Next, functions and effects of the semiconductor device A20 and its manufacturing method will be described.

  The semiconductor device A20 includes a first semiconductor element 12, a first columnar body 13, a wiring layer 21, a second semiconductor element 23, and a sealing resin 3 that have the same configuration as the semiconductor device A10. In addition, the semiconductor device A20 includes a second columnar body 22 that is electrically connected to the wiring layer 21 and is spaced apart from the first columnar body 13 in plan view. The side surface 221 of the second columnar body 22 is covered with the sealing resin 3, and the end surface 222 is exposed from the sealing resin 3. For this reason, also in the semiconductor device A20, a substrate on which each of the first semiconductor element 12 and the second semiconductor element 23 is mounted becomes unnecessary, and the apparatus can be further reduced in thickness. Also in the semiconductor device A20, all of the first columnar body 13 and the second columnar body 22 that serve as a conduction path in the thickness direction Z of the first semiconductor element 12 are encapsulating resin except for the end surface 222 of the second columnar body 22. 3 is covered. For this reason, there is no possibility that a failure occurs in the conductive path inside the semiconductor device A20 due to the thermal shock when the semiconductor device A20 is mounted. Therefore, the semiconductor device A20 can further reduce the thickness and improve the reliability.

  Here, according to the manufacturing method of the semiconductor device A20, the step of forming the protective layer 82 on the base member 81, the step of forming the second columnar body 85 on the base member 81, and the first semiconductor element 80 on the protective layer 82. The process of mounting is equipped. In addition, a step of forming the first sealing resin 83 covering the first columnar body 803 and the second columnar body 85, and a wiring layer 84 in contact with the first sealing resin 83 and mounting the second semiconductor element 861 are provided. A step of forming, and a step of peeling the substrate 81 from the protective layer 82. By providing such a process, also in the semiconductor device A20, the substrate on which each of the first semiconductor element 12 and the second semiconductor element 23 is mounted is unnecessary, and both the first columnar body 13 and the second columnar body 22 are provided. Can be configured to be covered with the sealing resin 3.

  The second columnar body 22 of the semiconductor device A20 is configured to be covered with the first sealing resin 31. For this reason, since the area of the 1st joint surface 312 of the 1st sealing resin 31 expands rather than semiconductor device A10, since the arrangement area of the wiring layer 21 is ensured more widely, the passive element mounted in the wiring layer 21 26 types can be increased. Therefore, a more complicated circuit can be configured in the semiconductor device A20.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways.

A10, A20: Semiconductor device 11: Protective layer 111: Opening 12: First semiconductor element 121: Element main surface 122: Element back surface 13: First columnar body 131: Top surface 14: Adhesive layer 21: Wiring layer 211: Bottom Base layer 211a: first base layer 211b: second base layer 212: plating layer 22: second columnar body 221: side surface 222: end surface 23: second semiconductor element 231: electrode bump 24: bonding layer 25: frame-like body 26: Passive element 261: Solder layer 3: Sealing resin 31: First sealing resin 311: Resin back surface 312: First bonding surface 32: Second sealing resin 321: Resin main surface 322: Second bonding surface 4: Pad layer 80: first semiconductor element 801: element main surface 802: element back surface 803: first columnar body 803a: first top surface 804: adhesive layer 81: base material 811: insulating film 812: release layer 813: columnar body Underlayer 82: Protective layer 821: Opening 83: First sealing resin 84: Wiring layer 841: Wiring underlayer 842: Plating layer 85: Second columnar body 851: End surface 852: Second top surface 861: Second semiconductor Element 861a: Electrode bump 862: Frame-like body 863: Bonding layer 864: Passive element 865: Solder layer 87: Second sealing resin 88: Pad layer 891: First mask layer 891a: Cavity portion 892: Second mask layer 892a : Cavity 893: third mask layer 893a cavity X: first direction Y: second direction Z: thickness direction CL: cutting line

Claims (33)

A first semiconductor element having an element main surface and an element back surface facing opposite sides in the thickness direction;
A first columnar body extending along the thickness direction of the first semiconductor element from the element main surface;
A wiring layer connected to the first columnar body;
A second semiconductor element mounted on the wiring layer;
A second columnar body that is electrically connected to the wiring layer and that is spaced apart from the first columnar body in plan view and that extends along the thickness direction of the first semiconductor element;
A sealing resin that covers the first semiconductor element, the first columnar body, the wiring layer, and the second semiconductor element;
The second columnar body has a side surface along the thickness direction of the first semiconductor element, and an end surface intersecting the side surface,
The semiconductor device, wherein the side surface is covered with the sealing resin, and the end surface is exposed from the sealing resin. The sealing resin includes a first sealing resin having a resin back surface facing the same direction as the element back surface of the first semiconductor element, and a first bonding surface facing the opposite side of the resin back surface;
A second seal having a resin main surface facing in the same direction as the element main surface of the first semiconductor element, and a second bonding surface facing away from the resin main surface and in contact with the first bonding surface. A stop resin,
The first sealing resin covers the first semiconductor element and the first columnar body,
The semiconductor device according to claim 1, wherein the second sealing resin covers the wiring layer and the second semiconductor element.   The semiconductor device according to claim 2, wherein both the first sealing resin and the second sealing resin are synthetic resins mainly composed of an epoxy resin.   The semiconductor device according to claim 2, further comprising a protective layer that is disposed in contact with the back surface of the first sealing resin and is an insulator.   The semiconductor device according to claim 4, wherein the protective layer is made of polyimide.   The semiconductor device according to claim 4, comprising an adhesive layer interposed between the protective layer and the first semiconductor element.   The side surface of the second columnar body is covered with the second sealing resin, and the end surface of the second columnar body is exposed from the resin main surface of the second sealing resin. The semiconductor device according to any one of the above.   The side surface of the second columnar body is covered with the first sealing resin, and the end surface of the second columnar body is exposed from an opening formed in the protective layer. A semiconductor device according to claim 1. The wiring layer is composed of a base layer and a plating layer stacked on each other,
The base layer is in contact with the first joint surface of the first columnar body and the first sealing resin, and is set to be thinner than the plating layer. The semiconductor device described. The underlayer includes a first underlayer that is in contact with the first columnar body and the first bonding surface of the first sealing resin, and a second underlayer interposed between the first underlayer and the plating layer. And including
The semiconductor device according to claim 9, wherein the second base layer and the plating layer are both made of the same material.   The semiconductor device according to claim 10, wherein each of the second base layer and the plating layer is made of Cu.   The semiconductor device according to claim 10, wherein the first underlayer is made of Ti.   The semiconductor device according to claim 10, wherein the second columnar body is made of the same material as the second base layer and the plating layer.   The semiconductor device according to claim 1, further comprising a bonding layer interposed between the second semiconductor element and the wiring layer.   The semiconductor device according to claim 14, wherein the bonding layer includes an Ni layer and an alloy layer containing Sn stacked on each other.   The semiconductor device according to claim 14, further comprising a frame body that surrounds the bonding layer and is an insulator.   The semiconductor device according to claim 16, wherein the frame body is made of polyimide.   The semiconductor device according to claim 1, further comprising a pad layer that is in contact with the end face of the second columnar body and exposed to the outside.   The semiconductor device according to claim 18, wherein the pad layer is composed of a Ni layer, a Pd layer, and an Au layer stacked on each other.   The semiconductor device according to claim 1, further comprising a passive element mounted on the wiring layer. A step of preparing a first semiconductor element having an element main surface and an element back surface facing in opposite directions in the thickness direction and having a first columnar body extending from the element main surface along the thickness direction When,
Mounting the first semiconductor element on the substrate such that the back surface of the element faces the substrate;
Forming a first sealing resin covering the first semiconductor element and the first columnar body;
Forming a wiring layer in contact with the first columnar body and the first sealing resin;
Mounting a second semiconductor element on the wiring layer;
Forming a second sealing resin in contact with the first sealing resin and covering the wiring layer and the second semiconductor element;
Removing the base material, and
The step of forming the wiring layer includes a step of forming a second columnar body extending along the thickness direction of the base material,
In the step of forming the second sealing resin, the second columnar body is formed with an end surface that intersects the thickness direction of the base material and is exposed from the second sealing resin. A method for manufacturing a semiconductor device.   Between the step of forming the second sealing resin and the step of removing the base material, a pad layer in contact with the end surface of the second columnar body exposed from the second sealing resin is formed by electroless plating. The method for manufacturing a semiconductor device according to claim 21, comprising the step of:   Between the step of preparing the first semiconductor element and the step of mounting the first semiconductor element, a protective layer is formed by coating so as to cover the base material and face the element back surface of the first semiconductor element. The method for manufacturing a semiconductor device according to claim 22, comprising the step of: A step of preparing a first semiconductor element having an element main surface and an element back surface facing in opposite directions in the thickness direction and having a first columnar body extending from the element main surface along the thickness direction When,
Forming a protective layer covering the substrate and having an opening;
Forming a second columnar body extending from the opening along the thickness direction of the base material on the base material;
Mounting the first semiconductor element on the protective layer such that the back surface of the element faces the protective layer;
Forming a first sealing resin covering the first semiconductor element, the first columnar body, and the second columnar body;
Forming a wiring layer in contact with the first columnar body, the second columnar body, and the first sealing resin;
Mounting a second semiconductor element on the wiring layer;
Forming a second sealing resin in contact with the first sealing resin and covering the wiring layer and the second semiconductor element;
Removing the base material, and
In the step of removing the substrate, an end surface that intersects the thickness direction of the substrate and is exposed from the opening of the protective layer appears in the second columnar body. Method.   The semiconductor according to claim 24, further comprising a step of forming, by electroless plating, a pad layer that contacts the end face of the second columnar body exposed from the opening of the protective layer after the step of removing the base material. Device manufacturing method.   The step of forming the protective layer includes a step of forming, by sputtering, a columnar base layer that is interposed between the base material and the protective layer and exposed from the opening of the protective layer. 25. A method for manufacturing a semiconductor device according to 25.   27. The method of manufacturing a semiconductor device according to claim 26, wherein in the step of forming the protective layer, the protective layer is formed by photolithography.   28. The method of manufacturing a semiconductor device according to claim 26, wherein in the step of forming the second columnar body, the second columnar body is formed by electrolytic plating.   29. The method of manufacturing a semiconductor device according to claim 26, wherein, in the step of removing the base material, the columnar body underlayer is removed together with the base material.   In the step of forming the wiring layer, a step of forming a wiring base layer in contact with the first columnar body and the first sealing resin by a sputtering method, and a step of forming a plating layer in contact with the wiring base layer by electrolytic plating A method for manufacturing a semiconductor device according to claim 21, comprising:   The step of forming the wiring layer includes a step of forming a bonding layer in contact with the plating layer and mounting the second semiconductor element by electrolytic plating after forming the plating layer. A method for manufacturing a semiconductor device.   32. The method of manufacturing a semiconductor device according to claim 31, wherein the step of forming the wiring layer includes a step of forming a frame-like body that is in contact with the plating layer and surrounds the periphery of the bonding layer by photolithography.   33. The method of manufacturing a semiconductor device according to claim 21, wherein in the step of mounting the second semiconductor element, a passive element is mounted on the wiring layer together with the second semiconductor element.

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