JP2021034573A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of suppressing corrosion of a wiring layer in a manufacturing process of the device.SOLUTION: A semiconductor device comprises: an insulation layer 10 having a plurality of penetration parts 11 penetrated to a thickness direction z; a plurality of first terminals 51 individually housed in the plurality of penetration parts 11; a wiring layer 20 which contains a lower ground layer 20A that contacts to the plurality of first terminals 51, and is positioned so as to be separated to the thickness direction z from a back surface 102 of the insulation layer 10, and is conducted to the plurality of first terminals 51; a semiconductor element mounted onto the wiring layer 20; and a plurality of second terminals 52 individually covering one part of each of the plurality of first terminals 51. Each of the plurality of penetration parts 11, includes a regulation surface 111 connected to the back surface 102, and regulating a formation of each penetration part 11. Each regulation surface 111 of the plurality of penetration parts 11, includes a first part 111A stood in the thickness direction z from the back surface 102, and one part of each of the plurality of first terminals 51 is directly covered with the first part 111A of any one of each regulation surface 111 of the plurality of penetration parts 11.SELECTED DRAWING: Figure 10

Description

The present invention relates to a semiconductor device.

Patent Document 1 includes an insulating layer made of a material containing a synthetic resin, a wiring layer (conductor layer in Patent Document 1) arranged inside and on the surface of the insulating layer, and a semiconductor chip bonded to the wiring layer. , An example of a semiconductor device including a resin composition in which the semiconductor chip is sealed is disclosed. Although the semiconductor device can be made smaller, the insulating layer and the wiring layer are vulnerable to bending. Therefore, as disclosed in Patent Document 1, in the manufacture of the semiconductor device, a release layer is formed on a support layer such as a metal plate, and an insulating layer and a wiring layer are placed on the release layer. The method of forming is adopted. The support layer is removed after the semiconductor chip is bonded to the wiring layer and the semiconductor chip is resin-sealed. The release layer is formed to prevent damage to the insulating layer and the wiring layer when the support layer is removed. The release layer is made of a metal thin film such as titanium. The release layer is removed by wet etching.

In the manufacture of the semiconductor device, after removing the release layer, a plurality of terminals individually covering a plurality of regions of the wiring layer exposed from the insulating layer may be formed by electroless plating. When the release layer is made of titanium, it becomes difficult to form a plurality of terminals if the release layer is insufficiently removed. Therefore, when trying to completely remove the release layer by wet etching, if titanium is contained in the composition of the wiring layer, the wiring layer may be eroded together with the release layer. If the wiring layer is eroded, it may cause the wiring layer to peel off from the insulating layer. Therefore, in the manufacturing process of the semiconductor device, a measure for suppressing erosion of the wiring layer is required.

Japanese Unexamined Patent Publication No. 2011-124381

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device capable of suppressing erosion of the wiring layer in the manufacturing process of the device.

The semiconductor device provided by the present invention has an insulating layer having a main surface and a back surface facing opposite sides in the thickness direction, a plurality of penetrating portions extending from the main surface to the back surface, and the plurality of penetrating portions. Each of the plurality of first terminals individually housed together with a base layer that is in contact with both the main surface and the plurality of first terminals and is located away from the back surface in the thickness direction. The base layer includes a wiring layer conducting to the first terminal of the above, a semiconductor element mounted on the wiring layer, and a plurality of second terminals individually covering a part of each of the plurality of first terminals. The composition of the above-mentioned composition contains a metal element, each of the plurality of penetrating portions is connected to the main surface and the back surface, and has a defining surface that defines the shape of the penetrating portion. Each of the surfaces has a first portion that rises from the back surface in the thickness direction, and a part of each of the plurality of first terminals is the first portion of any of the defined surfaces of the plurality of penetration portions. It is characterized by being directly covered by the part.

In the practice of the present invention, each of the plurality of first terminals preferably has an upper surface facing the same side as the main surface in the thickness direction, a lower surface facing the opposite side to the upper surface, and the upper surface and the lower surface. The upper surface of the plurality of first terminals is in contact with the base layer, and each of the side surfaces of the plurality of first terminals is any of the defined surfaces of the plurality of penetrating portions. It is in contact with the first part.

In the practice of the present invention, preferably, each of the defined surfaces of the plurality of penetrating portions further has a second portion located between the main surface and the back surface in the thickness direction, and the second portion. Extends from the first portion of any of the defined surfaces of the plurality of penetrating portions in a direction orthogonal to the thickness direction, and a part of each of the plurality of first terminals extends through the plurality of penetrating portions. It is directly covered by the second part of any of the defined surfaces of the part.

In the practice of the present invention, each of the upper surfaces of the plurality of first terminals is in contact with the second portion of any of the defined surfaces of the plurality of penetrating portions.

In the practice of the present invention, the composition of the base layer preferably contains titanium.

In the practice of the present invention, preferably, the wiring layer further includes a main body layer which is laminated on the base layer and contains a metal element, and the composition of the plurality of first terminals contains a metal element and is a main body layer. The composition includes the same metal element contained in the composition of the plurality of first terminals.

In the practice of the present invention, the composition of the plurality of first terminals and the main body layer preferably contains copper.

In the practice of the present invention, the composition of the plurality of first terminals and the main body layer preferably contains nickel.

In the practice of the present invention, preferably, the wiring layer has a plurality of bases including portions individually housed with respect to the plurality of penetration portions, and each of the plurality of bases has the plurality of first terminals. It is in contact with the upper surface of any one of the above.

In the practice of the present invention, preferably, each of the side surfaces of the plurality of first terminals includes an exposed portion that is not covered by the first portion of any of the defined surfaces of the plurality of penetrating portions, and the exposed portion. Is connected to the lower surface of any one of the plurality of first terminals.

In the practice of the present invention, each of the plurality of second terminals preferably has a bottom portion covering the lower surface of any of the plurality of first terminals and the said one of the plurality of first terminals connected to the lower surface. It has a side portion that covers the exposed portion.

In carrying out the present invention, preferably, each of the plurality of bases has an end surface that is flush with the exposed portion of any of the plurality of first terminals, and the side portions of the plurality of second terminals. Each covers the end face of any of the plurality of bases.

Preferably, in the practice of the present invention, the composition of the plurality of second terminals includes nickel and gold.

Preferably, in practicing the present invention, the composition of the plurality of second terminals further comprises palladium.

In the practice of the present invention, preferably, the semiconductor element has a plurality of pads facing the wiring layer, and the plurality of pads are joined to the wiring layer in a state where continuity with the wiring layer is ensured. ing.

In the practice of the present invention, it is preferable that a plurality of electronic components mounted on the wiring layer are further provided, and each of the plurality of electronic components has a pair of electrodes located apart from each other, and the plurality of electronic components are of the plurality of electronic components. Each of the pair of electrodes is joined to the wiring layer in a state where continuity with the wiring layer is ensured.

In the practice of the present invention, a sealing resin is further provided, and the sealing resin is in contact with both the main surface and the wiring layer, and covers the semiconductor element and the plurality of electronic components.

According to the semiconductor device according to the present invention, it is possible to suppress erosion of the wiring layer in the manufacturing process of the device.

Other features and advantages of the present invention will become more apparent with the detailed description given below based on the accompanying drawings.

It is a top view of the semiconductor device which concerns on 1st Embodiment of this invention, and is transmitted through the sealing resin. It is a plan view corresponding to FIG. 1, and is transparent to a plurality of bonding layers, a semiconductor element, a plurality of electronic components, and a sealing resin. It is a bottom view of the semiconductor device shown in FIG. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which follows the VI-VI line of FIG. It is a partially enlarged view of FIG. It is a partially enlarged view of FIG. It is a partially enlarged view of FIG. 1 and is transparent to the wiring layer. FIG. 5 is a cross-sectional view taken along the line XX of FIG. 9 is a cross-sectional view taken along the line XI-XI of FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is a partially enlarged plan view of the semiconductor device which concerns on 2nd Embodiment of this invention, and is transmitted through a wiring layer and a sealing resin. FIG. 2 is a cross-sectional view taken along the line XXVIII-XXVIII of FIG. 27. FIG. 2 is a cross-sectional view taken along the line XXIX-XXIX of FIG. 27.

A mode for carrying out the present invention will be described with reference to the accompanying drawings.

[First Embodiment]
The semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 11. The semiconductor device A10 includes an insulating layer 10, a plurality of first terminals 51, a wiring layer 20, a plurality of bonding layers 39, a semiconductor element 31, a plurality of electronic components 32, a sealing resin 40, and a plurality of second terminals 52. .. The semiconductor device A10 is in the form of a resin package that is surface-mounted on a wiring board. The package type is a QFN (quad flat non-leaded package) characterized in that a plurality of leads do not protrude from the sealing resin 40. Here, FIG. 1 is transparent to the sealing resin 40 for convenience of understanding. FIG. 2 further transmits the plurality of bonding layers 39, the semiconductor element 31, and the plurality of electronic components 32 with respect to FIG. 1 for convenience of understanding. In FIG. 2, the transmitted semiconductor element 31 and the plurality of electronic components 32 are shown by imaginary lines (dashed-dotted lines), respectively. 9 is transparent to the wiring layer 20 with respect to FIG. 1 for convenience of understanding.

In the description of the semiconductor device A10, for convenience, the thickness direction of the insulating layer 10 is referred to as "thickness direction z". The direction orthogonal to the thickness direction z is called the "first direction x". The direction orthogonal to both the thickness direction z and the first direction x is referred to as a "second direction y". As shown in FIG. 1, the semiconductor device A10 has a rectangular shape when viewed along the thickness direction z.

As shown in FIGS. 1 to 6, a wiring layer 20 is arranged on the insulating layer 10. The insulating layer 10 is made of a material containing polyimide. As the material of the other insulating layer 10, a material mainly composed of an organic compound such as a material containing polybenzoxazole, a material containing a phenol resin, and a material containing a polyamide can be adopted. The insulating layer 10 has a main surface 101, a back surface 102, and a plurality of through portions 11.

As shown in FIGS. 4 to 6, the main surface 101 and the back surface 102 face opposite to each other in the thickness direction z. The main surface 101 faces the semiconductor element 31 and the plurality of electronic components 32. The back surface 102 is exposed to the outside of the semiconductor device A10 and faces the target wiring board when the semiconductor device A10 is mounted. As shown in FIG. 5, the plurality of penetrating portions 11 penetrate the insulating layer 10 from the main surface 101 to the back surface 102 in the thickness direction z.

As shown in FIGS. 9 to 11, each of the plurality of penetration portions 11 has a defined surface 111. The defined surface 111 is connected to the main surface 101 and the back surface 102. The defining surface 111 defines the shape of the target penetrating portion 11 among the plurality of penetrating portions 11. In the semiconductor device A10, each of the defined surfaces 111 of the plurality of penetrating portions 11 has a first portion 111A. The first part 111A rises from the back surface 102 in the thickness direction z.

As shown in FIGS. 2 to 6 (excluding FIG. 4), the plurality of first terminals 51 are individually housed in the plurality of penetrating portions 11 of the insulating layer 10. In the example shown by the semiconductor device A10, each of the plurality of first terminals 51 has a rectangular shape when viewed along the thickness direction z. The composition of the plurality of first terminals 51 includes a metallic element. The metal element is copper (Cu) or nickel (Ni).

As shown in FIGS. 9 to 11, each of the plurality of first terminals 51 has an upper surface 511, a lower surface 512, and a side surface 513. The upper surface 511 faces the same side as the main surface 101 of the insulating layer 10 in the thickness direction z. The lower surface 512 faces the opposite side of the upper surface 511. The side surface 513 is connected to the top surface 511 and the side surface 513. A part of each of the plurality of first terminals 51 is directly covered with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. In the semiconductor device A10, each of the side surfaces 513 of the plurality of first terminals 51 is in contact with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. Each of the side surfaces 513 of the plurality of first terminals 51 includes an exposed portion 513A. The exposed portion 513A is a region not covered by the first portion 111A of any of the defined surfaces 111 of the plurality of penetrating portions 11. The exposed portion 513A is connected to the lower surface 512 of any one of the plurality of first terminals 51.

As shown in FIGS. 2 to 6 (excluding FIG. 3), the wiring layer 20 is arranged on the main surface 101 of the insulating layer 10 and the plurality of penetrating portions 11 of the insulating layer 10. The wiring layer 20 constitutes a part of a conductive path between the semiconductor element 31, the plurality of electronic components 32, and the wiring board on which the semiconductor device A10 is mounted. The wiring layer 20 is conductive to the plurality of first terminals 51. As shown in FIGS. 7 to 11 (excluding FIG. 9), the wiring layer 20 includes a base layer 20A and a main body layer 20B. Each composition of the base layer 20A and the main body layer 20B contains a metal element.

The base layer 20A is in contact with the main surface 101, the defined surfaces 111 of the plurality of penetrating portions 11, and the upper surface 511 of the plurality of first terminals 51. The base layer 20A is composed of a barrier layer in contact with these elements and a seed layer laminated on the barrier layer. The composition of the barrier layer contains titanium (Ti). Therefore, the composition of the base layer 20A includes titanium. The composition of the seed layer is the same as the composition of the main body layer 20B. The base layer 20A is located away from the back surface 102 of the insulating layer 10 in the thickness direction z. The main body layer 20B is laminated on the base layer 20A. In the wiring layer 20, the main body layer 20B is the main conductive path. The composition of the main body layer 20B contains the same metal element contained in the composition of the plurality of first terminals 51. Therefore, the composition of the main body layer 20B contains copper or nickel.

As shown in FIGS. 2, 5 and 6, the wiring layer 20 has a plurality of base portions 21, a plurality of main body portions 22, and a plurality of bump portions 23. Of these, the plurality of base portions 21 and the plurality of main body portions 22 are composed of a base layer 20A and a main body layer 20B as shown in FIGS. 7 to 11 (however, excluding FIG. 9).

As shown in FIGS. 2, 10 and 11, the plurality of bases 21 are individually housed in the plurality of through portions 11 of the insulating layer 10 and in the thickness direction from the main surface 101 of the insulating layer 10. Includes a portion protruding to z. Each of the plurality of bases 21 is laminated on any of the plurality of first terminals 51. Therefore, each of the plurality of bases 21 is in contact with the upper surface 511 of any one of the plurality of first terminals 51. When viewed along the thickness direction z, the shape and size of each of the plurality of bases 21 is equal to the shape and size of any one of the plurality of first terminals 51 overlapping the base 21. As shown in FIG. 10, each of the plurality of bases 21 has an end face 211. The end face 211 is flush with the exposed portion 513A of any of the plurality of first terminals 51.

As shown in FIGS. 2 to 6 (however, excluding FIG. 3), the plurality of main body portions 22 are arranged on the main surface 101 of the insulating layer 10. Some of the plurality of body portions 22 are connected to any of the plurality of base portions 21.

As shown in FIGS. 7 and 8, the plurality of bump portions 23 are arranged on the main body layer 20B. The plurality of bump portions 23 project from the main body layer 20B in the thickness direction z. The composition of the plurality of bump portions 23 includes the same metal element contained in the composition of the main body layer 20B. Therefore, the composition of the plurality of bump portions 23 includes copper or nickel. As shown in FIG. 2, the plurality of bump portions 23 includes a plurality of first bump portions 231 and a plurality of second bump portions 232. Each of the plurality of first bump portions 231 is arranged on the main body layer 20B constituting any of the plurality of main body portions 22. Each of the plurality of second bump portions 232 is arranged on the main body layer 20B constituting any of the plurality of base portions 21 or on the main body layer 20B constituting any of the plurality of main body portions 22. .. When viewed along the thickness direction z, the size of each of the plurality of first bump portions 231 is smaller than the size of each of the plurality of second bump portions 232.

As shown in FIGS. 4 to 8, the plurality of bonding layers 39 are individually arranged with respect to the plurality of bump portions 23 of the wiring layer 20. The plurality of bonding layers 39 have conductivity. Each of the plurality of bonding layers 39 is composed of a nickel layer in contact with any of the plurality of bump portions 23 and an alloy layer containing tin (Sn) laminated on the nickel layer. The alloy layer is made of, for example, a tin-silver (Ag) -based alloy or a tin-antimony (Sb) -based alloy. The plurality of bonding layers 39 includes a plurality of first bonding layers 391 and a plurality of second bonding layers 392. The plurality of first bonding layers 391 are individually arranged with respect to the plurality of first bump portions 231 among the plurality of bump portions 23. The plurality of second bonding layers 392 are individually arranged with respect to the plurality of second bump portions 232 among the plurality of bump portions 23.

As shown in FIGS. 4 to 7 (however, excluding FIG. 5), the semiconductor element 31 is mounted on a plurality of first bump portions 231 among the plurality of bump portions 23 of the wiring layer 20. The semiconductor element 31 is a flip chip mounting type element. In the example shown by the semiconductor device A10, the semiconductor element 31 is an LSI. The semiconductor element 31 has a plurality of pads 311. The plurality of pads 311 are conductive to a circuit configured inside the semiconductor element 31. Each of the plurality of pads 311 faces any of the plurality of first bump portions 231. As shown in FIG. 7, each of the plurality of pads 311 is bonded to one of the plurality of first bump portions 231 via any of the plurality of first bonding layers 391 among the plurality of bonding layers 39. There is. That is, the plurality of pads 311 are joined to the wiring layer 20 in a state where continuity with the wiring layer 20 is ensured. As a result, the semiconductor element 31 is electrically connected to the wiring layer 20.

As shown in FIGS. 2 and 5, each of the plurality of electronic components 32 is mounted on two adjacent second bump portions 232 of the plurality of bump portions 23 of the wiring layer 20. The plurality of electronic components 32 are surface mount type and chip type. Each of the plurality of electronic components 32 corresponds to any of passive elements such as resistors, capacitors and inductors, and diodes. In the example shown by the semiconductor device A10, when any one of the plurality of electronic components 32 is a resistor, a thick film (metal glaze film) type resistor is assumed. In addition, when any one of the plurality of electronic components 32 is a capacitor, a ceramic capacitor is assumed.

As shown in FIGS. 1 and 5, each of the plurality of electronic components 32 has a pair of electrodes 321. The pair of electrodes 321 are located apart from each other. As shown in FIG. 8, each of the pair of electrodes 321 of the plurality of electronic components 32 has a plurality of second bump portions 232 via any of the plurality of second bonding layers 392 among the plurality of bonding layers 39. It is joined to either. That is, each of the pair of electrodes 321 of the plurality of electronic components 32 is joined to the wiring layer 20 in a state where continuity with the wiring layer 20 is ensured. As a result, the plurality of electronic components 32 are electrically connected to the wiring layer 20.

As shown in FIGS. 4 to 6, the sealing resin 40 is in contact with both the main surface 101 of the insulating layer 10 and the wiring layer 20. The sealing resin 40 covers the wiring layer 20 (however, a part of the plurality of bases 21 is excluded), the semiconductor element 31, and the plurality of electronic components 32. The sealing resin 40 is made of an insulating material containing, for example, a black epoxy resin.

As shown in FIGS. 3 to 6 (excluding FIG. 4), the plurality of second terminals 52 individually cover a part of each of the plurality of first terminals 51 and are outside the semiconductor device A10. On the other hand, it is exposed. The semiconductor device A10 is mounted on the wiring board by joining each of the plurality of second terminals 52 to the wiring board via solder. In the semiconductor device A10, each of the plurality of second terminals 52 is laminated in the order of the nickel layer, the palladium (Pd) layer, and the gold (Au) layer in the order closest to any one of the plurality of first terminals 51. It is composed of a metal layer. Therefore, the composition of the plurality of second terminals 52 includes nickel, palladium and gold.

As shown in FIGS. 9 and 10, each of the plurality of second terminals 52 has a bottom portion 521 and a side portion 522. The bottom portion 521 covers the lower surface 512 of any one of the plurality of first terminals 51. The side portion 522 is connected to the bottom portion 521 of any one of the plurality of first terminals 51, and extends from the bottom portion 521 in the thickness direction z. Each of the side portions 522 of the plurality of second terminals 52 covers the exposed portion 513A of any of the plurality of first terminals 51 and the end surface 211 of any of the plurality of bases 21 of the wiring layer 20.

Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 12 to 26. The cross-sectional positions of FIGS. 12 to 26 are the same as the cross-sectional positions of FIG.

First, as shown in FIG. 12, the temporary fixing layer 801 is applied to the surface of the base material 80 on one side in the thickness direction z. The base material 80 is a glass plate. The base material 80 may be a silicon wafer as well as a glass plate. The temporary fixing layer 801 is made of a material containing an organic compound.

Next, as shown in FIG. 13, a peeling layer 802 covering the entire temporary fixing layer 801 is formed. The release layer 802 is composed of a metal thin film that is in contact with the temporary fixing layer 801 and is made of titanium, and a metal thin film that is laminated on the metal thin film and is made of copper. The release layer 802 is formed by forming each of these metal thin films by a sputtering method.

Next, as shown in FIG. 14, an insulating layer 82 covering the release layer 802 is formed. The insulating layer 82 has a plurality of penetrating portions 821 penetrating the insulating layer 82 in the thickness direction z. The insulating layer 82 is made of a material containing photosensitive polyimide. The insulating layer 82 is formed by applying the material to the entire peeling layer 802 and the plurality of conductive layers 81 using a spin coater or the like, and then performing lithographic patterning on the material. As a result, a plurality of penetrating portions 821 are formed in the insulating layer 82.

Next, as shown in FIG. 15, a plurality of conductive layers 81 are formed in contact with the release layer 802 and individually housed in the plurality of penetrating portions 821 of the insulating layer 82. The plurality of conductive layers 81 are made of copper. The plurality of conductive layers 81 are formed by electrolytic plating with the insulating layer 82 as a mask and the release layer 802 as a conductive path. By this step, the peripheral surface of the insulating layer 82 surrounding each of the plurality of through portions 821 is uniformly in contact with any side surface of the plurality of conductive layers 81.

Next, as shown in FIGS. 16 to 18, a wiring layer 83 is formed on the insulating layer 82 and a part of each of the plurality of conductive layers 81 exposed from the plurality of through portions 821 of the insulating layer 82. .. The steps of forming the wiring layer 83 include a step of forming the base layer 83A shown in FIG. 16, a step of forming the plurality of main body layers 83B shown in FIG. 17, and a step of forming the plurality of bump layers 83C shown in FIG. And include.

First, as shown in FIG. 16, a base layer 83A is formed which covers the insulating layer 82 and a part of each of the plurality of conductive layers 81 exposed from the plurality of penetrating portions 821 of the insulating layer 82. The base layer 83A is formed on the entire barrier layer after a barrier layer is formed on the entire of the insulating layer 82 and a part of each of the plurality of conductive layers 81 exposed from the plurality of through portions 821 by a sputtering method. It is formed by forming a seed layer into a film by a sputtering method. The barrier layer is made of titanium having a thickness of 100 nm to 300 nm. The seed layer is made of copper having a thickness of 200 nm to 600 nm.

Next, as shown in FIG. 17, a plurality of main body layers 83B are formed on the base layer 83A. The plurality of body layers 83B are made of copper. The plurality of main body layers 83B are formed by electrolytic plating using the base layer 83A as a conductive path after performing lithography patterning on the base layer 83A. By going through this step, each of the plurality of through portions 821 of the insulating layer 82 is in a state of being filled with any of the plurality of conductive layers 81, the base layer 83A, and the plurality of main body layers 83B. ..

Next, as shown in FIG. 18, a plurality of bump layers 83C are formed on the plurality of main body layers 83B. The plurality of bump layers 83C are made of copper. The plurality of bump layers 83C are formed by lithographic patterning on the base layer 83A and the plurality of main body layers 83B, and then electrolytic plating using the base layer 83A and the plurality of main body layers 83B as conductive paths. By going through this step, the formation of the wiring layer 83 is completed.

Next, as shown in FIG. 19, a plurality of bonding layers 39 are individually formed on the plurality of bump layers 83C of the wiring layer 83. In this step, first, lithography patterning is performed on the base layer 83A, the plurality of main body layers 83B, and the plurality of bump layers 83C. Next, the nickel layer is formed by electrolytic plating using the base layer 83A, the plurality of main body layers 83B, and the plurality of bump layers 83C as conductive paths. Finally, by forming an alloy layer containing tin on the nickel layer by electrolytic plating using the base layer 83A, the plurality of main body layers 83B, the plurality of bump layers 83C, and the nickel layer as a conductive path, a plurality of layers are formed. The formation of the bonding layer 39 is completed.

Then, as shown in FIG. 20, a part of the base layer 83A is removed. The target of removal of the base layer 83A is a portion where the plurality of main body layers 83B are not laminated. The base layer 83A is removed by wet etching with a mixed solution of _{sulfuric acid (H 2} SO ₄ ) and hydrogen peroxide (H ₂ O _2). By going through this step, the base layer 83A laminated and remaining on the insulating layer 82 and a part of the plurality of main body layers 83B laminated on the base layer 83A are formed on a plurality of wiring layers 20 of the semiconductor device A10. It becomes the main body 22. In addition, the plurality of bump layers 83C serve as the plurality of bump portions 23 of the wiring layer 20 of the semiconductor device A10.

Next, as shown in FIG. 21, the semiconductor element 31 and the plurality of electronic components 32 (for convenience of illustration, the electronic component 32 shown in FIG. 21 is singular) are joined to the wiring layer 20 via the plurality of bonding layers 39. To do. Of these, the semiconductor element 31 is bonded to the wiring layer 20 by flip-chip bonding. First, each of the pair of electrodes 321 of the plurality of electronic components 32 is temporarily attached to one of the plurality of second bonding layers 392 among the plurality of bonding layers 39. Next, using a collet, the plurality of pads 311 of the semiconductor element 31 are temporarily attached to the plurality of first bonding layers 391 among the plurality of bonding layers 39 individually. Next, the plurality of bonding layers 39 are melted by reflow. Finally, by solidifying the melted plurality of bonding layers 39 by cooling, the bonding of the semiconductor element 31 and the plurality of electronic components 32 to the wiring layer 20 is completed.

Next, as shown in FIG. 22, the sealing resin 84 in contact with the insulating layer 82 and the wiring layer 20 is formed. The sealing resin 84 is made of a material containing a black epoxy resin. The sealing resin 84 is formed by compression molding. By going through this step, the wiring layer 20, the semiconductor element 31, and the plurality of electronic components 32 (for convenience of illustration, the number of the electronic components 32 shown in FIG. 22 is singular) are covered with the sealing resin 84. At the same time, the wiring layer 83 located at the plurality of through portions 821 of the insulating layer 82 is also covered with the sealing resin 84.

Next, as shown in FIG. 23, the tape 85 is attached to the surface of the sealing resin 84 facing the thickness direction z, and then the base material 80 and the temporary fixing layer 801 are removed. First, the tape 85 is attached to the surface of the sealing resin 84. The tape 85 is a dicing tape. The tape 85 is located on the side opposite to the insulating layer 82 with respect to the sealing resin 84 in the thickness direction z. Next, the base material 80 is irradiated with a laser. As a result, the bond between the base material 80 and the temporary fixing layer 801 is weakened, and the base material 80 can be peeled off from the temporary fixing layer 801. Finally, by irradiating the temporary fixing layer 801 with plasma, the temporary fixing layer 801 adhering to the release layer 802 is removed.

Then, as shown in FIG. 24, the release layer 802 is removed. The release layer 802 is removed by wet etching with a mixed solution of sulfuric acid and hydrogen peroxide. By going through this step, a part of the plurality of conductive layers 81 can be visually recognized from the insulating layer 82.

Next, as shown in FIG. 25, the plurality of conductive layers 81, the insulating layer 82, the wiring layer 83 located at the plurality of through portions 821 of the insulating layer 82, and the sealing resin 84 are placed in the first direction x and. It is divided into a plurality of pieces by cutting in a grid pattern along both directions of the second direction y. A dicing blade or the like is used for cutting. However, in this step, the tape 85 is not cut. Therefore, a groove G is formed between the two adjacent pieces. Through this step, the individual insulating layer 82 becomes the insulating layer 10 of the semiconductor device A10, and the individual sealing resin 84 becomes the sealing resin 40 of the semiconductor device A10. In addition, the plurality of individual conductive layers 81 serve as the plurality of first terminals 51 of the semiconductor device A10, and the individual wiring layer 83 serves as the plurality of bases 21 of the wiring layer 20 of the semiconductor device A10. It becomes. Further, a part of the plurality of bases 21 can be visually recognized from the sealing resin 40.

Finally, as shown in FIG. 26, a plurality of second terminals 52 are formed which individually cover each part of the plurality of first terminals 51 and each part of the plurality of bases 21. The plurality of second terminals 52 are formed by electroless plating. Through the above steps, the semiconductor device A10 is manufactured.

Next, the action and effect of the semiconductor device A10 will be described.

In the semiconductor device A10, a plurality of first terminals 51 individually housed in the plurality of through portions 11 of the insulating layer 10, a wiring layer 20 conducting conduction to the plurality of first terminals 51, and a plurality of first terminals. A plurality of second terminals 52 that individually cover each part of the 51 are provided. The wiring layer 20 includes a base layer 20A that is in contact with the plurality of first terminals 51 and is located away from the back surface 102 of the insulating layer 10 in the thickness direction z. Each of the plurality of penetrating portions 11 has a defining surface 111 that is connected to the back surface 102 and defines the shape of the penetrating portion 11. Each of the defined surfaces 111 of the plurality of penetrating portions 11 has a first portion 111A rising from the back surface 102 in the thickness direction z. A part of each of the plurality of first terminals 51 is directly covered with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. As a result, in the process of removing the release layer 802 shown in FIG. 24 in the manufacturing process of the semiconductor device A10, the plurality of conductive layers 81 prevent the etching solution from reaching the base layer 20A (base layer 83A in FIG. 24). Will be done. The plurality of conductive layers 81 are elements that become a plurality of first terminals 51 in the step of individualization shown in FIG. 25. Therefore, according to the semiconductor device A10, it is possible to suppress the erosion of the wiring layer 20 in the manufacturing process of the semiconductor device A10.

Each of the plurality of first terminals 51 has a side surface 513 connected to an upper surface 511 and a lower surface 512. Each of the side surfaces 513 of the plurality of first terminals 51 is in contact with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. As a result, in the process of removing the release layer 802 shown in FIG. 24 in the manufacturing process of the semiconductor device A10, the intrusion of the etching solution is caused by each of the side surfaces 513 of the plurality of first terminals 51 and a plurality of surfaces in contact with the side surface 513. It will be blocked at the boundary with any first portion 111A of the defining surface 111 of the penetrating portion 11.

The effect of suppressing the erosion of the wiring layer 20 by the plurality of first terminals 51 becomes more remarkable when the composition of the release layer 802 and the composition of the base layer 20A both contain titanium.

Each of the side surfaces 513 of the plurality of first terminals 51 includes an exposed portion 513A that is not covered by any first portion 111A of the defined surface 111 of the plurality of through portions 11. The exposed portion 513A is connected to the lower surface 512 of any one of the plurality of first terminals 51. On the other hand, each of the plurality of second terminals 52 has a bottom portion 521 and a side portion 522 covering the exposed portion 513A of any of the plurality of first terminals 51. As a result, when the semiconductor device A10 is mounted on the wiring board by soldering, the solder adheres not only to the bottom portion 521 but also to the side portion 522. Thereby, the mounting strength of the semiconductor device A10 on the wiring board can be improved.

The wiring layer 20 has a plurality of bases 21 including portions individually housed with respect to the plurality of penetrations 11. Each of the plurality of bases 21 has an end surface 211 that is flush with any of the exposed portions 513A of the plurality of first terminals 51. Each of the side portions 522 of the plurality of second terminals 52 covers the end surface 211 of any of the plurality of bases 21. As a result, the size of each of the side portions 522 of the plurality of second terminals 52 in the thickness direction z becomes larger. Therefore, when the semiconductor device A10 is mounted on the wiring board by soldering, the volume of the solder adhering to the side portion 522 becomes larger. Therefore, the mounting strength of the semiconductor device A10 on the wiring board can be further improved.

The composition of the plurality of second terminals 52 preferably includes nickel and gold. As a result, when the semiconductor device A10 is mounted on the wiring board by soldering, the wiring layer 20 and the plurality of first terminals 51 are protected from the thermal impact of the solder, and the wettability of the solder is improved. By including palladium in addition to nickel and gold in the composition of the plurality of second terminals 52, the wettability of the solder becomes better.

The semiconductor device A10 further includes a plurality of electronic components 32 mounted on the wiring layer 20. The plurality of electronic components 32 are joined to the wiring layer 20 in a state where continuity with the wiring layer 20 is ensured. As a result, the plurality of electronic components 32 can take charge of voltage adjustment of the electric signal input to the semiconductor element 31 and the like. Therefore, the number of electronic components mounted on the wiring board together with the semiconductor device A10 can be reduced.

[Second Embodiment]
The semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. 27 to 29. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are designated by the same reference numerals, and redundant description will be omitted. Here, FIG. 27 is a partially enlarged plan view of the semiconductor device A10 described above, which corresponds to FIG. 9, and is transparent to the wiring layer 20 and the sealing resin 40.

In the semiconductor device A20, the configuration of the plurality of penetrating portions 11 of the insulating layer 10 is different from the configuration of the semiconductor device A10 described above.

As shown in FIGS. 28 and 29, in the semiconductor device A20, each of the defined surfaces 111 of the plurality of penetrating portions 11 has a first portion 111A, a second portion 111B, and a third portion 111C. The second part 111B is located between the main surface 101 and the back surface 102 of the insulating layer 10 in the thickness direction z. The second portion 111B extends in a direction orthogonal to the thickness direction z from the first portion 111A of any of the defined surfaces 111 of the plurality of penetrating portions 11. The third part 111C is connected to the second part 111B of any of the defined surfaces 111 of the plurality of penetrating parts 11 and the main surface 101. The third part 111C has a convex curved surface.

As shown in FIGS. 28 and 29, in the semiconductor device A20, a part of each of the plurality of first terminals 51 is the first portion 111A of any of the defined surfaces 111 of the plurality of penetrating portions 11, and the said definition. It is directly covered with the second part 111B of the surface 111. Each of the side surfaces 513 of the plurality of first terminals 51 is in contact with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. In addition, each of the upper surfaces 511 of the plurality of first terminals 51 is in contact with the second portion 111B of any of the defined surfaces 111 of the plurality of penetrating portions 11. As a result, each of the upper surfaces 511 of the plurality of first terminals 51 is the second portion 111B and the third portion of the defining surface 111 that defines the shape of any of the plurality of penetrating portions 11 in which the first terminal 51 is housed. The structure is such that the 111C is in contact with the eaves-shaped portion of the insulating layer 10.

Next, the action and effect of the semiconductor device A20 will be described.

In the semiconductor device A20, a plurality of first terminals 51 individually housed in the plurality of through portions 11 of the insulating layer 10, a wiring layer 20 conducting conduction to the plurality of first terminals 51, and a plurality of first terminals. A plurality of second terminals 52 that individually cover each part of the 51 are provided. The wiring layer 20 includes a base layer 20A that is in contact with the plurality of first terminals 51 and is located away from the back surface 102 of the insulating layer 10 in the thickness direction z. Each of the plurality of penetrating portions 11 has a defining surface 111 that is connected to the back surface 102 and defines the shape of the penetrating portion 11. Each of the defined surfaces 111 of the plurality of penetrating portions 11 has a first portion 111A rising from the back surface 102 in the thickness direction z. A part of each of the plurality of first terminals 51 is directly covered with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. Therefore, the semiconductor device A20 can also suppress the erosion of the wiring layer 20 in the manufacturing process of the semiconductor device A20.

In the semiconductor device A20, each of the defined surfaces 111 of the plurality of penetrating portions 11 has a second portion 111B located between the main surface 101 and the back surface 102 of the insulating layer 10 in the thickness direction z. The second portion 111B extends in a direction orthogonal to the thickness direction z from the first portion 111A of any of the defined surfaces 111 of the plurality of penetrating portions 11. A part of each of the plurality of first terminals 51 is directly covered by the first portion 111A of any of the defining surfaces 111 of the plurality of penetrating portions 11 and the second portion 111B of the defining surface 111. As a result, in the process of removing the release layer 802 shown in FIG. 24 in the manufacturing process of the semiconductor device A20, the etching solution reaches the base layer 20A by the plurality of first terminals 51 as compared with the case of the semiconductor device A10. It is strongly blocked.

In the semiconductor device A20, each of the side surfaces 513 of the plurality of first terminals 51 is in contact with the first portion 111A of any of the defined surfaces 111 of the plurality of through portions 11. In addition, each of the upper surfaces 511 of the plurality of first terminals 51 is in contact with the second portion 111B of any of the defined surfaces 111 of the plurality of penetrating portions 11. As a result, in the process of removing the release layer 802 shown in FIG. 24 in the manufacturing process of the semiconductor device A20, the intrusion of the etching solution is caused by each of the upper surfaces 511 of the plurality of first terminals 51 and a plurality of contacts with the upper surface 511. The boundary between the penetrating portion 11 and the second portion 111B of any of the defining surfaces 111 of the penetrating portion 11 is also blocked. Therefore, the effect of the semiconductor device A20 to prevent the etching solution from reaching the base layer 20A is further improved as compared with the case of the semiconductor device A10.

The present invention is not limited to the semiconductor device A10 and the semiconductor device A20 described above. The specific configuration of each part of the present invention can be freely redesigned.

A10, A20: Semiconductor device 10: Insulation layer 101: Main surface 102: Back surface 11: Penetration part 111: Specified surface 111A: First part 111B: Second part 111C: Third part 20: Wiring layer 20A: Underlayer 20B: Main body layer 21: Base 211: End face 22: Main body 23: Bump part 231: First bump part 232: Second bump part 31: Semiconductor element 311: Pad 32: Electronic component 321: Electrode 39: Bonding layer 391: First Bonding layer 392: Second bonding layer 40: Encapsulating resin 51: First terminal 511: Top surface 512: Bottom surface 513: Side surface 513A: Exposed part 52: Second terminal 521: Bottom part 522: Side part 80: Base material 801: Temporary Fixed layer 802: Peeling layer 81: Conductive layer 82: Insulating layer 821: Penetration part 83: Wiring layer 83A: Underlayer layer 83B: Main body layer 83C: Bump layer 84: Encapsulating resin 85: Tape G: Groove z: Thickness direction x: 1st direction y: 2nd direction

Claims (17)

An insulating layer having a main surface and a back surface facing opposite sides in the thickness direction, and a plurality of penetrating portions extending from the main surface to the back surface.
A plurality of first terminals individually housed in the plurality of penetrating portions,
A wiring layer that includes a base layer that is in contact with both the main surface and the plurality of first terminals and is located away from the back surface in the thickness direction, and is conductive to the plurality of first terminals.
The semiconductor element mounted on the wiring layer and
A plurality of second terminals that individually cover a part of each of the plurality of first terminals are provided.
The composition of the base layer contains metal elements and contains
Each of the plurality of penetrating portions has a defining surface that is connected to the main surface and the back surface and defines the shape of the penetrating portion.
Each of the defined surfaces of the plurality of penetrating portions has a first portion that rises from the back surface in the thickness direction.
A semiconductor device, wherein a part of each of the plurality of first terminals is directly covered with the first portion of any of the defined surfaces of the plurality of penetration portions. Each of the plurality of first terminals has an upper surface facing the same side as the main surface in the thickness direction, a lower surface facing the side opposite to the upper surface, and a side surface connected to the upper surface and the lower surface. ,
The upper surface of the plurality of first terminals is in contact with the base layer.
The semiconductor device according to claim 1, wherein each of the side surfaces of the plurality of first terminals is in contact with the first portion of any of the defined surfaces of the plurality of penetrating portions. Each of the defined surfaces of the plurality of penetrations further comprises a second portion located between the main surface and the back surface in the thickness direction.
The second portion extends in a direction orthogonal to the thickness direction from the first portion of any of the defined surfaces of the plurality of penetrating portions.
The semiconductor device according to claim 2, wherein a part of each of the plurality of first terminals is directly covered by the second portion of any of the defined surfaces of the plurality of penetrating portions. The semiconductor device according to claim 3, wherein each of the upper surfaces of the plurality of first terminals is in contact with the second portion of any of the defined surfaces of the plurality of penetrating portions. The semiconductor device according to any one of claims 2 to 4, wherein the composition of the base layer contains titanium. The wiring layer further includes a main body layer laminated on the base layer and containing a metal element.
The composition of the plurality of first terminals contains a metallic element and contains metal elements.
The semiconductor device according to any one of claims 2 to 5, wherein the composition of the main body layer contains the same metal element contained in the composition of the plurality of first terminals. The semiconductor device according to claim 6, wherein the composition of the plurality of first terminals and the main body layer contains copper. The semiconductor device according to claim 6, wherein the composition of the plurality of first terminals and the main body layer contains nickel. The wiring layer has a plurality of bases including portions individually housed with respect to the plurality of penetrations.
The semiconductor device according to any one of claims 6 to 8, wherein each of the plurality of bases is in contact with the upper surface of any of the plurality of first terminals. Each of the side surfaces of the plurality of first terminals includes an exposed portion that is not covered by the first portion of any of the defined surfaces of the plurality of penetration portions.
The semiconductor device according to claim 9, wherein the exposed portion is connected to the lower surface of any one of the plurality of first terminals. Each of the plurality of second terminals includes a bottom portion covering the lower surface of any of the plurality of first terminals, and a side portion covering the exposed portion of any of the plurality of first terminals connected to the lower surface. The semiconductor device according to claim 10. Each of the plurality of bases has an end face that is flush with the exposed portion of any of the plurality of first terminals.
The semiconductor device according to claim 11, wherein each of the side portions of the plurality of second terminals covers the end face of any one of the plurality of base portions. The semiconductor device according to any one of claims 6 to 12, wherein the composition of the plurality of second terminals includes nickel and gold. The semiconductor device according to claim 13, wherein the composition of the plurality of second terminals further includes palladium. The semiconductor element has a plurality of pads facing the wiring layer, and has a plurality of pads.
The semiconductor device according to any one of claims 1 to 14, wherein the plurality of pads are joined to the wiring layer in a state where continuity with the wiring layer is ensured. Further equipped with a plurality of electronic components mounted on the wiring layer,
Each of the plurality of electronic components has a pair of electrodes located apart from each other.
The semiconductor device according to claim 15, wherein each of the pair of electrodes of the plurality of electronic components is joined to the wiring layer while ensuring continuity with the wiring layer. With more sealing resin,
The semiconductor device according to claim 16, wherein the sealing resin is in contact with both the main surface and the wiring layer, and covers the semiconductor element and the plurality of electronic components.

Images